Features
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Two Different IF Receiving Bandwidth Versions are Available (BIF = 300 kHz or 600 kHz)
5V to 20V Automotive-Compatible Data Interface
IC Condition Indicator, Sleep or Active Mode
Data Clock Available for Manchester- and Bi-phase-coded Signals
Fully Integrated VCO
Supply Voltage 4.5V to 5.5V, Operating Temperature Range -40°C to +105°C
Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB
ESD Protection According to MIL-STD. 883 (2KV HBM)
High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW
Front-end Filter; Up to 40 dB is Achievable with State-of-the-art SAWs
Communication to Microcontroller Possible Via a Single, Bi-directional Data Line
Power Management (Polling) is also Possible by Means of a Separate Pin Via the
Microcontroller
Programmable Digital Noise Suppression
SSO20 Package
UHF ASK/FSK
Receiver
ATA5743
Benefits
• Low Power Consumption Due to Configurable Self Polling with a
Programmable Time frame Check
• High Sensitivity, Especially at Low Data Rates
• Minimal External Circuitry Requirements, no RF Components on the PC Board Except
Matching to the Receiver Antenna
• Sensitivity Reduction Possible Even While Receiving
• Low-cost Solution Due to High Integration Level
1. Description
The ATA5743 is a multi-chip PLL receiver device supplied in an SSO20 package. It
has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The
receiver is well suited to operate with Atmel's PLL RF transmitter U2741B. Its main
applications are in the areas of telemetering, security technology, and keyless-entry
systems. It can be used in the frequency receiving range of f0 = 300 MHz to 450 MHz
for ASK or FSK data transmission. All the statements made below refer to
433.92 MHz and 315 MHz applications.
Rev. 4839B–RKE–08/05
2. System Block Diagram
Figure 2-1.
System Block Diagram
UHF ASK/FSK
Remote Control Receiver
UHF ASK/FSK
Remote Control Transmitter
ATA5743
ATA575x
XTO
Demod
Control
1...5
Microcontroller
PLL
Antenna
Antenna
VCO
PLL
Power
amp.
LNA
XTO
VCO
3. Pin Configuration
Figure 3-1.
Pinning SSO20
SENS
IC_ACTIVE
CDEM
AVCC
TEST
AGND
MIXVCC
LNAGND
LNA_IN
NC
2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA
POLLING/_ON
DGND
DATA_CLK
MODE
DVCC
XTO
LFGND
LF
LFVCC
ATA5743
4839B–RKE–08/05
ATA5743
Table 3-1.
Pin Description
Pin
Symbol
Function
1
SENS
2
IC_ACTIVE
3
CDEM
4
AVCC
Analog power supply
5
TEST
Test pin, during operation at GND
6
AGND
Analog ground
7
MIXVCC
8
LNAGND
9
LNA_IN
10
NC
11
LFVCC
Sensitivity-control resistor
IC condition indicator
Low = sleep mode
High = active mode
Lower cut-off frequency data filter
Power supply mixer
High-frequency ground LNA and mixer
RF input
Not connected
Power supply VCO
12
LF
13
LFGND
Loop filter
14
XTO
15
DVCC
Digital power supply
16
MODE
Selecting 433.92 MHz/315 MHz
Low: fXT0 = 4.90625 MHz (USA)
High: fXT0 = 6.76438 MHz (Europe)
17
DATA_CLK
18
DGND
19
POLLING/_ON
20
DATA
Ground VCO
Crystal oscillator
Bit clock of data stream
Digital ground
Selects polling or receiving mode
Low: receiving mode
High: polling mode
Data output/configuration input
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Figure 3-2.
Block Diagram
FSK/ASK
Demodulator
and data filter
CDEM
RSSI
AVCC
Dem_out
Data
Interface
DATA
Limiter out
POLLING/_ON
SENS
IF Amp
Sensitivity
reduction
Polling circuit
and
control logic
AGND
TEST
DATA_CLK
MODE
4. Order
DGND
FE
CLK
DVCC
IC_ACTIVE
LPF
3 MHz
MIXVCC
Standby logic
LFGND
LNAGND
LFVCC
IF Amp
LPF
3 MHz
VCO
XTO
XTO
f
LNA_IN
LNA
LF
64
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ATA5743
4. RF Front-end
The RF front-end of the receiver is a heterodyne configuration that converts the input signal into
a 1 MHz IF signal. As seen in Figure 3-2 on page 4, the front-end consists of an LNA (Low-Noise
Amplifier), an LO (Local Oscillator), a mixer, and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF,
and is then divided by 64. The divided frequency is compared to fXTO by the phase frequency
detector. The current output of the phase frequency detector is connected to a passive loop filter
and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF
is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using
the following formula: fXTO = fLO/64.
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. As
demonstrated in Figure 4-1, the crystal should be connected to GND via a capacitor CL. The
value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When
designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO
must be considered.
Figure 4-1.
PLL Peripherals
VS
DVCC
CL
XTO
R1 = 820 Ω
C9 = 4.7 nF
C10 = 1 nF
LFGND
LF
LFVCC
VS
R1
C10
C9
The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz.
This value for BLoop exhibits the best possible noise performance of the LO. Figure 4-1 shows
the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at pin LF is
limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO cannot settle in time before the bit check starts to evaluate the incoming data stream. Self polling
will also not work in that case.
fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula: fLO = fRF - fIF
To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF
frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter
is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and
fLO. This relation is dependent on the logic level at pin MODE.
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4839B–RKE–08/05
This is described by the following formulas:
f LO
MODE = 0 (USA) : f IF = --------314
f LO
MODE = 1 (Europe) : f IF = ----------------432.92
The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications.
F o r ap p l i c a ti o n s w h e re f R F = 3 15 M H z , M O D E m us t be s e t t o “0 ” . In t he c a s e o f
fRF = 433.92 MHz, MODE must be set to “1”. For other RF frequencies, fIF is not equal to 1 MHz.
fIF is then dependent on the logical level at pin MODE and on fRF. Table 4-1 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF input
pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver
ATA5743 exhibits its highest sensitivity at the best signal-to-noise ratio (SNR) in the LNA.
Hence, noise matching is the best choice for designing the transformation network.
A good practice when designing the network is to start with power matching. From that starting
point, the values of the components can be varied to some extent to achieve the best sensitivity.
If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef = 40 dB
can be achieved. There are SAWs available that exhibit a notch at ∆f = 2 MHz. These SAWs
work best for an intermediate frequency of fIF = 1 MHz. The selectivity of the receiver is also
improved by using a SAW. In typical automotive applications, a SAW is used.
Figure 4-2 on page 7 shows a typical input matching network, for f RF = 315 MHz and
fRF = 433.92 MHz, using a SAW. Figure 4-3 on page 7 illustrates an according input matching to
50Ω without a SAW. The input matching networks shown in Figure 4-3 on page 7 are the reference networks for the parameters given in the table “Electrical Characteristics” on page 33.
Table 4-1.
6
Calculation of LO and IF Frequency
Conditions
Local Oscillator Frequency
Intermediate Frequency
fRF = 315 MHz, MODE = 0
fLO = 314 MHz
fIF = 1 MHz
fRF = 433.92 MHz, MODE = 1
fLO = 432.92 MHz
fIF = 1 MHz
300 MHz < fRF < 365 MHz,
MODE = 0
f RF
f LO = ------------------1
1 + ---------314
f LO
f IF = --------314
365 MHz < fRF < 450 MHz,
MODE = 1
f RF
f LO = --------------------------1
1 + -----------------432.32
f LO
f IF = ----------------432.92
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ATA5743
Figure 4-2.
Input Matching Network with SAW Filter
8
8
LNAGND
C3
L
22p
25n
9
LNA_IN
C16
27p
25n
9
LNA_IN
L3
TOKO LL2012
fRF = 315 MHz
L2
B3760
IN
OUT
5
TOKO LL2012
RFIN
2
22n
B3761
IN
OUT
5
47n
GND
GND
1, 3, 4
Figure 4-3.
120n
100p
L2
TOKO LL2012
2
L
C16
L3
TOKO LL2012
fRF = 433.92 MHz
RFIN
C3
68n
100p
LNAGND
ATA5743
ATA5743
6, 7, 8
1, 3, 4
6, 7, 8
Input Matching Network without SAW Filter
fRF = 433.92 MHz
8
fRF = 315 MHz
8
LNAGND
ATA5743
C3
15p
L
25n
C16
100p
RFIN
1.5p
C17
LNAGND
33n
L3
9
ATA5743
C3
27p
LNA_IN
L
25n
9
LNA_IN
C16
100p
RFIN
2.7p
C17
TOKO LL2012
F22NJ
47n
L3
TOKO LL2012
F39NJ
Please notice that for all coupling conditions (see Figure 4-2 and Figure 4-3), the bond wire
inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with
the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical, but
must be large enough not to detune the series resonance circuit. For cost reduction this inductor
can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by
about 1 to 2 dB.
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4839B–RKE–08/05
5. Analog Signal Processing
5.1
IF Amplifier
The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter.
The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or
fRF = 433.92 MHz. For other RF input frequencies refer to Table 4-1 on page 6 to determine the
center frequency.
The ATA5743 is available with two different IF bandwidths. ATA5743P3, the version with
BIF = 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter U2741B is used.
The receiver ATA5743P6 employs an IF bandwidth of BIF = 600 kHz. Both versions can be used
together with the U2741B in ASK and FSK mode. If used in ASK applications, higher tolerances
for the receiver and PLL transmitter crystals are allowed. SAW transmitters exhibit much higher
transmit frequency tolerances compared to PLL transmitters. Generally, it is necessary to use
BIF = 600 kHz together with SAW transmitters.
5.2
RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into
the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is
operated within its linear range, the best SNR is maintained in ASK mode. If the dynamic range
is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI
amplifier is exceeded if the power of the input signal is 60 dB higher than the sensitivity of the
receiver.
In FSK mode the SNR is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red.
VTh_red is determined by the value of the external resistor RSense. RSense is connected between
pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By
this means it is possible to operate the receiver at a lower sensitivity.
If RSense is connected to GND, the receiver operates at full sensitivity.
If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity
is defined by the value of RSense, the maximum sensitivity by the SNR of the LNA input. The
reduced sensitivity depends on the signal strength at the output of the RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This
matching is illustrated in Figure 4-3 on page 7 and exhibits the best possible sensitivity.
RSense can be connected to VS or GND via a microcontroller. The receiver can be switched
from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver
will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver
is already active, the data stream at pin DATA will disappear when the input signal is
lower than defined by the reduced sensitivity. Instead of the data stream, the pattern shown
in Figure 5-1 on page 9 is issued at pin DATA to indicate that the receiver is still active (see
Figure 6-26 on page 29).
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ATA5743
4839B–RKE–08/05
ATA5743
Figure 5-1.
Steady L State Limited DATA Output Pattern
DATA
5.3
tDATA_min
tDATA_L_max
FSK/ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK
demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the
OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode.
In ASK mode, an automatic threshold control circuit (ATC) is used to set the detection reference
voltage to a value where a good SNR is achieved. This circuit effectively suppresses any kind of
inband noise signals or competing transmitters. If the SNR (ratio to suppress inband noise signals) exceeds 10 dB, the data signal can be detected properly.
The FSK demodulator is intended to be used for an FSK deviation of 10 kHz ≤ ∆f ≤ 100 kHz. In
FSK mode the data signal can be detected if the SNR (ratio to suppress inband noise signals)
exceeds 2 dB. This value is guaranteed for all modulation schemes of a disturber signal.
The output signal of the demodulator is filtered by the data filter before it is fed into the digital
signal processing circuit. The data filter improves the SNR as its passband can be adopted to
the characteristics of the data signal. The data filter consists of a 1st-order high-pass and a
2nd-order low-pass filter.
The high-pass filter cut-off frequency is defined by an external capacitor connected to pin
CDEM. The cut-off frequency of the high-pass filter is defined by the following formula:
1
fcu_DF = ------------------------------------------------------------2 × π × 30 kΩ × CDEM
In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption.
Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other
hand, CDEM must be large enough to meet the data filter requirements according to the data
signal. Recommended values for CDEM are given in the electrical characteristics.
The cut-off frequency of the low-pass filter is defined by the selected baud-rate range
(BR_Range). The BR_Range is defined in the OPMODE register (refer to section “Configuration
of the Receiver” on page 24). The BR_Range must be set in accordance to the used baud rate.
The ATA5743 is designed to operate with data coding where the DC level of the data signal is
50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used,
the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. Even
then, the sensitivity will be reduced by up to 2 dB.
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig).
These limits are defined in the electrical characteristics; to maintain full sensitivity of the
receiver, they should not be exceeded.
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4839B–RKE–08/05
5.4
Receiving Characteristics
The RF receiver ATA5743 can be operated with and without a SAW front-end filter. In a typical
automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and
without a SAW front-end filter is illustrated in Figure 5-2. This example relates to ASK mode and
the 300-kHz bandwidth version of the ATA5743. FSK mode and the 600-kHz bandwidth version
of the receiver exhibit similar behavior. Note that the mirror frequency is reduced by 40 dB. The
plots are printed relative to the maximum sensitivity. If a SAW filter is used, an insertion loss of
about 4 dB must be considered.
Figure 5-2.
Receiving Frequency Response
0.0
-10.0
without SAW
-20.0
-30.0
dP (dB)
-40.0
-50.0
-60.0
-70.0
-80.0
with SAW
-90.0
-100.0
-6.0
-5.0 -4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
df (MHz)
When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the
sum of the deviation of the crystal and the XTO deviation of the ATA5743. Low-cost crystals are
specified to be within ±100 ppm. The XTO deviation of the ATA5743 is an additional deviation
due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is
used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the
IF-filter bandwidth are equivalent in ASK mode, but not in FSK mode.
6. Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected will the receiver remain active and transfer the data to the connected microcontroller. If there is no valid signal present, the receiver
remains in sleep mode most of the time, resulting in low current consumption; this condition is
called polling mode. A connected microcontroller is disabled during this time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate, etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It
can be either operated by a single bi-directional line (to save ports to the connected microcontroller), or it can be operated by up to five uni-directional ports.
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ATA5743
6.1
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. As
seen in Figure 6-1, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE. As
described in section “RF Front-end” on page 5, the frequency of the crystal oscillator (fXTO) is
defined by the RF input signal (fRFin) which also defines the operating frequency of the local
oscillator (fLO).
Figure 6-1.
Generation of the Basic Clock Cycle
TCLK
MODE
Divider
:14/:10
fXTO
16
L : USA(:10)
H: Europe(:14)
DVCC
15
XTO
XTO
14
Pin MODE can now be set in accordance with the desired clock cycle TClk, which controls the
following application relevant parameters:
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0)
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly
used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent
parameters on these electrical characteristics, here are displayed the three conditions for each
parameter.
• Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
• Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
• Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The
electrical characteristic is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range)
which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference:
BR_Range =
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
TXClk = 8 ×
TXClk = 4 ×
TXClk = 2 ×
TXClk = 1 ×
TClk
TClk
TClk
TClk
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6.2
Polling Mode
As shown in Figure 6-2 on page 13, the receiver’s polling mode consists of a continuous cycle of
three different modes. In sleep mode, the signal processing circuitry is disabled for the time
period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming
data stream is analyzed bit-by-bit, looking for a valid transmitter signal. If no valid signal is
present, the receiver is set back to sleep mode after the period TBit-check. This period varies
check-by-check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During TStartup and T Bit-check , the current consumption is I S = I Son . The
condition of the receiver is indicated on pin IC_ACTIVE.
The average current consumption in polling mode is dependent on the duty cycle of the active
mode and can be calculated as:
I Soff × T Sleep + I Son × ( T Startup + T Bit-check )
I Spoll = --------------------------------------------------------------------------------------------------------------T Sleep + T Startup + T Bit-check
During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the
reception of a transmitted command, the transmitter must start the telegram with an adequate
preburst. The required length of the preburst depends on the polling parameters TSleep, TStartup,
TBit-check, and the start-up time of a connected microcontroller (TStart, µC). Thus, TBit-check depends
on the actual bit rate and the number of bits (NBit-check) to be tested.
The following formula indicates how to calculate the preburst length.
TPreburst ≥ TSleep + TStartup + TBit-check + TStart_µC
6.3
Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (see Table 6-8 on page 26), and the basic clock cycle TClk. It is calculated to
be:
TSleep = Sleep × XSleep × 1024 × TClk
In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set
to “1”; the time resolution is about 2 ms in that case. The sleep time can be extended to almost
half a second by setting XSleep to 8. XSleep can be set to 8 by setting bit XSleepStd to “1”.
As seen in Table 6-7 on page 26, the highest register value of sleep sets the receiver into a
permanent sleep condition. The receiver remains in that condition until another value for Sleep is
programmed into the OPMODE register. This function is desirable where several devices share
a single data line and may also be used for microcontroller polling – via pin POLLING/_ON, the
receiver can be switched on and off.
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ATA5743
Figure 6-2.
Polling Mode Flow Chart
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and polling logic are
enabled.
Output level on pin IC_ACTIVE => low
IS = ISoff
TSleep = Sleep × XSleep × 1024 × TClk
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (TStartup) all
circuits are in a stable condition and ready
to receive.
Output level on pin IC_ACTIVE => high
IS = ISon
TStartup
Bit-check Mode:
The incoming data stream is analyzed. If
the timing indicates a valid transmitter
signal, the receiver is set to receive mode.
Otherwise it is set to Sleep mode.
Output level on pin IC_ACTIVE => high
IS = ISon
TBit-check
NO
Sleep:
5-bit word defined by Sleep0 to Sleep4 in
OPMODE register
XSleep:
Extension factor defined by XSleepStd
according to Table 9
TClk:
Basic clock cycle defined by fXTO and pin
MODE
TStartup:
Defined by the selected baud rate range
and TClk. The baud-rate range is defined
by Baud0 and Baud1 in the OPMODE
register
TBit-check:
Depends on the result of the bit check
If the bit check is ok, TBit-check depends
on the number of bits to be checked
(NBit-check), and on the utilized data rate
If the bit check fails, the average time
period for that check depends on the
selected baud-rate range on TClk. The
baud-rate range is defined by Baud0 and
Baud1 in the OPMODE register
Bit-check
OK?
YES
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set to
Sleep mode through an OFF command
via pin DATA or POLLING/_ON.
Output level on pin IC_ACTIVE => high
IS = ISon
OFF command
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4839B–RKE–08/05
Figure 6-3.
Timing Diagram for Complete Successful Bit Check
(Number of checked Bits: 3)
Bit check ok
IC_ACTIVE
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Data_out (DATA)
TStart-up
TBit-check
Start-up mode
Bit-check mode
Receiving mode
6.3.1
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter, and signals due to noise. This is done by subsequent time
frame checks where the distances between two signal edges are continuously compared to a
programmable time window. The maximum count of this edge-to-edge test before the receiver
switches to receiving mode is also programmable.
6.3.2
Configuring the Bit Check
Assuming a modulation scheme that contains two edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in the
OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks, respectively. If NBit-check is
set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower
value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 6-3 shows an
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
As demonstrated in Figure 6-4, the time window for the bit check is defined by two separate time
limits. If the edge-to-edge time tee is between the lower bit-check limit, TLim_min, and the upper
bit-check limit, TLim_max, the check will be continued. If tee is smaller than TLim_min, or tee exceeds
TLim_max, the bit check will be terminated and the receiver will switch to sleep mode.
Figure 6-4.
Valid Time Window for Bit Check
1/fSig
Dem_out
tee
TLim_min
TLim_max
For best noise immunity it is recommended to use a low span between TLim_min and TLim_max.
This is achieved by using a fixed frequency at a 50% duty cycle for the transmitter preburst. For
this reason, a “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice. A
good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time t ee . Using preburst patterns that contain
various edge-to-edge time periods, the bit-check limits must be programmed according to the
required span.
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The bit-check limits are determined by means of the formula below.
TLim_min = Lim_min × TXClk
TLim_max = (Lim_max -1) × TXClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined in the section “Digital Signal
Processing” on page 16. The lower limit should be set to Lim_min ≥ 10. The maximum value of
the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (NBit-check) to
prevent switching to receiving mode due to noise.
Figure 6-5, Figure 6-6 and Figure 6-7 on page 16 illustrate the bit check for the bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
TXClk.
Figure 6-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 6-6 the bit
check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim
reaches Lim_max. This is illustrated in Figure 6-7 on page 16.
Figure 6-5.
Timing Diagram During Bit Check
(Lim_min = 14, Lim_max = 24)
Bit check ok
Bit check ok
IC_ACTIVE
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Bit-checkcounter
0
TStart-up
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4
TXClk
TBit-check
Start-up mode
Figure 6-6.
Bit-check mode
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check failed ( CV_Lim < Lim_min )
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Bit check
1/2 Bit
Dem_out
Bit-checkcounter
0
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12
TStart-up
TBit-check
Start-up mode
Bit-check mode
0
TSleep
Sleep mode
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Figure 6-7.
Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
Bit check failed ( CV_Lim ≥ Lim_max )
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Bit check
1/2 Bit
Dem_out
Bit-checkcounter
6.3.3
0
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0
TStart-up
TBit-check
TSleep
Start-up mode
Bit-check mode
Sleep mode
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and TBit-check varies for each check.
Therefore, an average value for T Bit-check is given in the electrical characteristics. T Bit-check
depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a lower
value for TBit-check, resulting in lower current consumption in polling mode.
In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in
a longer period for TBit-check, requiring a higher value for the transmitter preburst, TPreburst.
6.3.4
Receiving Mode
If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving
mode. As shown in Figure 6-3 on page 14, the internal data signal is then switched to pin DATA,
and the data clock is available after the start bit has been detected (Figure 6-14 on page 20). A
connected microcontroller can be woken up by the negative edge at pin DATA or by the data
clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to polling
mode explicitly.
6.3.5
Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
converted into the output signal data. This processing depends on the selected baud-rate range
(BR_Range). Figure 6-8 on page 17 illustrates how Dem_out is synchronized by the extended
clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only
after TXClk has elapsed. The edge-to-edge time period tee of the Data signal, as a result, is
always an integral multiple of TXClk.
The minimum time period between two edges of the data signal is limited to tee ≥ TDATA_min (see
Figure 6-9 on page 17). This implies an efficient suppression of spikes at the DATA output
during data reception. At the same time, it limits the maximum frequency of edges at DATA. This
eases the interrupt handling of a connected microcontroller.
The maximum time period for DATA to stay Low is limited to T DATA_L_max . This function is
employed to ensure a finite response time in programming or switching off the receiver via pin
DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter
data stream. Figure 6-10 on page 17 shows an example where Dem_out remains Low after the
receiver has switched to receiving mode.
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Figure 6-8.
Synchronization of the Demodulator Output
T XClk
Clock bit-check
counter
Dem_out
Data_out (DATA)
Figure 6-9.
tee
Debouncing of the Demodulator Output
Dem_out
Data_out (DATA)
t DATA_min
t DATA_min
tDATA_min
t ee
tee
t ee
Figure 6-10. Steady L State Limited DATA Output Pattern After Transmission
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
t DATA_min
Start-up mode
Bit-check mode
t DATA_L_max
Receiving mode
After the end of a data transmission, the receiver remains active. Depending on the bit
Noise_Disable in the OPMODE register, the output signal at pin DATA is high, or random noise
pulses appear at pin DATA (see section “Digital Noise Suppression” on page 22). The
edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than
TDATA_min.
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6.3.6
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON.
When using pin DATA, this pin must be pulled to Low by the connected microcontroller for
the period t1. Figure 6-11 illustrates the timing of the OFF command (see also Figure 6-26 on
page 29). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not limited, but it is recommended not to exceed the specified value to prevent erasing the reset
marker. (see section “Programming the Configuration Register” on page 28) Note also that an
internal reset for the OPMODE and the LIMIT register will be generated if t1 exceeds the specified values. This item is explained in more detail in the section “Configuration of the Receiver” on
page 24. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to be “1”
during the register configuration. Only one sync pulse (t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF
command the sleep time TSleep elapses. Note that the capacitive load at pin DATA is limited (see
section “Data Interface” on page 30).
Figure 6-11. Timing Diagram of the OFF command via Pin DATA
IC_ACTIVE
t1
t2
t3
t5
t4
t10
t7
Out1
(microcontroller)
Data_out (DATA)
X
Serial bi-directional
data line
X
Bit 1
("1")
(Start bit)
TSleep
TStart-up
Sleep mode
Start-up mode
OFF command
Receiving
mode
Figure 6-12. Timing Diagram of the OFF command via Pin POLLING/_ON
IC_ACTIVE
t on2
ton3
Bit check ok
POLLING/_ON
Data_out (DATA)
X
X
Serial bi-directional
data line
X
X
Receiving mode
18
Sleep mode
Start-up mode
Bit-check mode
Receiving mode
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ATA5743
Figure 6-13. Activating the Receiving Mode via Pin POLLING/_ON
IC_ACTIVE
ton1
POLLING/_ON
Data_out (DATA)
X
Serial bi-directional
data line
X
Sleep mode
Start-up mode
Receiving mode
Figure 6-12 on page 18 illustrates how to set the receiver back to polling mode via pin
POLLING/_ON. The pin POLLING/_ON must be held to low for the time period ton2. After the
positive edge on pin POLLING/_ON and the delay ton3, the polling mode is active and the sleep
time TSleep elapses.
This command is faster than using pin DATA, but at the cost of an additional connection to the
microcontroller.
Figure 6-13 illustrates how to set the receiver to receive mode via the pin POLLING/_ON. The
pin POLLING/_ON must be held to Low. After the delay ton1, the receiver changes from sleep
mode to start-up mode regardless of the programmed values for TSleep and NBit-check. As long as
POLLING/_ON is held to Low, the values for TSleep and NBit-check will be ignored, but not deleted
(see section “Digital Noise Suppression” on page 22).
If the receiver is polled exclusively by a microcontroller, TSleep must be programmed to 31
(permanent sleep mode). In this case, the receiver remains in sleep mode as long as POLLING/_ON is held to High.
6.4
Data Clock
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift
register. Using this data clock, a microcontroller can easily synchronize the data stream. This
clock can only be used for Manchester- and Bi-phase-coded signals.
6.4.1
Generation of the Data Clock
After a successful bit check, the receiver switches from polling mode to receiving mode and the
data stream is available at pin DATA. In receiving mode, the data clock control logic (Manchester/Bi-phase demodulator) is active and examines the incoming data stream. This is done, as in
the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. As illustrated in Figure 6-14 on page 20,
only two distances between two edges in Manchester- and Bi-phase-coded signals are valid
(T and 2T).
The limits for T are the same as used for the bit check. They can be programmed in the
LIMIT-register (Lim_min and Lim_max, see Table 6-10 on page 27 and Table 6-11 on page 27).
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The limits for 2T are calculated as follows:
Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) - (Lim_max - Lim_min)/2
Upper limit of 2T: Lim_max_2T = (Lim_min + Lim_max) + (Lim_max - Lim_min)/2
Note:
If the result for “Lim_min_2T” or “Lim_max_2T” is not an integer value, it will be rounded up.
The data clock is available after the data clock control logic has detected the distance 2T (Start
bit), and then issues pulses with a delay of tDelay after the edges on pin DATA (see Figure 6-14).
If the data clock control logic detects a timing or logical error (Manchester code violation), as
illustrated in Figure 6-15 and Figure 6-16 on page 21, it stops the output of the data clock. The
receiver remains in receiving mode and starts with the bit check. If the bit check was successful
and the start bit has been detected, the data clock control logic starts again with the generation
of the data clock (see Figure 6-17 on page 21).
It is recommended to use the function of the data clock only in conjunction with the bit check 3, 6
or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the pin POLLING/_ON,
the data clock is available if the data clock control logic has detected the distance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 6-14. Timing Diagram of the Data Clock
Preburst
Data
Bit check ok
T
1
1
1
1
2T
1
0
1
1
0
1
0
Dem_out
Data_out (DATA)
DATA_CLK
Start bit
tDelay
t P_Data_Clk
Receiving mode,
data clock control logic active
Bit-check mode
Figure 6-15. Data Clock Disappears Because of a Timing Error
Data
(Tee < TLim_min
Timing error
OR T Lim_max
< Tee < T Lim_min_2T OR Tee > TLim_max_2T )
Tee
1
1
1
1
1
0
1
1
0
1
0
Dem_out
Data_out (DATA)
DATA_CLK
Receiving mode,
data clock control
logic active
20
Receiving mode,
bit check active
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ATA5743
Figure 6-16. Data Clock Disappears Because of a Logical Error
Data
Logical error (Manchester code violation)
1
1
1
0
1
1
?
0
0
1
0
Dem_out
Data_out (DATA)
DATA_CLK
Receiving mode,
data clock control
logic active
Receiving mode,
bit check aktive
Figure 6-17. Output of the Data Clock After a Successful Bit Check
Data
Bit check ok
1
1
1
1
1
0
1
1
0
1
0
Dem_out
Data_out (DATA)
DATA_CLK
Receiving mode,
bit check active
Start bit
Receiving mode,
data clock control
logic active
The delay of the data clock is calculated as follows:
tDelay = tDelay1 + tDelay2
tDelay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1
depends on the capacitive load CL at pin DATA and the external pull-up resistor Rpup. For the
falling edge, tDelay1 depends additionally on the external voltage VX (see Figure 6-18 on page 22,
Figure 6-19 on page 22 and Figure 6-26 on page 29). When the level of Data_In is equal to the
level of Data_Out, the data clock is issued after an additional delay tDelay2.
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at
pin DATA is exceeded, the data clock disappears (see section “Data Interface” on page 29).
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4839B–RKE–08/05
Figure 6-18. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Data_Out
VX
VIh = 0.65 × VS
Serial bi-directional
data line
VII = 0.35 × VS
Data_In
DATA_CLK
tDelay1
tDelay
tDelay2
t P_Data_Clk
Figure 6-19. Timing Characteristic of the Data Clock (Falling Edge on Pin DATA)
Data_Out
VX
VIh = 0.65 × VS
Serial bi-directional
data line
VII = 0.35 × VS
Data_In
DATA_CLK
t Delay1
t Delay
6.5
tDelay2
tP_Data_Clk
Digital Noise Suppression
After a data transmission, digital noise appears on the data output (see Figure 6-20 on page 23).
To prevent digital noise from keeping the connected microcontroller busy, it can be suppressed
in two different ways.
6.5.1
Automatic Noise Suppression
The automatic noise suppression is illustrated in Figure 6-21 on page 23. If the bit
Noise_Disable (Table 6-9 on page 26) in the OPMODE register is set to “1” (default), the
receiver changes to bit-check mode at the end of a valid data stream. The digital noise is suppressed and the level at pin DATA is High in that case. The receiver changes back to receiving
mode, if the bit check was successful.
This way of suppressing the noise is recommended if the data stream is Manchester or Bi-phase
coded and is active after power on.
Figure 6-22 on page 23 illustrates the behavior of the data output at the end of a data stream.
Note that if the last period of the data stream is a high period (rising edge to falling edge), a
pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range.
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Figure 6-20. Output of Digital Noise at the End of the Data Stream
Bit check ok
Bit check ok
Preburst
Data_out (DATA)
Data
Digital Noise
Digital Noise
Preburst
Data
Digital Noise
DATA_CLK
Bit-check
mode
Receiving mode,
data clock control
logic active
Receiving mode,
bit check aktive
Receiving mode,
data clock control
logic active
Receiving mode,
bit check aktive
Figure 6-21. Automatic Noise Suppression
Bit check ok
Bit check ok
Preburst
Data_out (DATA)
Data
Preburst
Data
DATA_CLK
Bit-check
mode
Receiving mode,
data clock control
logic active
Receiving mode,
data clock control
logic active
Bit-check
mode
Bit-check
mode
Figure 6-22. Occurrence of a Pulse at the End of the Data Stream
(Tee < TLim_min or T Lim_max < Tee < T Lim_min_2T or T ee > TLim_max_2T )
Timing error
T ee
Data stream
1
1
Digital noise
1
Dem_out
Data_out (DATA)
T Pulse
DATA_CLK
Receiving mode,
data clock control
logic active
6.5.2
Bit-check mode
Controlled Noise Suppression by the Microcontroller
The controlled noise suppressionis illustrated in Figure 6-23 on page 24. If the bit Noise_Disable
(see Table 6-9 on page 26) in the OPMODE register is set to “0”, digital noise appears at the end
of a valid data stream. To suppress the noise, the pin POLLING/_ON must be set to Low. The
receiver remains in receiving mode. Then, the OFF command causes the change to the start-up
mode. The programmed sleep time (see Table 6-7 on page 26) will not be executed because the
level at pin POLLING/_ON is Low, but the bit check is active. The OFF command activates the
bit check also if the pin POLLING/_ON is held to Low. The receiver changes back to receiving
mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the pin POLLING/_ON must be set to High.
This way of suppressing the noise is recommended if the data stream is not Manchester or
Bi-phase coded.
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4839B–RKE–08/05
Figure 6-23. Controlled Noise Suppression
Bit check ok
Serial bi-directional
data line
OFF command
Preburst
Data
Bit check ok
Digital Noise
Preburst
Data
Digital Noise
(DATA_CLK)
POLLING/_ON
Bit-check
mode
6.6
Receiving mode
Start-up Bit-check
mode
mode
Receiving mode
Sleep
mode
Configuration of the Receiver
The ATA5743 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT.
The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern
called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on
reset (POR), the registers are set to default mode. If the receiver is operated in default mode,
there is no need to program the registers. Table 6-3 on page 25 shows the structure of the registers. As seen in Table 6-1, bit 1 defines if the receiver is set back to polling mode via the OFF
command (see section “Receiving Mode” on page 16) or if it is programmed. Bit 2 represents the
register address. It selects the appropriate register to be programmed. To get a high programming reliability, bit 15 (Stop bit), at the end of the programming operation, must be set to “0”.
Table 6-1.
Effect of Bit 1 and Bit 2 on Programming the Registers
Bit 1
Bit 2
1
x
The receiver is set back to polling mode (OFF command)
0
1
The OPMODE register is programmed
0
0
The LIMIT register is programmed
Table 6-2.
Effect of Bit 15 on Programming the Register
Bit 15
24
Action
Action
0
The values will be written into the register (OPMODE or LIMIT)
1
The values will not be written into the register
ATA5743
4839B–RKE–08/05
ATA5743
Table 6-3.
Bit 1
Bit 2
Effect of the Configuration Words Within the Registers
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
X
Sleep
Noise
Suppression
Bit 15
OFF command
1
OPMODE register
BR_Range
0
Modu-lat
ion
NBit-check
1
Default values
of bits 3 to 14
Sleep
Baud1
Baud0
BitChk1
BitChk0
ASK/_
FSK
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
XSleepStd
Noise_
Disable
0
0
0
1
0
0
0
1
1
0
0
1
0
LIMIT register
Lim_min
0
0
Default values
of bits 3 to 14
Lim_max
Lim_
min5
Lim_
min4
Lim_
min3
Lim_
min2
Lim_
min1
Lim_
min0
Lim_
max5
Lim_
max4
Lim_
max3
Lim_
max2
Lim_
max1
Lim_max0
0
1
0
1
0
1
1
0
1
0
0
1
0
Table 6-4 on page 25 to Table 6-11 on page 27 illustrate the effect of the individual configuration
words. The default configuration is highlighted for each word.
BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is
used to define the bit-check limits TLim_min and TLim_max as shown in Table 6-10 on page 27 and
Table 6-11 on page 27.
Table 6-4.
Effect of the Configuration Word BR_Range
BR_Range
Baud1
Baud0
Baud-Rate Range/Extension Factor for Bit-Check Limits (XLim)
0
0
BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to
1.8 kBaud) XLim = 8 (default)
0
1
BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to
3.2 kBaud) XLim = 4
1
0
BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to
5.6 kBaud) XLim = 2
1
1
BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to
10 kBaud) XLim = 1
Table 6-5.
Effect of the Configuration Word NBit-check
NBit-check
BitChk1
BitChk0
Number of Bits to be Checked
0
0
0
0
1
3 (default)
1
0
6
1
1
9
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4839B–RKE–08/05
Table 6-6.
Effect of the Configuration Bit Modulation
Modulation
Selected Modulation
ASK/_FSK
Table 6-7.
0
FSK (default)
1
ASK
Effect of the Configuration Word Sleep
Sleep
Start Value for Sleep Counter
(TSleep = Sleep × XSleep × 1024 × TClk)
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
0
0
0
0
0
0 (Receiver is continuously polling until a valid
signal occurs)
0
0
0
0
1
1 (TSleep ≈ 2 ms for XSleep = 1 in
US-/European applications)
0
0
0
1
0
2
0
0
0
1
1
3
...
...
...
...
...
...
0
0
1
1
0
6 (USA: TSleep = 12.52 ms, Europe:
TSleep = 12.72 ms) (default)
...
...
...
...
...
...
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31 (Permanent sleep mode)
Table 6-8.
Effect of the Configuration Bit XSleep
XSleep
XSleepStd
Extension Factor for Sleep Time
(TSleep = Sleep × XSleep × 1024 × TClk)
0
1 (default)
1
8
Table 6-9.
Effect of the Configuration Bit Noise Suppression
Noise Suppression
26
Noise_Disable
Suppression of the Digital Noise at Pin DATA
0
Noise suppression is inactive
1
Noise suppression is active (default)
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ATA5743
Table 6-10.
Effect of the Configuration Word Lim_min
Lim_min(1) (Lim_min < 10 Is Not Applicable)
Lower Limit Value for Bit Check
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TLim_min = Lim_min × Lim × TClk)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
0
0
1
1
0
0
12
...
...
...
...
...
...
0
1
0
1
0
1
...
...
...
...
...
...
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Note:
21 (default)
USA: TLim_min = 342 µs, Europe: TLim_min = 348 µs)
1. Lim_min is also used to determine the margins of the data clock control logic (see section “Data Clock” on page 19).
Table 6-11.
Effect of the Configuration Word Lim_max
Lim_max(1) (Lim_max < 12 Is Not Applicable)
Upper Limit Value for Bit Check
Lim_max
5
Lim_max
4
Lim_max
3
Lim_max
2
Lim_max
1
Lim_max
0
(TLim_max = (Lim_max - 1) × XLim × TClk)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14
...
...
...
...
...
...
1
0
1
0
0
1
...
...
...
...
...
...
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Note:
6.6.1
41 (default)
USA: TLim_max = 652 µs,
Europe: TLim_max = 662 µs)
1. Lim_max is also used to determine the margins of the data clock control logic (see section “Data Clock” on page 19).
Conservation of the Register Information
The ATA5743 has integrated power-on reset and brown-out detection circuitry to provide a
mechanism to preserve the RAM register information.
As seen in Figure 6-24 on page 28, a power-on reset (POR) is generated if the supply voltage VS
drops below the threshold voltage VThReset. The default parameters are programmed into the
configuration registers in that condition. Once VS exceeds VThReset the POR is cancelled after the
minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is
turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset.
The RM is represented by the fixed frequency fRM at a 50% duty-cycle. RM can be cancelled via
a Low pulse t1 at pin DATA.
27
4839B–RKE–08/05
The RM implies the following characteristics:
• fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be
misinterpreted by the connected microcontroller.
• If the receiver is set back to polling mode via pin DATA, RM cannot be cancelled by accident
if t1 is applied according to the proposal in the section “Programming the Configuration
Register” on page 28.
By means of that mechanism the receiver cannot lose its register information without communicating that condition via the reset marker RM.
Figure 6-24. Generation of the Power-on Reset
V ThReset
VS
POR
tRst
Data_out (DATA)
X
1/fRM
6.6.2
Programming the Configuration Register
Figure 6-25. Timing of the Register Programming
IC_ACTIVE
t1
t2
t3
t9
t8
t5
t4
t6
t7
Out1 (µC)
Data_out (DATA)
Serial bi-directional
data line
X
X
Bit 1
(0)
(Start bit)
Bit 2
(1)
(Registerselect)
Programming frame
Receiving
mode
28
Bit 14
(0)
(Poll8)
Bit 15
(0)
(Stop bit)
TSleep TStart-up
Sleep Start-up
mode mode
ATA5743
4839B–RKE–08/05
ATA5743
Figure 6-26. Data Interface
VX = 5 V to 20 V
VS = 4.5 V to 5.5 V
ATA5743
Microcontroller
Rpup
0 V/5 V
Data_In
Input Interface
0 to 20 V
I/O
DATA
Serial bi-directional data line
ID
CL
Out1 microcontroller
Data_out
The configuration registers are programmed serially via the bi-directional data line as demonstrated in Figure 6-25 on page 28 and Figure 6-26.
To start programming, the microcontroller pulls the serial data line DATA to Low for the time
period t1. When DATA has been released, the receiver becomes the master device. When the
programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with
the pulse length t3. After each of these pulses, a programming window occurs. The delay until
the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time
period t7 during t5, the appropriate bit is set to “0”. If no programming pulse t7 is issued, this bit
is set to “1”. All 15 bits are subsequently programmed this way. The time frame to program a bit
is defined by t6.
Bit 15 is followed by the equivalent time window t9. During this window, the equivalent acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word
that was already stored in that register. E_Ack should be used to verify that the mode word was
correctly transferred to the register; in order to do this, the register must be programmed twice.
Programming of a register is possible with the receiver in either sleep mode or in active mode.
During programming, the LNA, LO, low-pass filter IF-amplifier, and the FSK/ASK Manchester
demodulator are disabled.
The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is
set to “1”, it represents the OFF command to set the receiver back to polling mode immediately.
For the length of the programming start pulse t1, the following convention should be considered:
• t1(min) < t1 < 5632 × TClk: t1(min) is the minimum specified value for the relevant BR_Range
Similarly, programming the OFF command is initiated if the receiver is not in reset mode. If the
receiver is in reset mode, programming the OFF command is not initiated and the reset marker
(RM) is still present at pin DATA.
This period is generally used to switch the receiver to polling mode or to start the programming
of a register. In reset condition, RM can not be cancelled by accident.
• t1 > 7936 × TClk
Programming registers or the OFF command is initiated in any case. The registers OPMODE
and LIMIT are set to the default values. RM is cancelled if present.
29
4839B–RKE–08/05
This period is used if the connected microcontroller detected RM. If the receiver operates in
default mode, this time period for t1 can generally be used.
Note that the capacitive load at pin DATA is limited.
6.6.3
Data Interface
The data interface (see Figure 6-26 on page 29) is designed for automotive requirements. It can
be connected via the pull-up resistor Rpup up to 20 V and is short-circuit protected.
The applicable pull-up resistor R pup depends on the load capacity C L at pin DATA and the
selected BR_range (see Table 6-12). More detailed information about the calculation of the
maximum load capacity at pin DATA is given in the separate document “Application Note RKE
Design Kit (U2741B, U3741BM)”. The internal circuitry with respect to the pin DATA is similar in
ATA5743 and U3741BM.
Table 6-12.
Applicable Rpup
BR_range
Applicable Rpup
B0
1.6 kΩ to 47 kΩ
B1
1.6 kΩ to 22 kΩ
B2
1.6 kΩ to 12 kΩ
B3
1.6 kΩ to 5.6 kΩ
B0
1.6 kΩ to 470 kΩ
B1
1.6 kΩ to 220 kΩ
B2
1.6 kΩ to 120 kΩ
B3
1.6 kΩ to 56 kΩ
CL ≤ 1 nF
CL ≤ 100 pF
Figure 6-27. Application Circuit: fRF = 433.92 MHz without SAW Filter
VS
+ C7
2.2 µF
20%
IC_ACTIVE
C6
R2
10 nF
10%
GND
C14
5%
X7R 10%
C3 15 pF
5%
np0
4
5
6
7
DGND
DATA_CLK
AVCC
TEST
AGND
MODE
8
9
MIXVCC
LNAGND
LNA_IN
DVCC
XTO
LFGND
LF
NC
LFVCC
20
19
18
17
16
DATA
POLLING/_ON
DATA_CLK
6.7643
MHz C11
15
14
5% 12 pF
Q1 np0
13
12
11
C8 150 pF
C12
150 pF C15
np0 10%
30
CDEM
10
25 nH
C17
SENS
DATA
IC_ACTIVE POLLING /_ON
33 nF
C13 10 nF
1.5 pF
5%
np0
1
2
3
np0 10%
10nF
10%
X7R
C16
L2
100 pF
5%
33 nH np0
5%
Sensitivity reduction
R3
≥ 1.6 kΩ
ATA5743
X7R
COAX
VX = 5 V to 20 V
56 kΩ to 150 kΩ
10%
R1
820Ω
5%
C9
C10
4.7 nF
1 nF
X7R 5% X7R 5%
ATA5743
4839B–RKE–08/05
ATA5743
Figure 6-28. Application Circuit: fRF = 315 MHz without SAW Filter
VS
+ C7
IC_ACTIVE
C6
2.2 µF
20%
R2
10 nF
10%
VX = 5 V to 20 V
56 kΩ to 150 kΩ
10%
GND
R3
≥ 1.6 kΩ
ATA5743
1
2
3
C14
X7R
5%
33 nF
C13 10 nF
X7R 10%
C3 27 pF
5%
np0
SENS
DATA
IC_ACTIVE POLLING /_ON
CDEM
DGND
DATA_CLK
4
5
6
7
AVCC
TEST
AGND
8
9
MIXVCC
LNAGND
LNA_IN
10
MODE
DVCC
LFGND
LF
NC
LFVCC
20
19
18
17
16
DATA
POLLING/_ON
DATA_CLK
4.906
MHz
15
14
C8 150 pF
np0 10%
150 pF C15
10nF
10%
X7R
np0 10%
C17
C16
2.7 pF
5%
np0
R1
100 pF
5%
np0
L2
C11
5% 15 pF
Q1 np0
13
12
11
C12
25nH
COAX
XTO
Sensitivity reduction
820 Ω
5%
C9
C10
4.7 nF
1 nF
X7R 5% X7R 5%
47 nH
5%
Figure 6-29. Application Circuit: fRF = 433.92 MHz with SAW Filter
VS
+ C7
2.2 µF
20%
IC_ACTIVE
C6
R2
10 nF
10%
GND
1
2
3
C14
5%
33 nF
4
5
6
C13 10 nF
X7R 10%
7
C3 22 pF
8
9
5%
np0
25nH
10
22 nH
5%
2
IN
MODE
AVCC
TEST
AGND
DVCC
XTO
MIXVCC
LNAGND
LNA_IN
NC
LFGND
LF
LFVCC
20
19
18
17
16
DATA
POLLING/_ON
DATA_CLK
6.7643
MHz C11
15
14
5% 12 pF
Q1 np0
13
12
11
C8
C12
C15
C16
100 pF
5%
np0
150 pF
10%
np0
L2
SENS
DATA
IC_ACTIVE POLLING /_ON
CDEM
DGND
DATA_CLK
B3760 OUT
GND
1, 3, 4 6, 7, 8
5
L3
68 nH
5%
Sensitivity reduction
R3
≥ 1.6 kΩ
ATA5743
X7R
COAX
VX = 5 V to 20 V
56 kΩ to 150 kΩ
10%
150 pF
10%
np0
10nF
10%
X7R
R1
820 Ω
5%
C9
C10
4.7 nF
1 nF
X7R 5% X7R 5%
31
4839B–RKE–08/05
Figure 6-30. Application Circuit: fRF = 315 MHz with SAW Filter
VS
+ C7
2.2 µF
20%
IC_ACTIVE
C6
R2
10 nF
10%
GND
1
2
3
C14
5%
33 nF
4
5
6
7
C13 10 nF
X7R 10%
C3 27 pF
8
9
10
5%
np0
25nH
L2
2
IN
47 nH
5%
SENS
DATA
IC_ACTIVE POLLING /_ON
CDEM
DGND
DATA_CLK
MODE
AVCC
TEST
DVCC
AGND
XTO
MIXVCC
LNAGND
LFGND
LF
LNA_IN
NC
LFVCC
20
19
18
17
16
DATA_CLK
4.906
MHz C11
15
14
5% 15 pF
Q1 np0
13
12
11
C8 150 pF
C12
C16
100 pF
5%
np0
B3761 OUT
5
DATA
POLLING/_ON
C15
150 pF
10%
np0
COAX
R3
≥ 1.6 kΩ
5%
ATA5743
X7R
Sensitivity reduction
VX = 5 V to 20 V
56 kΩ to 150 kΩ
10%
np0 10%
10nF
10%
X7R
L3
120 nF
5%
R1
820 Ω
5%
C9
GND
C10
4.7 nF
1 nF
X7R 5% X7R 5%
1, 3, 4 6, 7, 8
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Max.
Unit
Supply voltage
VS
6
V
Power dissipation
Ptot
1000
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
-55
+125
°C
Ambient temperature
Tamb
-40
+105
°C
10
dBm
Maximum input level, input matched to 50Ω
Pin_max
8. Thermal Resistance
Parameters
Junction ambient
32
Symbol
Value
Unit
RthJA
100
K/W
ATA5743
4839B–RKE–08/05
ATA5743
9. Electrical Characteristics
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
6.76438 MHz Osc.
(MODE: 1)
Parameter
Test Conditions
Symbol
Min.
Typ.
Max.
4.90625 MHz Osc.
(MODE: 0)
Min.
Typ.
Variable Oscillator
Max.
Min.
2.0383
2.0383
16.3
8.2
4.1
2.0
16.3
8.2
4.1
2.0
Typ.
Max.
Unit
1/fXTO/10
1/fXTO/14
1/fXTO/10
1/fXTO/14
µs
µs
8×
4×
2×
1×
8×
4×
2×
1×
µs
µs
µs
µs
Basic Clock Cycle of the Digital Circuitry
Basic clock cycle
MODE = 0 (USA)
MODE = 1 (Europe)
BR_Range0
Extended basic BR_Range1
clock cycle
BR_Range2
BR_Range3
TClk
2.0697
2.0697
TXClk
16.6
8.3
4.1
2.1
16.6
8.3
4.1
2.1
TSleep
Sleep ×
XSleep ×
1024 ×
2.0697
Sleep ×
XSleep ×
1024 ×
2.0697
Sleep ×
XSleep ×
1024 ×
2.0383
TStartup
1855
1061
1061
663
1855
1061
1061
663
1827
1045
1045
653
TClk
TClk
TClk
TClk
TClk
TClk
TClk
TClk
Polling Mode
Sleep time (see
Sleep and XSleep are
Figure 6-2,
defined in the
Figure 6-11, and
OPMODE register
Figure 6-25)
BR_Range0
Start-up time
BR_Range1
(see Figure 6-2
BR_Range2
and Figure 6-3)
BR_Range3
Average bit-check
time while polling,
no RF applied
(see Figure 6-6, and
Figure 6-7)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TBit-check
Bit-check time for a
valid input signal fSig ,
(see Figure 6-3)
NBit-check = 0
NBit-check = 3
NBit-check = 6
NBit-check = 9
TBit-check
Intermediate
frequency
MODE = 0 (USA)
MODE = 1 (Europe)
fIF
Baud-rate range
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Time for bit
check (see
Figure 6-2)
0.45
0.24
0.14
0.08
3/fSig
6/fSig
9/fSig
Sleep ×
XSleep × Sleep × XSleep
1024 × × 1024 × TClk
2.0383
1827
1045
1045
653
896.5
512.5
512.5
320.5 × TClk
Sleep ×
XSleep × 1024
× TClk
ms
896.5
512.5
512.5
320.5 × TClk
µs
µs
µs
µs
0.45
0.24
0.14
0.08
3.5/fSig
6.5/fSig
9.5/fSig
3/fSig
6/fSig
9/fSig
ms
ms
ms
ms
3.5/fSig
6.5/fSig
9.5/fSig
1 × TXClk
3/fSig
6/fSig
9/fSig
1 × TClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
Receiving Mode
Minimum time
period between
BR_Range =
edges at pin
DATA
BR_Range0
(see Figure 5-1,
BR_Range1
Figure 6-9 and
BR_Range2
Figure 6-10, with
BR_Range3
the exception of
parameter TPulse)
BR_Range
tDATA-min
1.0
fXTO × 64/314
fXTO × 64/432.92
1.0
1.0
1.8
3.2
5.6
1.8
3.2
5.6
10.0
1.0
1.8
3.2
5.6
1.8
3.2
5.6
10.0
165
83
41.4
20.7
165
83
41.4
20.7
163
81
40.7
20.4
163
81
40.7
20.4
BR_Range0 ×
BR_Range1 ×
BR_Range2 ×
BR_Range3 ×
10 ×
10 ×
10 ×
10 ×
TXClk
TXClk
TXClk
TXClk
MHz
MHz
2 µs/TClk
2 µs/TClk
2 µs/TClk
2 µs/TClk
kBaud
kBaud
kBaud
kBaud
10 ×
10 ×
10 ×
10 ×
µs
µs
µs
µs
TXClk
TXClk
TXClk
TXClk
33
4839B–RKE–08/05
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
6.76438 MHz Osc.
(MODE: 1)
Parameter
Test Conditions
Maximum Low
period at pin
DATA (see
Figure 5-1 and
Figure 6-10)
Symbol
Min.
Typ.
4.90625 MHz Osc.
(MODE: 0)
Max.
Min.
Typ.
Max.
2152
1076
538
270
2152
1076
538
270
2120
1060
530
265
2120
1060
530
265
21.8
19.4
21.5
Variable Oscillator
Min.
Typ.
Max.
Unit
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tDATA_L_max
Delay to activate
the start-up
mode (see
Figure 6-13)
Ton1
19.7
OFF command
at pin
POLLING/_ON
(see
Figure 6-12)
Ton2
16.6
Delay to activate
the sleep mode
(see
Figure 6-12)
Ton3
17.6
19.7
17.4
19.4
16.6
8.3
4.1
2.1
16.6
8.3
4.1
2.1
16.3
8.2
4.1
2.0
16.3
8.2
4.1
2.0
117.9
117.9
119.8
119.8
3367
2277
1735
1464
16.43
11650
11650
11650
11650
3311
2243
1709
1442
16.18
t2
795
798
t3
265
t4
t5
BR_Range =
Pulse on pin
DATA at the end
BR_Range0
of a data stream
BR_Range1
(see
BR_Range2
Figure 6-22)
BR_Range3
TPulse
130 ×
130 ×
130 ×
130 ×
TXClk
TXClk
TXClk
TXClk
9.5 × TClk
130 ×
130 ×
130 ×
130 ×
TXClk
TXClk
TXClk
TXClk
10.5 × TClk
8 × TClk
16.4
8.5 × TClk
8×
4×
2×
1×
TClk
TClk
TClk
TClk
µs
µs
µs
µs
µs
µs
9.5 × TClk
8×
4×
2×
1×
TClk
TClk
TClk
TClk
µs
µs
µs
µs
µs
Configuration of the Receiver
Frequency of the
(see Figure 6-23)
reset marker
fRM
1
--------------------------------4096 × T Clk
1
--------------------------------4096 × T Clk
11470
11470
11470
11470
1624 × TClk
1100 × TClk
838 × TClk
707 × TClk
7936 × TClk
5632 ×
5632 ×
5632 ×
5632 ×
783
786
384.5 × TClk
385.5 × TClk
µs
265
261
261
128 × TClk
128 × TClk
µs
131
131
129
129
63.5 × TClk
63.5 × TClk
µs
530
530
522
522
256 × TClk
256 × TClk
µs
Hz
BR_Range =
Programming
BR_Range0
start pulse (see
BR_Range1
Figure 6-11 and
BR_Range2
Figure 6-25)
BR_Range3
after POR
Programming
delay period
Synchronization
pulse
Delay until the
programming
window starts
(see Figure 6-11 and
Figure 6-25)
Programming
window
34
t1
TClk
TClk
TClk
TClk
µs
µs
µs
µs
µms
ATA5743
4839B–RKE–08/05
ATA5743
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
6.76438 MHz Osc.
(MODE: 1)
Parameter
Test Conditions
Symbol
Min.
Time frame
of a bit
(see
Figure 6-25)
t6
Programming
pulse (see
Figure 6-11 and
Figure 6-25)
Typ.
4.90625 MHz Osc.
(MODE: 0)
Max.
Min.
1060
1060
t7
132
Equivalent
acknowledge
pulse: E_Ack
(see
Figure 6-25)
t8
Equivalent time
window (see
Figure 6-25)
OFF bit
programming
window (see
Figure 6-11)
Typ.
Variable Oscillator
Max.
Min.
1044
1044
529
130
265
265
t9
534
t10
Typ.
Max.
Unit
512 × TClk
512 × TClk
µs
521
64 × TClk
256 × TClk
µs
261
261
128 × TClk
128 × TClk
µs
534
526
526
258 × TClk
258 × TClk
µs
930
930
916
916
449.5 × TClk
449.5 × TClk
µs
0
0
0
0
16.6
8.3
4.15
2.07
0
0
0
0
16.3
8.2
4.08
2.04
0
0
0
0
1×
1×
1×
1×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
66.2
33.1
16.56
8.3
66.2
33.1
16.56
8.3
65.2
32.6
16.3
8.2
65.2
32.6
16.3
8.2
TXClk
TXClk
TXClk
TXClk
4×
4×
4×
4×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
Data Clock
Minimum delay
time between
edge at DATA
and DATA_CLK
(see Figure 6-18
and Figure 6-19)
Pulse width of
negative pulse at
pin DATA_CLK
(see Figure 6-18
and Figure 6-19)
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tDelay2
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tP_DATA_CLK
4×
4×
4×
4×
35
4839B–RKE–08/05
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
Parameters
Current consumption
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Sleep mode
(XTO and polling logic active)
ISoff
170
276
µA
IC active (start-up-, bit check-,
receiving mode) pin DATA = H
FSK
ASK
ISon
7.5
7.1
9.1
8.7
mA
mA
IIP3
-28
ISLORF
-73
NF
7
dB
ZiLNA_IN
1.0 || 1.56
1.3 || 1.0
kΩ || pF
kΩ || pF
IP1db
-40
dBm
LNA Mixer (Input Matched According to Figure 4-3)
Third-order intercept point
LNA/mixer/IF amplifier
LO spurious emission at RFIn
Required according to I-ETS 300220
Noise figure LNA and mixer (DSB)
LNA_IN input impedance
at 433.92 MHz
at 315 MHz
1 dB compression point (LNA, mixer,
Referred to RFin
IF amplifier)
Maximum input level
BER ≤10-3
FSK mode
ASK mode
Pin_max
dBm
-57
dBm
-22
-20
dBm
dBm
449
MHz
-93
-113
-90
-110
dBC/Hz
dBC/Hz
-55
-47
dBC
Local Oscillator
Operating frequency range VCO
fVCO
Phase noise VCO/LO
fosc = 432.92 MHz
At 1 MHz
At 10 MHz
Spurs of the VCO
At ±fXTO
299
L(fm)
KVCO
190
MHz/V
Loop bandwidth of the PLL
For best LO noise (design
parameter)
R1 = 820Ω
C9 = 4.7 nF
C10 = 1 nF
BLoop
100
kHz
Capacitive load at pin LF
The capacitive load at pin LF is
limited if bit check is used. The
limitation therefore also applies to
self-polling.
CLF_tot
XTO operating frequency
XTO crystal frequency appropriate
load capacitance must be connected
to XTAL
fXTAL = 6.764375 MHz (EU)
fXTAL = 4.90625 MHz (US)
fXTO
fXTO = 6.764 MHz
fXTO = 4.906 MHz
VCO gain
Series resonance resistor of the
crystal
Static capacitance at pin XTO to
GND
36
10
nF
+30 ppm
MHz
RS
150
220
Ω
Ω
C0
6.5
pF
-30 ppm
fXTAL
ATA5743
4839B–RKE–08/05
ATA5743
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
Parameters
Test Conditions
Symbol
Input matched according to
Figure 4-3
ASK (level of carrier)
BER ≤10-3, BW = 300 kHz
fin = 433.92 MHz/315 MHz
VS = 5V, Tamb = 25° C, fIF = 1 MHz
BR_Range0
BR_Range1
BR_Range2
BR_Range3
PRef_ASK
Input matched according to
Figure 4-3
ASK (level of carrier)
BER ≤10-3, BW = 600kHz
fin = 433.92 MHz/315 MHz
VS = 5V, Tamb = 25°C, fIF = 1 MHz
BR_Range0
BR_Range1
BR_Range2
BR_Range3
PRef_ASK
Min.
Typ.
Max.
Unit
-109
-107
-106
-104
-111
-109
-108
-106
-113
-111
-110
-108
dBm
dBm
dBm
dBm
-108
-106.5
-106
-104
-110
-108.5
-108
-106
-112
-110.5
-110
-108
dBm
dBm
dBm
dBm
Analog Signal Processing
Input sensitivity ASK
300 kHz IF-filter
Input sensitivity ASK
600 kHz IF-filter
Sensitivity variation ASK for the full
operating range compared to
Tamb = 25°C, VS = 5V
Sensitivity variation ASK for full
operating range including IF-filter
compared to Tamb = 25°C, VS = 5V
300 kHz and 600 kHz version
fin = 433.92 MHz/315 MHz
fIF = 1 MHz, PASK = PRef_ASK + ∆PRef
∆PRef
+2.5
-1.5
dB
300 kHz version
fin = 433.92 MHz/315 MHz
fIF = 0.89 MHz to 1.11 MHz
fIF = 0.86 MHz to 1.14 MHz
PASK = PRef_ASK + ∆PRef
∆PRef
+5.5
+7.5
-1.5
-1.5
dB
dB
600 kHz version
fin = 433.92 MHz/315 MHz
fIF = 0.79 MHz to 1.21 MHz
fIF = 0.73 MHz to 1.27 MHz
PASK = PRef_ASK + ∆PRef
∆PRef
+5.5
+7.5
-1.5
-1.5
dB
dB
37
4839B–RKE–08/05
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
BR_Range0
df = ±16 kHz
df = ±10 kHz to ±30 kHz
PRef_FSK
-101
-99
-104
-105.5
-105.5
dBm
dBm
BR_Range1
df = ±16 kHz
df = ±10 kHz to ±30 kHz
PRef_FSK
-99
-97
-102
-103.5
-103.5
dBm
dBm
BR_Range2
df = ±16 kHz
df = ±10 kHz to ±30 kHz
PRef_FSK
-97.5
-95.5
-100.5
-102
-102
dBm
dBm
BR_Range3
df = ±16 kHz
df = ±10 kHz to ±30 kHz
PRef_FSK
-95.5
-93.5
-98.5
-100
-100
dBm
dBm
BR_Range0
df = ±16 kHz
df = ±10 kHz to ±100 kHz
PRef_FSK
-101
-99
-104
-105.5
-105.5
dBm
dBm
BR_Range1
df = ±16 kHz
df = ±10 kHz to ±100 kHz
PRef_FSK
-99
-97
-102
-103.5
-103.5
dBm
dBm
BR_Range2
df = ±16 kHz
df = ±10 kHz to ±100 kHz
PRef_FSK
-97.5
-95.5
-100.5
-102
-102
dBm
dBm
BR_Range3
df = ±16 kHz
df = ±10 kHz to ±100 kHz
PRef_FSK
-95.5
-93.5
-98.5
-100
-100
dBm
dBm
∆PRef
+3
-1.5
dB
Input matched according to
Figure 4-3
BER ≤10-3, BW = 300 kHz
fin = 433.92 MHz/315 MHz
VS = 5V, Tamb = 25°C
fIF = 1 MHz
Input sensitivity FSK
300 kHz IF-filter
Input matched according to
Figure 4-3
BER ≤10-3, BW = 600 kHz
fin = 433.92 MHz/315 MHz
VS = 5V, Tamb = 25° C
fIF = 1 MHz
Input sensitivity FSK
600 kHz IF-filter
Sensitivity variation FSK for the full
operating range compared to
Tamb = 25°C, VS = 5V
38
300 kHz and 600 kHz version
fin = 433.92 MHz/315 MHz
fIF = 1 MHz
PFSK = PRef_FSK + ∆PRef
ATA5743
4839B–RKE–08/05
ATA5743
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
Parameters
Sensitivity variation FSK for the full
operating range including IF-filter
compared to Tamb = 25°C, VS = 5V
Test Conditions
Symbol
Min.
300 kHz version
fin = 433.92 MHz/ 315 MHz
fIF = 0.89 MHz to 1.11 MHz
fIF = 0.86 MHz to 1.14 MHz
fIF = 0.82 MHz to 1.18 MHz
PFSK = PRef_FSK + ∆PRef
∆PRef
600 kHz version
fin = 433.92 MHz/ 315 MHz
fIF = 0.85 MHz to 1.15 MHz
fIF = 0.80 MHz to 1.20 MHz
fIF = 0.74 MHz to 1.26 MHz
PFSK = PRef_FSK + ∆PRef
∆PRef
SNR to suppress inband noise
ASK mode
signals. Noise signals may have any
FSK mode
modulation scheme
SNRASK
SNRFSK
Dynamic range RSSI ampl.
DRRSSI
Lower cut-off frequency of the data
filter
CDEM = 33 nF
1
f cu_DF = ------------------------------------------------------------2 × π × 30 kΩ × CDEM
Recommended CDEM for best
performance
BR_Range0 (default)
BR_Range1
BR_Range2
BR_Range3
BR_Range0 (default)
Edge-to-edge time period of the input BR_Range1
data signal for full sensitivity
BR_Range2
BR_Range3
Upper cut-off frequency data filter
Upper cut-off frequency
programmable in 4 ranges
via a serial mode word
BR_Range0 (default)
BR_Range1
BR_Range2
BR_Range3
fcu_DF
Max.
Unit
+6
+8
+11
-2
-2
-2
dB
dB
dB
+6
+8
+11
-2
-2
-2
dB
dB
dB
12
3
dB
dB
60
0.11
fu
0.16
dB
0.20
39
22
12
8.2
CDEM
tee_sig
Typ.
270
156
89
50
2.8
4.8
8.0
15.0
3.4
6.0
10.0
19.0
nF
nF
nF
nF
1000
560
320
180
µs
µs
µs
µs
4.0
7.2
12.0
23.0
kHz
kHz
kHz
kHz
RSense connected from pin SENS
to VS, input matched according to
Figure 4-3
RSense = 56 kΩ, fin = 433.92 MHz,
at BW = 300 kHz
at BW = 600 kHz
Reduced sensitivity
kHz
dBm
(peak
level)
-71
-67
-76
-72
-81
-77
dBm
dBm
RSense = 100 kΩ, fin = 433.92 MHz,
at BW = 300 kHz
at BW = 600 kHz
-80
-76
-85
-81
-90
-86
dBm
dBm
RSense = 56 kΩ, fin = 315 MHz,
at BW = 300 kHz
at BW = 600 kHz
-72
-68
-77
-73
-82
-78
dBm
dBm
RSense = 100 kΩ, fin = 315 MHz,
at BW = 300 kHz
at BW = 600 kHz
-81
-77
-86
-82
-91
-87
dBm
dBm
PRef_Red
39
4839B–RKE–08/05
9. Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
(For typical values: VS = 5V, Tamb = 25°C)
Parameters
Test Conditions
= 56 kΩ
R
Reduced sensitivity variation over full Sense
RSense = 100 kΩ
operating range
PRed = PRef_Red + ∆PRed
Symbol
Min.
Typ.
Max.
Unit
∆PRed
5
6
0
0
0
0
dB
dB
∆PRed
∆PRed
∆PRed
∆PRed
∆PRed
∆PRed
0
-3.5
-6.0
-9.0
-11.0
-13.5
VThRESET
1.95
Values relative to RSense = 56 kΩ
Reduced sensitivity variation for
different values of RSense
RSense = 56 kΩ
RSense = 68 kΩ
RSense = 82 kΩ
RSense = 100 kΩ
RSense = 120 kΩ
RSense = 150 kΩ
PRed = PRef_Red + ∆PRed
Threshold voltage for reset
dB
dB
dB
dB
dB
dB
2.8
3.75
V
0.35
0.08
0.8
0.3
20
20
45
85
V
V
V
µA
mA
°C
0.35 × VS
V
V
Digital Ports
Data output
- Saturation voltage Low
- maximum voltage at pin DATA
- quiescent current
- short-circuit current
- ambient temperature in case of
permanent short-circuit
Data input
- Input voltage Low
- Input voltage High
Iol ≤12 mA
Iol = 2 mA
Voh = 20V
Vol = 0.8V to 20V
Voh = 0V to 20V
Vol
Vol
Voh
Iqu
Iol_lim
tamb_sc
VIl
Vich
13
30
0.65 × VS
DATA_CLK output
- Saturation voltage Low
- Saturation voltage High
IDATA_CLK = 1 mA
IDATA_CLK = -1 mA
Vol
Voh
VS - 0.4 V
0.1
VS - 0.15 V
0.4
V
V
IC_ACTIVE output
- Saturation voltage Low
- Saturation voltage High
IIC_ACTIVE = 1 mA
IIC_ACTIVE = -1 mA
Vol
Voh
VS-0.4 V
0.1
VS - 0.15 V
0.4
V
V
POLLING/_ON input
- Low level input voltage
- High level input voltage
Receiving mode
Polling mode
VIl
VIh
0.8 × VS
0.2 × VS
V
V
MODE input
- Low level input voltage
- High level input voltage
Division factor = 10
Division factor = 14
VIl
VIh
0.8 × VS
0.2 × VS
V
V
Test input must always be set to Low
VIl
0.2 × VS
V
TEST input
- Low level input voltage
40
ATA5743
4839B–RKE–08/05
ATA5743
10. Ordering Information
Extended Type Number
ATA5743P3-TKQY
Package
SSO20
Remarks
Taped and reeled, Pb-free, 300 kHz bandwidth
ATA5743P3-TKSY
SSO20
Tube, Pb-free, 300 kHz bandwidth
ATA5743P6-TKQY
SSO20
Taped and reeled, Pb-free, 600 kHz bandwidth
ATA5743P6-TKSY
SSO20
Tube, Pb-free, 600 kHz bandwidth
ATA5743P3-TGQY
SO20
Taped and reeled, Pb-free, 300 kHz bandwidth
ATA5743P3-TGSY
SO20
Tube, Pb-free, 300 kHz bandwidth
ATA5743P6-TGQY
SO20
Taped and reeled, Pb-free, 600 kHz bandwidth
ATA5743P6-TGSY
SO20
Tube, Pb-free, 600 kHz bandwidth
11. Package Information
41
4839B–RKE–08/05
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
1
10
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
42
Revision No.
History
4839B-RKE-08/05
•
•
•
•
Put datasheet in a new template
First page: Pb-free logo added
Page 41: Ordering Information changed
Page 42: Drawing SO20 added
ATA5743
4839B–RKE–08/05
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4839B–RKE–08/05