TEMIC U3741BM-M2FL

U3741BM
UHF ASK/FSK Receiver
Description
The U3741BM is a multi-chip PLL receiver device
supplied in an SO20 package. It has been specially
developed for the demands of RF low-cost data
transmission systems with low data rates from 1 kBaud to
10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester
or Bi-phase code. The receiver is well suited to operate
with the TEMIC PLL RF transmitter U2741B. Its main
applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in
the frequency receiving range of f0 = 300 MHz to
450 MHz for ASK or FSK data transmission. All the
statements made below refer to 433.92-MHz and
315-MHz applications.
Features
D Minimal external circuitry requirements, no RF
D ESD protection according to MIL-STD. 883
components on the PC board except adaptation to the
receiver antenna
(4KV HBM) except Pin POUT (2KV HBM)
D
D
D
D
High sensitivity, especially at low data rates
Sensitivity reduction possible even while receiving
D High image frequency suppression due to 1 MHz IF
in conjunction with a SAW front-end filter. Up to
40 dB is thereby achievable with newer SAWs.
D Programmable output port for sensitivity selection or
Fully integrated VCO
Low power consumption due to configurable self
polling with a programmable timeframe check
D Supply voltage 4.5 V to 5.5 V,
for controlling external periphery
D Communication to mC possible via a single,
bi-directional data line
operating temperature range –40°C to 105°C
D Single-ended RF input for easy adaptation to
l/4 antenna or printed antenna on PCB
D Low-cost solution due to high integration level
D Power management (polling) is also possible by
means of a separate pin via the mC
D 2 different IF bandwidth versions are available
(300 kHz and 600 kHz)
System Block Diagram
UHF ASK/FSK
Remote control transmitter
1 Li cell
UHF ASK/FSK
Remote control receiver
U3741BM
U2741B
Demod.
Encoder
M44Cx9x
Keys
Control
1...3
mC
PLL
IF Amp
Antenna Antenna
XTO
VCO
Power
amp.
PLL
LNA
XTO
VCO
14917
Figure 1. System block diagram
Rev. A1, 15-Oct-98
1 (25)
Preliminary Information
U3741BM
Ordering Information
Extended Type Number
U3741BM-M2FL
U3741BM-M2FLG3
U3741BM-M3FL
U3741BM-M3FLG3
Package
SO20
SO20
SO20
SO20
Remarks
2: IF bandwidth of 300 kHz, tube
2: IF bandwidth of 300 kHz, taped and reeled
3: IF bandwidth of 600 kHz, tube
3: IF bandwidth of 600 kHz, taped and reeled
Pin Description
SENS
1
20
DATA
FSK/ASK
2
19
ENABLE
CDEM
3
18
TEST
AVCC
4
17
POUT
AGND 5
16
MODE
DGND 6
15
DVCC
MIXVCC
7
14
XTO
LNAGND
8
13
LFGND
LNA_IN
9
12
LF
n.c. 10
11
LFVCC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
14844
Figure 2. Pinning SO20
17
18
19
20
Symbol
Function
SENS
Sensitivity-control resistor
FSK/ASK Selecting FSK/ASK
Low: FSK, High: ASK
CDEM Lower cut-off frequency data filter
AVCC
Analog power supply
AGND Analog ground
DGND Digital ground
MIXVCC Power supply mixer
LNAGND High-frequency ground LNA and
mixer
LNA_IN RF input
n.c.
Not connected
LFVCC Power supply VCO
LF
Loop filter
LFGND Ground VCO
XTO
Crystal oscillator
DVCC
Digital power supply
MODE Selecting 433.92 MHz /315 MHz
Low: 4.90625 MHz (USA)
High: 6.76438 (Europe)
POUT
Programmable output port
TEST
Test pin, during operation at GND
ENABLE Enables the polling mode
Low: polling mode off
(sleep mode)
H:
polling mode on
(active mode)
DATA
Data output / configuration input
2 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Block Diagram
VS
FSK/ASK–
Demodulator
and data filter
FSK/ASK
CDEM
RSSI
AVCC
50 kW
DEMOD_OUT
DATA
Limiter out
ENABLE
SENS
IF Amp
Sensitivity
reduction
Polling circuit
and
control logic
AGND
POUT
MODE
4. Order
DGND
TEST
FE
CLK
DVCC
Standby logic
LPF
3 MHz
MIXVCC
LFGND
LNAGND
LFVCC
IF Amp
LPF
3 MHz
VCO
XTO
XTO
f
LNA_IN
LNA
LF
64
15011
Figure 3. Block diagram
RF Front End
The RF front end of the receiver is a heterodyne
configuration that converts the input signal into a 1-MHz
IF signal. According to figure 3, the front end consists of
an LNA (low noise amplifier) LO (local oscillator), a
mixer and RF amplifier.
The LO generates the carrier frequency for the mixer via
a PLL synthesizer. The XTO (crystal oscillator) generates
the reference frequency fXTO. The VCO (voltagecontrolled oscillator) generates the drive voltage
frequency fLO for the mixer. fLO is dependent on the
voltage at Pin LF. fLO is divided by factor 64. The divided
frequency is compared to fXTO by the phase frequency
detector. The current output of the phase frequency
detector is connected to a passive loop filter and thereby
generates the control voltage VLF for the VCO. By means
of that configuration VLF is controlled in a way that
fLO/64 is equal to fXTO. If fLO is determined, fXTO can be
calculated using the following formula:
fXTO = fLO/64
The XTO is a one-pin oscillator that operates at the series
resonance of the quartz crystal. According to figure 4, the
crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal
supplier. The value of CL should be optimized for the
individual board layout to achieve the exact value of fXTO
and hereby of fLO. When designing the system in terms
of receiving bandwidth, the accuracy of the crystal and
the XTO must be considered.
Rev. A1, 15-Oct-98
3 (25)
Preliminary Information
U3741BM
VS
DVCC
MODE
f
+ 0 (USA) f + 314
MODE
f
+ 1 (Europe) f + 432.92
CL
XTO
LF
LFVCC
VS
R1
LO
IF
The relation is designed to achieve the nominal IF
frequency of fIF = 1 MHz for most applications. For
applications where fRF = 315 MHz, MODE must be set to
‘0’. In the case of fRF = 433.92 MHz, MODE must be set
to ‘1’. For other RF frequencies, fIF is not equal to 1 MHz.
fIF is then dependent on the logical level at Pin MODE and
on fRF. Table 1 summarizes the different conditions.
R1 = 820 W
C9 = 4.7 nF
C10 = 1 nF
LFGND
LO
IF
C10
C9
The RF input either from an antenna or from a generator
must be transformed to the RF input Pin LNA_IN. The
input impedance of that pin is provided in the electrical
parameters. The parasitic board inductances and
capacitances also influence the input matching. The RF
receiver U3741BM exhibits its highest sensitivity at the
best signal-to-noise ratio in the LNA. Hence, noise
matching is the best choice for designing the
transformation network.
Figure 4. PLL peripherals
The passive loop filter connected to Pin LF is designed for
a loop bandwidth of BLoop = 100 kHz. This value for
BLoop exhibits the best possible noise performance of the
LO. Figure 4 shows the appropriate loop filter
components to achieve the desired loop bandwidth. If the
filter components are changed for any reason please
notify that the maximum capacitive load at Pin LF is
limited. If the capacitive load is exceeded, a bitcheck may
no longer be possible since fLO cannot settle in time
before the bitcheck starts to evaluate the incoming data
stream. Self polling does therefore also not work in that
case.
A good practice when designing the network is to start
with power matching. From that starting point, the values
of the components can be varied to some extent to achieve
the best sensitivity.
If a SAW is implemented into the input network a mirror
frequency suppression of DPRef = 40 dB can be achieved.
There are SAWs available that exhibit a notch at
Df = 2 MHz. These SAWs work best for an intermediate
frequency of IF = 1 MHz. The selectivity of the receiver
is also improved by using a SAW. In typical automotive
applications, a SAW is used.
fLO is determined by the RF input frequency fRF and the
IF frequency fIF using the following formula:
fLO = fRF – fIF
To determine fLO, the construction of the IF filter must be
considered at this point. The nominal IF frequency is
fIF = 1 MHz. To achieve a good accuracy of the filter’s
corner frequencies, the filter is tuned by the crystal
frequency fXTO. This means that there is a fixed relation
between fIF and fLO. This relation is dependent on the
logic level at pin mode. This is described by the following
formulas:
Figure 5 shows a typical input matching network, for
fRF = 315 MHz and fRF = 433.92 MHz using a SAW.
Figure 6 illustrates an according input matching to 50 W
without a SAW. The input matching networks shown in
figure 6 are the reference networks for the parameters
given in the electrical characteristics.
Table 1. Calculation of LO and IF frequency
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
+
+
)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
+ )
+
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Conditions
fRF = 315 MHz, MODE = 0
fRF = 433.92 MHz, MODE = 1
300 MHz < fRF < 365 MHz, MODE = 0
365 MHz < fRF < 450 MHz, MODE = 1
Local Oscillator Frequency
fLO = 314 MHz
fLO = 432.92 MHz
f RF
f LO
1
1 314
f LO
f RF
1
1
432.92
4 (25)
Intermediate Frequency
fIF = 1 MHz
fIF = 1 MHz
f RF
f LO
314
f LO
f RF
432.92
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
8 LNAGND
8
U3741BM
9
C3
L
22p
25n
L2
TOKO LL2012
F33NJ
RFIN
33n
C2
1
IN
2
IN_GND
8.2p
9
C3
L
47p
25n
L3
27n
8.2p
100p
fRF = 315 MHz
TOKO LL2012
F27NJ
B3555
OUT
OUT_GND
CASE_GND
3,4 7,8
LNA_N
C16
C17
100p
fRF = 433.92 MHz
U3741BM
LNA_N
C16
LNAGND
L2
TOKO LL2012
F82NJ
RFIN
5
6
82n
C2
1
IN
2
IN_GND
10p
C17
L3
47n
22p
TOKO LL2012
F47NJ
B3551
OUT
OUT_GND
CASE_GND
3,4 7,8
14105
5
6
14106
Figure 5. Input matching network with SAW filter
fRF = 433.92 MHz
fRF = 315 MHz
8 LNAGND
8 LNAGND
U3741BM
9
25n
15p
U3741BM
9
LNA_N
25n
33p
RFIN
LNA_N
RFIN
3.3p
3.3p
100p
22n
100p
39n
TOKO LL2012
F22NJ
TOKO LL2012
F39NJ
14107
14108
Figure 6. Input matching network without SAW filter
Please notify that for all coupling conditions (see
figures 5 and 6), the bond wire inductivity of the LNA
ground is compensated. C3 forms a series resonance
circuit together with the bond wire. L = 25 nH is a feed
inductor to establish a DC path. Its value is not critical but
must be large enough not to detune the series resonance
circuit. For cost reduction this inductor can be easily
printed on the PCB. This configuration improves the
sensitivity of the receiver by about 1 dB to 2 dB.
Analog Signal Processing
IF Amplifier
The signals coming from the RF front end are filtered by
the fully integrated 4th-order IF filter. The IF center
frequency is fIF = 1 MHz for applications where
fRF = 315 MHz or fRF = 433.92 MHz is used. For other
RF input frequencies refer to table 1 to determine the
center frequency.
The U3741BM is available with 2 different IF
bandwidths. U3741BM-M2, the version with
BIF = 300 kHz, is well suited for ASK systems where the
TEMIC PLL transmitter U2741B is used. The receiver
U3741BM - M3 employs an IF bandwidth of
fIF = 600 kHz. This version can be used together with the
U2741B in FSK and ASK mode. If used in ASK
applications, it allows higher tolerances for the receiver
and PLL transmitter crystals. SAW transmitters exhibit
much higher transmit frequency tolerances compared to
PLL transmitters. Generally, it is necessary to use
BIF = 600 kHz together with such transmitters.
Rev. A1, 15-Oct-98
5 (25)
Preliminary Information
U3741BM
RSSI Amplifier
FSK/ASK Demodulator and Data Filter
The subsequent RSSI amplifier enhances the output
signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is
DRRSSI = 60 dB. If the RSSI amplifier is operated within
its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter
signal, the S/N ratio is defined by the ratio of the
maximum RSSI output voltage and the RSSI output
voltage due to a disturber. The dynamic range of the RSSI
amplifier is exceeded if the RF input signal is about 60 dB
higher compared to the RF input signal at full sensitivity.
The signal coming from the RSSI amplifier is converted
into the raw data signal by the ASK/FSK demodulator.
The operating mode of the demodulator is set via Pin
ASK/FSK. Logic ‘L’ sets the demodulator to FSK,
applying ‘H’ sets it into ASK mode.
In FSK mode the S/N ratio is not affected by the dynamic
range of the RSSI amplifier.
In ASK mode an automatic threshold control circuit
(ATC) is employed to set the detection reference voltage
to a value where a good signal-to-noise ratio is achieved.
This circuit also implies the effective suppression of any
kind of inband noise signals or competing transmitters.
If the S/N ratio exceeds 10 dB, the data signal can be
detected properly.
The output voltage of the RSSI amplifier is internally
compared to a threshold voltage VTh_red. VTh_red is
determined by the value of the external resistor RSense.
RSense is connected between Pin Sense and GND or VS.
The output of the comparator is fed into the digital control
logic. By this means it is possible to operate the receiver
at a lower sensitivity.
The FSK demodulator is intended to be used for an FSK
deviation of Df ≥ 20 kHz. Lower values may be used but
the sensitivity of the receiver is reduced in that condition.
The minimum usable deviation is dependent on the
selected baudrate. In ASK mode, only BR_Range0 and
BR_Range1 are available. In FSK mode, the data signal
can be detected if the S/N Ratio exceeds 2 dB.
If RSense is connected to VS, the receiver operates at a
lower sensitivity. The reduced sensitivity is defined by the
value of RSense, the maximum sensitivity by the signal-tonoise ratio of the LNA input. The reduced sensitivity is
dependent on the signal strength at the output of the RSSI
amplifier.
The output signal of the demodulator is filtered by the
data filter before it is fed into the digital signal processing
circuit. The data filter improves the S/N ratio as its
passband can be adopted to the characteristics of the data
signal. The data filter consists of a 1st-order highpass and
a 1st-order lowpass filter.
Since different RF input networks may exhibit slightly
different values for the LNA gain the sensitivity values
given in the electrical characteristics refer to a specific
input matching. This matching is illustrated in figure 6
and exhibits the best possible sensitivity.
The highpass filter cut-off frequency is defined by an
external capacitor connected to Pin CDEM. The cut-off
frequency of the highpass filter is defined by the
following formula:
RSense can be connected to VS or GND via a µC or by the
digital output port POUT of the U3741BM receiver IC.
The receiver can be switched from full sensitivity to
reduced sensitivity or vice versa at any time. In polling
mode the receiver will not wake up if the RF input signal
does not exceed the selected sensitivity. If the receiver is
already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the
reduced sensitivity. Instead of the data stream, the pattern
according to figure 7 is issued at Pin DATA to indicate
that the receiver is still active.
fcu_DF
DATA
tmin2
t DATA_L_max
Figure 7. Steady L state limited DATA output pattern
+2
p
1
30 kW
CDEM
In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore,
CDEM cannot be increased to very high values if selfpolling is used. On the other hand CDEM must be large
enough to meet the data filter requirements according to
the data signal. Recommended values for CDEM are
given in the electrical characteristics. The values are
slightly different for ASK and FSK mode.
The cut-off frequency of the lowpass filter is defined by
the selected baudrate range (BR_Range). BR_Range is
defined in the OPMODE register (refer to chapter
‘Configuration of the Receiver’). BR_Range must be set
in accordance to the used baudrate.
6 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
The U3741BM is designed to operate with data coding
where the DC level of the data signal is 50%. This is valid
for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain
within the range of VDC_min = 33% and VDC_max = 66%.
The sensitivity may be reduced by up to 1.5 dB in that
condition.
Each BR_Range is also defined by a minimum and a
maximum edge-to-edge time (tee_sig). These limits are
defined in the electrical characteristics. They should not
be exceeded to maintain full sensitivity of the receiver.
Receiving Characteristics
The RF receiver U3741BM can be operated with and
without a SAW front end filter. In a typical automotive
application, a SAW filter is used to achieve better
selectivity. The selectivity with and without a SAW front
end filter is illustrated in figure 8. This example relates to
ASK mode and the 300-kHz bandwidth version of the
U3741BM. FSK mode and the 600-kHz version of the
receiver exhibit similar behavior. Note that the mirror
frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used,
an insertion loss of about 4 dB must be considered.
When designing the system in terms of receiving
bandwidth, the LO deviation must be considered as it also
determines the IF center frequency. The total LO
deviation is calculated to be the sum of the deviation of
the crystal and the XTO deviation of the U3741BM. Lowcost crystals are specified to be within ±100 ppm. The
XTO deviation of the U3741BM is an additional deviation due to the XTO circuit. This deviation is specified
to be ±30 ppm. If a crystal of ±100 ppm is used, the total
deviation is ±130 ppm in that case. Note that the receiving
bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.
Polling Circuit and Control logic
The receiver is designed to consume less than 1 mA while
being sensitive to signals from a corresponding
transmitter. This is achieved via the polling circuit. This
circuit enables the signal path periodically for a short
time. During this time the bitcheck logic verifies the
presence of a valid transmitter signal. Only if a valid
signal is detected the receiver remains active and
transfers the data to the connected µC. If there is no valid
signal present the receiver is in sleep mode most of the
time resulting in low current consumption. This condition
is called polling mode. A connected µC is disabled during
that time.
All relevant parameters of the polling logic can be
configured by the connected µC. This flexibility enables
the user to meet the specifications in terms of current
consumption, system response time, data rate etc.
Regarding the number of connection wires to the mC, the
receiver is very flexible. It can be either operated by a
single bi-directional line to save ports to the connected
mC. Or it can be operated by up to three uni-directional
ports.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the
analog filtering is derived from one clock. According to
figure 9, this clock cycle TClk is derived from the crystal
oscillator (XTO) in combination with a divider. The
division factor is controlled by the logical state at Pin
MODE. According to chapter ‘RF Front End’, the
frequency of the crystal oscillator (fXTO) is defined by the
RF input signal (fRFin) which also defines the operating
frequency of the local oscillator (fLO).
0
–10
without SAW
TClk
–20
MODE
dP ( dBm )
–30
Divider
:14/:10
–40
–50
f
–60
XTO
16
L : USA(:10)
H: Europe(:14)
DVCC
15
–70
with SAW
–80
XTO
–90
XTO
14
–100
–6 –5 –4 –3 –2 –1 0
1
2
3
4
5
6
df ( MHz )
Figure 8. Receiving frequency response
Figure 9. Generation of the basic clock cycle
Rev. A1, 15-Oct-98
7 (25)
Preliminary Information
U3741BM
Pin MODE can now be set in accordance with the desired
clock cycle TClk. TClk controls the following applicationrelevant parameters:
dependent on the duty cycle of the active mode and can
be calculated as:
D Timing of the polling circuit including bitcheck
I Spoll
D Timing of the analog and digital signal processing
D Timing of the register programming
D Frequency of the reset marker
D IF filter center frequency (fIF0)
Most applications are dominated by two transmission
frequencies: fSend = 315 MHz is mainly used in USA,
fSend = 433.92 MHz in Europe. In order to ease the usage
of all TClk-dependent parameters on this electrical
characteristics display three conditions for each parameter.
(fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
D Application Europe
(fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
D Other applications
(TClk is dependent on fXTO and on the logical state of
Pin MODE. The electrical characteristic is given as a
function of TClk).
The clock cycle of some function blocks depends on the
selected baud rate range (BR_Range) which is defined in
the OPMODE register. This clock cycle TXClk is defined
by the following formulas for further reference:
TXClk = 8 × TClk
TXClk = 4 × TClk
TXClk = 2 × TClk
TXClk = 1 × TClk
Polling Mode
According to figure 5 the receiver stays in polling mode
in a continuous cycle of three different modes. In sleep
mode the signal processing circuitry is disabled for the
time period TSleep while consuming low current of
IS = ISoff. During the start-up period, TStartup, all signal
processing circuits are enabled and settled. In the
following bitcheck mode, the incoming data stream is
analyzed bit by bit contra a valid transmitter signal. If no
valid signal is present, the receiver is set back to sleep
mode after the period TBitcheck. This period varies check
by check as it is a statistical process. An average value for
TBitcheck is given in the electrical characteristics. During
TStartup and TBitcheck the current consumption is IS = ISon.
The average current consumption in polling mode is
T Sleep
T Sleep
Soff
)I
)T
)
(T Startup T Bitcheck)
T Bitcheck
Startup
Son
)
During TSleep and TStartup the receiver is not sensitive to
a transmitter signal. To guarantee the reception of a
transmitted command the transmitter must start the
telegram with an adequate preburst. The required length
of the preburst is dependent on the polling parameters
TSleep, TStartup, TBitcheck and the startup time of a
connected µC (TStart,µC). TBitcheck thus depends on the
actual bitrate and the number of bits (NBitcheck) to be
tested.
The following formula indicates how to calculate the
preburst length.
TPreburst
D Application USA
BR_Range = BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
+I
wT
Sleep
+ TStartup + TBitcheck + TStart_mC
Sleep Mode
The length of period TSleep is defined by the 5-bit word
Sleep of the OPMODE register, the extension factor
XSleep, according to table 10, and the basic clock cycle
TClk. It is calculated to be:
TSleep = Sleep
XSleep
1024
TClk
In US- and European applications, the maximum value of
TSleep is about 60 ms if XSleep is set to 1. The time
resolution is about 2 ms in that case. The sleep time can
be extended to almost half a second by setting XSleep
to 8. XSleep can be set to 8 by bit XSleepStd or by bit
XSleepTemp resulting in a different mode of action as
described below:
XSleepStd = 1 implies the standard extension factor.
The sleep time is always extended.
XSleepTemp = 1 implies the temporary extension factor.
The extended sleep time is used as long as every bitcheck
is OK. If the bitcheck fails once, this bit is set back to 0
automatically resulting in a regular sleep time. This
functionality can be used to save current in presence of a
modulated disturber similar to an expected transmitter
signal. The connected µC is activated rarely in that
condition. If the disturber disappears, the receiver
switches back to regular polling and is again sensitive to
appropriate transmitter signals.
According to table 7, the highest register value of Sleep
sets the receiver into a permanent sleep condition. The
receiver remains in that condition until another value for
Sleep is programmed into the OPMODE register. This
function is desirable where several devices share a single
data line.
8 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling
logic is enabled.
IS = ISoff
TSleep = Sleep × XSleep × 1024 × TClk
Sleep:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleepStd and XSleepTemp
according to table 8
Basic clock cycle defined by fXTO
and Pin MODE
Is defined by the selected baud rate
range and TClk. The baud rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
XSleep:
TClk:
TStartup:
Start-up mode:
The signal processing circuits are
enabled. After the start-up time
(TStartup) all circuits are in stable
condition and ready to receive.
IS = ISoff
TStartup
NO
Bitcheck mode:
The incomming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver is
set to receiving mode. Otherwise it is
set to Sleep mode.
IS = ISoff
TBitcheck
Bitcheck
OK ?
TBitcheck:
Depends on the result of the
bitcheck
If the bitcheck is ok, TBitcheck
depends on the number of bits to be
checked (NBitcheck) and on the
utilized data rate.
If the bitcheck fails, the average
time period for that check depends
on the selected baud rate range and
on TClk. The baud rate range is
defined by Baud0 and Baud1 in the
OPMODE register.
YES
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected mC. It can be set to Sleep
mode through an OFF command via
Pin DATA or ENABLE.
IS = ISoff
OFF command
Figure 10. Polling mode flow chart
( Number of checked Bits: 3 )
Bitcheck ok
Enable IC
Bitcheck
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
DATA
Polling – Mode
Receiving mode
Figure 11. Timing diagram for complete sucessful bitcheck
Rev. A1, 15-Oct-98
9 (25)
Preliminary Information
U3741BM
Bitcheck Mode
In bitcheck mode the incoming data stream is examined
to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by
subsequent time frame checks where the distances
between 2 signal edges are continuously compared to a
programmable time window. The maximum count of this
edge-to-edge tests before the receiver switches to
receiving mode is also programmable.
Configuring the bitcheck
Assuming a modulation scheme that contains 2 edges per
bit, two time frame checks are verifying one bit. This is
valid for Manchester, Bi-phase and most other
modulation schemes. The maximum count of bits to be
checked can be set to 0, 3, 6 or 9 bits via the variable
NBitcheck in the OPMODE register. This implies 0, 6, 12
and 18 edge to edge checks respectively. If NBitcheck is set
to a higher value, the receiver is less likely to switch to
receiving mode due to noise. In the presence of a valid
transmitter signal, the bitcheck takes less time if NBitcheck
is set to a lower value. In polling mode, the bitcheck time
is not dependent on NBitcheck. Figure 11 shows an
example where 3 bits are tested successfully and the data
signal is transferred to Pin DATA.
According to figure 12, the time window for the bitcheck
is defined by two separate time limits. If the edge-to-edge
time tee is in between the lower bitcheck limit TLim_min
and the upper bitcheck limit TLim_max, the check will be
continued. If tee is smaller than TLim_min or tee exceeds
TLim_max, the bitcheck will be terminated and the receiver
switches to sleep mode.
1/fSig
Dem_out
t ee
TLim_min
TLim_max
Figure 12. Valid time window for bitcheck
For best noise immunity it is recommended to use a low
span between TLim_min and TLim_max. This is achieved
using a fixed frequency at a 50% duty cycle for the
transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence
in Manchester or Bi-phase is a good choice concerning
that advice. A good compromise between receiver
sensitivity and susceptibility to noise is a time window of
± 25% regarding the expected edge-to-edge time tee.
Using pre-burst patterns that contain various edge-toedge time periods, the bitcheck limits must be
programmed according to the required span.
The bitcheck limits are determined by means of the
formula below.
TLim_min = Lim_min × TXClk
TLim_max = (Lim_max –1) × TXClk
Lim_min and Lim_max are defined by a 5-bit word each
within the LIMIT register.
Using above formulas Lim_min and Lim_max can be
determined according to the required TLim_min, TLim_max
and TXClk. The time resolution in defining TLim_min and
TLim_max is TXClk. The minimum edge-to-edge time tee
(tDATA_L_min, tDATA_H_min) is defined according to the
chapter ‘Receiving Mode’. Due to this, the lower limit
should be set to Lim_min ≥ 10. The maximum value of
the upper limit is Lim_max = 63.
Figures 13, 14 and 15 are illustrating the bitcheck
for the default bitcheck limits Lim_min = 14 and
Lim_max = 24. When the IC is enabled, the signal
processing circuits are enabled during TStartup. The output
of the ASK/ FSK demodulator (Dem_out) is undefined
during that period. When the bitcheck becomes active,
the bitcheck counter is clocked with the cycle TXClk.
Figure 13 shows how the bitcheck proceeds if the bitcheck counter value CV_Lim is within the limits defined
by Lim_min and Lim_max at the occurrence of a signal
edge. In figure 14 the bitcheck fails as the value CV_lim
is lower than the limit Lim_min. The bitcheck also fails
if CV_Lim reaches Lim_max. This is illustrated in
figure 15.
( Lim_min = 14, Lim_max = 24 )
Bitcheck ok
Bitcheck ok
Enable IC
TStartup
Bitcheck
1/2 Bit
1/2 Bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4
1/2 Bit
Dem_out
Bitcheck–Counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
TClk
Figure 13. Timing diagram during bitcheck
10 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
( Lim_min = 14, Lim_max = 24 )
Bitcheck failed ( CV_Lim < Lim_min )
Enable IC
Bitcheck
1/2 Bit
Dem_out
Bitcheck–Counter
0
Startup – Mode
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12
0
Sleep–Mode
Bitcheck – Mode
Figure 14. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_min)
( Lim_min = 14, Lim_max = 24 )
Bitcheck failed ( CV_Lim = Lim_max )
Enable IC
Bitcheck
1/2 Bit
Dem_out
Bitcheck–Counter
0
Startup – Mode
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Bitcheck – Mode
0
Sleep–Mode
Figure 15. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_max)
Duration of the Bitcheck
If no transmitter signal is present during the bitcheck, the
output of the ASK/ FSK demodulator delivers random
signals. The bitcheck is a statistical process and TBitcheck
varies for each check. Therefore, an average value for
TBitcheck is given in the electrical characteristics.
TBitcheck depends on the selected baudrate range and on
TClk. A higher baudrate range causes a lower value for
TBitcheck resulting in a lower current consumption for
polling mode.
In the presence of a valid transmitter signal, TBitcheck is
dependant on the frequency of that signal, fSig and the
count of the checked bits, NBitcheck. A higher value for
NBitcheck thereby results in a longer period for TBitcheck
requiring a higher value for the transmitter pre-burst
TPreburst.
Receiving Mode
If the bitcheck is successful for all bits specified by
NBitcheck, the receiver switches to receiving mode.
According to figure 11, the internal data signal is
switched to Pin DATA in that case. A connected µC can
be woken up by the negative edge at Pin DATA. The
receiver stays in that condition until it is switched back to
polling mode explicitly.
Digital Signal Processing
The data from the ASK/ FSK demodulator (Dem_out) is
digitally processed in different ways and as a result
converted into the output signal data. This processing
depends on the selected baudrate range (BR_Range).
Figure 16 illustrates how Dem_out is synchronized by the
extended clock cycle TXClk. This clock is also used for the
Bitcheck counter. Data can change its state only after
TXClk elapsed. The edge-to-edge time period tee of the
Data signal as a result is always an integral multiple of
TXClk.
The minimum time period between two edges of the data
signal is limited to tee ≥ TDATA_min. This implies an
efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at
DATA. This eases the interrupt handling of a connected
µC. TDATA_min is to some extent affected by the preceding
edge-to-edge time interval tee as illustrated in figure 17.
If tee is in between the specified bitcheck limits, the
following level is frozen for the time period
TDATA_min = tmin1, in case of tee being outside that
bitcheck limits TDATA_min = tmin2 is the relevant stable
time period.
The maximum time period for DATA to be Low is limited
to TDATA_L_max. This function is employed to ensure a
finite response time in programming or switching off the
receiver via Pin DATA. TDATA_L_max is thereby longer
than the maximum time period indicated by the
transmitter data stream. Figure 18 gives an example
where Dem_out remains Low after the receiver is in
receiving mode.
Rev. A1, 15-Oct-98
11 (25)
Preliminary Information
U3741BM
T XClk
Clock Bitcheck
counter
Dem_out
DATA
t ee
Figure 16. Synchronization of the demodulator output
Dem_out
DATA
Lim_min <= CV_Lim < Lim_max
t
tmin1
ee
CV_Lim < Lim_min or CV_Lim >= Lim_max
t
tmin2
ee
Figure 17. Debouncing of the demodulator output
Enable IC
Bitcheck
Dem_out
DATA
Sleep – Mode
Bitcheck – Mode
Receiving mode
tmin2
t DATA_L_max
Figure 18. Steady L state limited DATA output pattern after transmission
After the end of a data transmission the receiver remains
active and random noise pulses appear at Pin DATA. The
edge-to-edge time period tee of the majority of these noise
pulses is equal or slightly higher than TDATA_min.
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via Pin
DATA or via Pin ENABLE.
When using Pin DATA, this pin must be pulled to Low for
the period t1 by the connected µC. Figure 19 illustrates
the timing of the OFF command (see also figure 23). The
minimum value of t1 depends on BR_Range. The
maximum value for t1 is not limited but it is
recommended not to exceed the specified value to
prevent erasing the reset marker. This item is explained
in more detail in the chapter ‘Configuration of the
Receiver’. Setting the receiver to sleep mode via DATA
is achieved by programming bit 1 of the OPMODE
register to be ‘1’. Only one sync pulse (t3) is issued.
The duration of the OFF command is determined by the
sum of t1, t2 and t10. After the OFF command initially the
sleep time TSleep elapses. Note that the capacitive load at
Pin DATA is limited. The resulting time constant t
together with an optional extenal pull-up resistor may not
be exceeded to ensure proper operation.
If the receiver is set to polling mode via Pin ENABLE, a
‘L’ pulse (TDoze) must be issued at that pin. Figure 20
illustrates the timing of that command. After the positive
edge of this pulse the sleep time TSleep elapses. The
receiver remains in sleep mode as long as ENABLE is
held to ‘L’. If the receiver is polled exclusively by a µC,
TSleep can be programmed to 0 to enable a instantaneous
response time. This command is the faster option than via
Pin DATA at the cost of an additional connection to the
µC.
12 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
t1
t2
t3
t5
t4
t10
t7
Out1 (mC)
DATA (U3741BM)
X
X
Serial bi–directional
data line
X
X
Bit 1
(”1”)
(Startbit)
Receiver
on
Startup mode
T Sleep
OFF Command
Figure 19. Timing diagram of the OFF-command via Pin DATA
TDoze
TSleep
toff
ENABLE
DATA (U3741BM)
X
X
Serial bi–directional
data line
X
X
Receiver on
Startup mode
Figure 20. Timing diagram of the OFF-command via Pin ENABLE
Configuration of the Receiver
The U3741BM receiver is configured via two 12-bit
RAM registers called OPMODE and LIMIT. The
registers can be programmed by means of the
bi-directional DATA port. If the register contents have
changed due to a voltage drop, this condition is indicated
by a certain output pattern called reset marker (RM). The
receiver must be reprogrammed in that case. After a
power-on reset (POR), the registers are set to default
mode. If the receiver is operated in default mode, there is
no need to program the registers.
Table 3 shows the structure of the registers. According to
table 2, bit 1 defines if the receiver is set back to polling
mode via the OFF command, (see chapter ‘Receiving
Mode’) or if it is programmed. Bit 2 represents the
register address. It selects the appropriate register to be
programmed.
Table 2. Effect of Bit 1 and Bit 2 in programming the registers
Bit 1 Bit 2
Action
1
x
The receiver is set back to polling
mode (OFF command)
0
1
The OPMODE register is programmed
0
0
The LIMIT register is programmed
Table 4 and the following illustrate the effect of the individual configuration words. The default configuration is
highlighted for each word.
BR_Range sets the appropriate baud rate range. At the
same time it defines XLim. XLim is used to define the
bitcheck limits TLim_min and TLim_max as shown in
table 4.
POUT can be used to control the sensitivity of the
receiver. In that application, POUT is set to 1 to reduce the
sensitivity. This implies that the receiver operates with
full sensitivity after a POR.
Rev. A1, 15-Oct-98
13 (25)
Preliminary Information
U3741BM
Table 3. Effect of the configuration words within the registers
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Baud1
Baud0
BitChk1
BitChk0
0
0
1
Lim_min5
Lim_min4
0
0
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
POUT
Sleep4
Sleep3
0
0
0
Lim_min3
Lim_min2
Lim_min1
1
1
1
Bit14
Sleep2
Sleep1
Sleep0
XSleep Std
XSleep Temp
1
0
1
1
0
0
Lim_min0
Lim_max5
Lim_max4
Lim_max3
Lim_max2
Lim_max1
Lim_max0
0
0
1
1
0
0
0
OFF command
1
OPMODE register
0
1
0
1
BR_Range
(Default)
NBitcheck
VPOUT
Sleep
XSleep
LIMIT register
0
0
0
0
Lim_min
(Default)
Lim_max
Table 4. Effect of the configuration word BR_Range
BR_Range
Baudrate Range
g / Extension Factor for Bitcheck Limits (XLim)
Baud1
Baud0
0
0
BR_Range0 (application USA / Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
0
1
XLim = 8 (Default)
BR_Range1 (application USA / Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
1
0
XLim = 4
BR_Range2 (application USA / Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
1
1
XLim = 2
BR_Range3 (Application USA / Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1
Table 5. Effect of the configuration word NBitcheck
NBitcheck
BitChk1
0
0
1
1
Number of Bits to be Checked
BitChk0
0
1
0
1
0
3
6 (Default)
9
Table 6. Effect of the configuration Bit VPOUT
VPOUT
POUT
0
1
Level of the Multi-Purpose Output Port POUT
0 (Default)
1
14 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Table 7. Effect of the configuration word Sleep
Start Value for Sleep Counter (TSleep = Sleep × Xsleep × 1024 × TClk)
Sleep
Sleep4
0
0
0
0
.
Sleep3
0
0
0
0
.
Sleep2
0
0
0
0
.
Sleep1
0
0
1
1
.
Sleep0
0
1
0
1
.
0 (Receiver is continuously polling until a valid signal occurs)
1 (TSleep ≈ 2ms for XSleep =1 in US- / European applications)
2
3
.
.
.
.
.
.
.
.
0
.
.
1
.
.
0
.
.
1
.
.
1
.
.
11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default)
.
.
.
.
.
.
.
.
1
1
1
.
1
1
1
.
1
1
1
.
0
1
1
.
1
0
1
.
29
30
31 (Permanent sleep mode)
Table 8. Effect of the configuration word XSleep
XSleep
XSleepStd
XSleepTemp
0
0
0
1
1
0
1
1
Table 9. Effect of the configuration word Lim_min
Lim_min
Lim_min < 10 is not applicable
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
Extension Factor for Sleepp Time (TSleepp = Sleep
p × Xsleep
p × 1024 × TClk)
1 (Default)
8 (XSleep is reset to 1 if bitcheck fails once)
8 (XSleep is set permanently)
8 (XSleep is set permanently)
1
1
0
0
1
0
1
0
1
0
Lower Limit Value for Bitcheck
(TLim_min = Lim_min × XLim × TClk)
10
11
12
13
14 (Default)
(USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
Rev. A1, 15-Oct-98
61
62
63
15 (25)
Preliminary Information
U3741BM
Table 10.Effect of the configuration word Lim_max
Lim_max
Lim_max < 12 is not applicable
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
.
0
0
1
.
0
1
0
.
.
.
.
.
.
.
.
.
.
.
.
.
0
1
1
0
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
Upper Limit Value for Bitcheck
(TLim_max = (Lim_max –1) × XLim × TClk)
12
13
14
24 (Default)
(USA: TLim_max = 375 µs, Europe: TLim_max = 381 µs)
Conservation of the Register Information
The U3741BM implies an integrated power-on reset and
brown–out detection circuitry to provide a mechanism to
preserve the RAM register information.
According to figure 21, a power-on reset (POR) is
generated if the supply voltage VS drops below the
threshold voltage VThReset. The default parameters are
programmed into the configuration registers in that
condition. Once VS exceeds VThReset the POR is canceled
after the minimum reset period tRst. A POR is also
generated when the supply voltage of the receiver is
turned on.
To indicate that condition, the receiver displays a reset
marker (RM) at Pin DATA after a reset. The RM is
V
61
62
63
represented by the fixed frequency fRM at a 50% duty
cycle. RM can be canceled via an ‘L’ pulse t1 at Pin
DATA. The RM implies the following characteristics:
D fRM is lower than the lowest feasible frequency of a
data signal. By this means, RM cannot be misinterpreted by the connected µC.
D If the receiver is set back to polling mode via pin
DATA, RM cannot be canceled by accident if t1 is
applied according to the proposal in the section
‘Programming the configuration registers’.
By means of that mechanism the receiver cannot lose its
register information without communicating that condition via the reset marker RM.
S
V
ThReset
POR
t Rst
DATA (U3741BM)
X
1 / f RM
Figure 21. Generation of the power on reset
16 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
t1
t2
t3
t9
t5
t4
TSleep
t8
t6
t7
Out1 (µC)
DATA (U3741BM)
X
X
Serial bi–directional
data line
X
X
Bit 1
(”0”)
(Startbit)
Receiver
on
Bit 2
(”1”)
(Register–
select)
Programming Frame
Bit 13
(”0”)
(Poll8)
Bit 14
(”1”)
(Poll8R)
Startup
mode
Figure 22. Timing of the register programming
Programming the Configuration Register
The configuration registers are programmed serially via
the bi-directional data line according to figure 22 and
figure 23.
mC
U3741BM
internal pull-up
resistor
bi-directional
data-line
DATA
I/O
Out1 ( m C)
Data (U3741BM)
Programming of a register is possible both in the sleep–
and in active-mode of the receiver.
During programming, the LNA, LO, lowpass filter IFamplifier and the FSK/ASK Manchester demodulator are
disabled.
The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to ‘1’, it
represents the OFF-command to set the receiver back to
polling mode at the same time. For the length of the
programming start pulse t1, the following convention
should be considered:
D t1(min) < t1 < 1535 × TClk: [t1(min) is the minimum
Figure 23. One wire connection to a mC
To start programming, the serial data line DATA is pulled
to ‘L’ for the time period t1 by the µC. When DATA has
been released, the receiver becomes the master device.
When the programming delay period t2 has elapsed it
emits 14 subsequent synchronization pulses with the
pulse length t3. After each of these pulses a programming
window occurs. The delay until the program window
starts is determined by t4, the duration is defined by t5.
Within the programming window, the individual bits are
set. If the µC pulls down Pin DATA for the time period t7
during t5, the according bit is set to ‘0’. If no programming pulse t7 is issued, this bit is set to ‘1’. All 14 bits are
subsequently programmed in this way. The time frame to
program a bit is defined by t6.
Bit 14 is followed by the equivalent time window t9. During this window the equivalent acknowledge pulse t8
(E_Ack) occurs if the just programmed modeword is
equivalent to the modeword that was already stored in
that register. E_Ack should be used to verify that the
modeword was correctly transferred to the register. The
register must be programmed twice in that case.
specified value for the relevant BR_Range]
Programming respectively OFF-command is initiated if
the receiver is not in reset mode. If the receiver is in reset
mode programming respectively Off-command is not
initiated and the reset marker RM is still present at Pin
DATA.
This period is generally used to switch the receiver to
polling mode. In a reset condition, RM is not canceled by
accident.
D t1 > 5632 × TClk
Programming respectively OFF-command is initiated in
any case. RM is canceled if present.
This period is used if the connected µC detected RM. If
a configuration register is programmed this time period
for t1 can generally be used.
Note that the capacitive load at Pin DATA is limited. The
resulting time constant t together with an optional extenal
pull-up resistor may not be exceeded to ensure proper
operation.
Rev. A1, 15-Oct-98
17 (25)
Preliminary Information
U3741BM
Absolute Maximum Ratings
Parameters
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
Maximum input level, input matched to 50 W
Symbol
Ptot
Tj
Tstg
Tamb
Pin_max
Min.
Typ.
Max.
450
150
+125
+105
10
–55
–40
Unit
mW
°C
°C
°C
dBm
Thermal Resistance
Parameters
Symbol
RthJA
Junction ambient
Value
100
Unit
K/W
Electrical Characteristics
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz,
unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameter
Test Condition
Symbol
6.76438 MHz Osc.
(MODE: 1)
Min.
Typ.
Max.
4.90625 MHz Osc.
(MODE: 0)
Min.
Typ.
Max.
Variable Oscillator
Min.
Typ.
Unit
Max.
Basic clock cycle of the digital circuitry
Basic clock
cycle
Extended
basic clock
cycle
MODE = 0 (USA)
MODE = 1 (Europe)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TClk
2.0383
TXClk
2.0697
16.6
8.3
4.1
2.1
16.3
8.2
4.1
2.0
Sleep ×
XSleep ×
1024 ×
2.0697
1855
1061
1061
663
Sleep ×
XSleep ×
1024 ×
2.0383
1827
1045
1045
653
0.45
0.24
0.14
0.14
0.47
0.26
0.16
0.15
1/fXTO/10
1/fXTO/14
8 × TClk
4 × TClk
2 × TClk
1 × TClk
µs
µs
µs
µs
µs
µs
Sleep ×
XSleep ×
1024 ×
TClk
896.5
512.5
512.5
320.5
× TClk
ms
Polling mode
Sleep time
Sleep and XSleep
are defined in the
OPMODE register
TSleep
Startup time
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TStartup
Time for
Bitcheck
Average bitcheck
time while polling
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TBitcheck
Bitcheck time for a
valid input signal
fSig
NBitcheck = 0
NBitcheck = 3
NBitcheck = 6
NBitcheck = 9
TBitcheck
0
3/fSig
6/fSig
9/fSig
0.166
3.5/fSig
6.5/fSig
9.5/fSig
0
3/fSig
6/fSig
9/fSig
µs
µs
µs
µs
µs
ms
ms
ms
ms
8 × TClk
3.5/fSig
6.5/fSig
9.5/fSig
0.164
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
Receiving mode
Intermediate
frequency
Baud rate
range
fIF
MODE=0 (USA)
MODE=1 (Europe)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
1.0
BR_Range
1.0
1.8
3.2
5.6
1.8
3.2
5.6
10.0
1.0
1.8
3.2
5.6
1.8
3.2
5.6
10.0
18 (25)
fXTO × 64 / 314
fXTO × 64 / 432.92
MHz
MHz
BR_Range0 × 2 µs / TClk
BR_Range1 × 2 µs / TClk
BR_Range2 × 2 µs / TClk
BR_Range3 × 2 µs / TClk
kBaud
kBaud
kBaud
kBaud
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Electrical Characteristics (continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz,
unless otherwise specified. (VS = 5 V, Tamb = 25°C)
Parameter
Test Condition
Symbol
6.76438 MHz Osc.
(MODE: 1)
Min.
Typ.
Max.
4.90625 MHz Osc.
(MODE: 0)
Min.
Typ.
Max.
149
182
75
91
37.3
45.5
18.6
22.8
2169
1085
542
271
147
179
73
90
36.7
44.8
18.3
22.4
2136
1068
534
267
Variable Oscillator
Min.
Typ.
Unit
Max.
Receiving mode (continued)
Minimum
time period
between edges
at Pin DATA
(figure 17)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Maximum
BR_Range0
low period at
BR_Range1
DATA
BR_Range2
(figure 18)
BR_Range3
OFF command at Pin
ENABLE
(figure 20)
Configuration of the receiver
Frequency of
the reset
marker
(figure 21)
Programming
start pulse
(figure 19,
figure 22)
TDATA_min
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
TDATA_L_
max
tDoze
3.1
fRM
9 × TXClk
11 × TXCl
9 × TXClk
11 × TXClk
9 × TXClk
11 × TXClk
9 × TXClk
11 × TXClk
131 × TXClk
131 × TXClk
131 × TXClk
131 × TXClk
1.5 × TClk
3.05
117.9
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
119.8
Hz
1
4096
BR_Range0
BR_Range1
BR_Range2
BR_Range3
after POR
t1
Programming
delay period
(figure 19,
figure 22)
Synchroni–
zation pulse
(figure 19,
figure 22)
Delay until of
the program
window starts
(figure 19,
figure 22)
Programming
window
(figure 19,
figure 22)
Time frame
of a bit
(figure 22)
t2
Programming
pulse
(figure 19,
figure 22)
Equivalent
acknowledge
pulse: E_Ack
(figure 22)
Equivalent
time window
(figure 22)
t7
OFF-bit
programming
window
(figure 19)
2188
1104
561
290
11656
795
3176
3176
3176
3176
798
2155
1087
553
286
11479
783
3128
3128
3128
3128
786
T Clk
1057 × TClk
533 × TClk
271 × TClk
140 × TClk
5632 × TClk
384.5 ×
TClk
1535 × TClk
1535 × TClk
1535 × TClk
1535 × TClk
µs
385.5 ×
TClk
µs
t3
265
261
128 × TClk
µs
t4
131
129
63.5 × TClk
µs
t5
530
522
256 × TClk
µs
t6
1060
1044
512 × TClk
µs
133
529
131
521
64 × TClk
256 × TClk
µs
t8
265
261
128 × TClk
µs
t9
534
526
258 × TClk
µs
t10
930
916
449.5 ×
TClk
µs
Rev. A1, 15-Oct-98
19 (25)
Preliminary Information
U3741BM
Electrical Characteristics (continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz,
unless otherwise specified. (VS = 5 V, Tamb = 25°C)
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Parameters
Test Conditions / Pins
Symbol
Typ.
Max.
Unit
Sleep mode
(XTO and polling logic active)
IC active
(startup-, bitcheck-, receiving
mode) Pin DATA = H
ISoff
190
276
µA
ISon
7.0
8.6
mA
LNA/ mixer/ IF amplifier
input matched according to
figure 6
LO spurious emission
Input matched according to
@ RFIn
figure 6, required according to
I–ETS 300220
Noise figure LNA and mixer Input matching according to
(DSB)
figure 6
LNA_IN input impedance
@ 433.92 MHz
@ 315 MHz
1 dB compression point
Input matched according to
(LNA, mixer, IF amplifier)
figure 6, referred to RFin
Maximum input level
Input matched according to
figure 6, BER ≤ 10–3,
FSK mode
ASK mode
IIP3
–28
ISLORF
–73
NF
7
dB
ZiLNA_IN
1.0 || 1.56
1.3 || 1.0
–40
kΩ || pF
kΩ || pF
dBm
Current consumption
Min.
LNA mixer
Third-order intercept point
IP1db
dBm
–57
dBm
Pin_max
–28
–20
dBm
dBm
449
MHz
–90
–110
–47
dBC/Hz
dBC/Hz
dBC
MHz/V
kHz
10
nF
6.764375
+30 ppm
4.90625
+30 ppm
150
220
4
MHz
MHz
Local oscillator
Operating frequency range
VCO
Phase noise VCO / LO
Spurious of the VCO
VCO gain
Loop bandwidth of the PLL
Capacitive load at Pin LF
XTO operating frequency
fVCO
fosc = 432.92 MHz
@ 1 MHz
@ 10 MHz
@ ± fXTO
For best LO noise
(design parameter)
R1 = 820
C9 = 4.7 nF
C10 = 1 nF
The capccitive load at Pin LF is
limited if bitcheck is used. The
limitation therefore also applies
to self polling.
XTO crystal frequency,
appropriate load capacitance
must be connected to XTAL
6.764375 MHz
L (fm)
fXTO = 6.764 MHz
4.906 MHz
–93
–113
–55
190
100
KVCO
BLoop
CLF_tot
fXTO
6.764375
–30 ppm
4.90625
–30 ppm
4.90625 MHz
Series resonance resistor of
the crystal
Static capacitance of the
crystal
299
RS
C0
20 (25)
6.764375
4.90625
pF
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Electrical Characteristics (continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz,
unless otherwise specified. (VS = 5 V, Tamb = 25°C)
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D
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Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
–109
–107
–106
–104
–111
–109
–108
–106
–113
–111
–110
–108
dBm
dBm
dBm
dBm
–108
–106.5
–106
–104
–110
–108.5
–108
–106
–112
–110.5
–110
–108
dBm
dBm
dBm
dBm
+2.5
–1.5
dB
+5.5
+7.5
–1.5
–1.5
dB
dB
+5.5
+7.5
–1.5
–1.5
dB
dB
Analog signal processing
Input sensitivity ASK
300-kHz IF filter
Input matched according to
figure 6
ASK (level of carrier)
BER ≤ 10–3, B = 300 kHz
fin = 433.92 MHz/ 315 MHz
T = 25°C, VS = 5 V
fIF = 1 MHz
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Input sensitivity ASK
Input matched according to
600 kHz IF filter
figure 6
ASK (level of carrier)
BER ≤ 10–3, B = 600 kHz
fin = 433.92 MHz/ 315 MHz
T = 25°C, VS = 5 V
fIF = 1 MHz
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Sensitivity variation ASK for 300-kHz and 600-kHz version
the full operating range
fin = 433.92 MHz/ 315 MHz
fIF = 1 MHz
compared to Tamb = 25°C,
PASK = PRef_ASK + PRef
VS = 5 V
Sensitivity variation ASK for
full operating range including
IF filter compared to
Tamb = 25°C, VS = 5 V
Input sensitivity FSK
600 kHz IF filter
300-kHz version
fin = 433.92 MHz/ 315 MHz
fIF = 0.88 MHz to 1.12 MHz
fIF = 0.85 MHz to 1.15 MHz
PASK = PRef_ASK + PRef
600-kHz version
fin = 433.92 MHz/ 315 MHz
fIF = 0.79 MHz to 1.21 MHz
fIF = 0.73 MHz to 1.27 MHz
PASK = PRef_ASK + PRef
Input matched according to
figure 6,
BER ≤ 10–3, B = 600 kHz
fin = 433.92 MHz/ 315 MHz
T = 25°C, VS = 5 V
fIF = 1 MHz
BR_Range0
df ≥ ± 20 kHz
df ≥ ± 30 kHz
BR_Range1
df ≥ ± 20 kHz
df ≥ ± 30 kHz
PRef_ASK
PRef_ASK
PRef
PRef
PRef
PRef_FSK
–95.5
–96.5
–97.5
–98.5
–99.5
100.5
dBm
dBm
–94.5
–95.5
–96.5
–97.5
–98.5
–99.5
dBm
dBm
Rev. A1, 15-Oct-98
21 (25)
Preliminary Information
U3741BM
Electrical Characteristics (continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz,
unless otherwise specified. (VS = 5 V, Tamb = 25°C)
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Parameters
Test Conditions / Pins
Symbol
Sensitivity variation FSK for
the full operating range
compared to Tamb = 25°C,
VS = 5 V
300-kHz and 600-kHz version
fin = 433.92 MHz/ 315 MHz
fIF = 1 MHz
PFSK = PRef_FSK + PRef
PRef
Sensitivity variation FSK for
full operating range including
IF filter compared to
Tamb = 25°C, VS = 5 V
600-kHz version
fin = 433.92 MHz/ 315 MHz
fIF = 0.86 MHz to 1.14 MHz
fIF = 0.82 MHz to 1.18 MHz
PFSK = PRef_FSK + PRef
The sensitivity of the receiver is
higher for higher values of DfFSK
BR_Range0
BR_Range1
BR_Range2 and BR_Range3
are not suitable for FSK
operation
ASK mode
FSK mode
PRef
FSK frequency deviation
S/N ratio to suppress inband
noise signals
Dynamic range RSSI ampl.
Lower cut-off frequency of
the data filter
Recommended CDEM for
best performance
Maximum edge-to-edge time
period of the input data signal
for full sensitivity
Upper cut-off frequency data
filter
Minimum edge-to-edge time
period of the input data signal
for full sensitivity
f cu_DF
2
p
1
30kW
Min.
Typ.
Max.
Unit
+2.5
–1.5
dB
+5.5
+7.5
–1.5
–1.5
dB
dB
50
50
kHz
kHz
12
3
dB
dB
dB
kHz
fFSK
20
20
SNRASK
SNRFSK
DRRSSI
fcu_DF
30
30
10
2
0.11
60
0.16
0.20
CDEM
CDEM = 33 nF
ASK mode
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3
FSK mode
BR_Range0 (Default)
BR_Range1
BR_Range2 and BR_Range3
are not suitable for FSK
operation
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3
Upper cut-off frequency
programmable in 4 ranges
via a serial mode word
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3
CDEM
39
22
12
8.2
nF
nF
nF
nF
27
15
nF
nF
CDEM
tee_sig
1000
560
320
180
s
s
s
s
3.7
6.5
11.4
20.4
270
156
89
50
kHz
kHz
kHz
kHz
s
s
s
s
fu
2.5
4.3
7.6
13.6
tee_sig
22 (25)
3.1
5.4
9.5
17.0
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Electrical Characteristics (continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz,
unless otherwise specified. (VS = 5 V, Tamb = 25°C)
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Parameters
Reduced sensitivity
Test Conditions / Pins
RSense connected from Pin Sens to
VS, input matched according to
figure 6
RSense = 56 k , fin = 433.92 MHz,
(VS = 5 V, Tamb = 25°C)
@ B = 300 kHz
@ B = 600 kHz
RSense = 100 k , fin = 433.92 MHz
@ B = 300 kHz
@ B = 600 kHz
RSense = 56 k , fin = 315 MHz
@ B = 300 kHz
@ B = 600 kHz
RSense = 100 k , fin = 315 MHz
@ B = 300 kHz
@ B = 600 kHz
Reduced sensitivity variation RSense = 56 k
over full operating range
RSense = 100 k
PRed = PRef_Red + PRed
Reduced sensitivity variation Values relative to
for different values of RSense RSense = 56 k
Symbol
PRed
Typ.
Max.
Unit
dBm
(peak
level)
–71
–67
–76
–72
–81
–77
dBm
dBm
–80
–76
–85
–81
–90
–86
dBm
dBm
–72
–68
–77
–73
–82
–78
dBm
dBm
–81
–77
5
6
–86
–82
0
0
–91
–87
0
0
dBm
dBm
dB
dB
PRed
RSense = 56 k
RSense = 68 k
RSense = 82 k
RSense = 100 k
RSense = 120 k
RSense = 150 k
PRed = PRef_Red + PRed
Threshold voltage for reset
Min.
PRef_Red
0
–3.5
–6.0
–9.0
–11.0
–13.5
dB
dB
dB
dB
dB
dB
VThRESET
1.95
2.8
3.75
V
VOI
RPup
39
0.08
50
0.3
61
2.5
41
540
V
k
s
pF
pF
0.08
VS–0.14V
0.3
V
V
0.2 × VS
V
V
0.2 × VS
V
V
0.2 × VS
V
V
0.2 × VS
V
Digital ports
Data output
– Saturation voltage LOW
– Internal pull-up resistor
– Maximum time constant
– Maximum caoacitive load
POUT output
– Saturation voltage LOW
– Saturation voltage HIGH
FSK/ASK input
– Low level input voltage
– High level input voltage
ENABLE input
– Low level input voltage
– High level input voltage
MODE input
– Low level input voltage
– High level input voltage
TEST input
– Low level input voltage
Iol = 1 mA
= CL (Rpup//RExt)
without ext. pull-up resistor
Rext = 5 k
CL
CL
IPOUT = 1 mA
IPOUT = –1 mA
VOl
VOh
VS–0.3V
FSK selected
ASK selected
VIl
VIh
0.8 × VS
Idle mode
Active mode
VIl
VIh
0.8 × VS
Division factor = 10
Division factor = 14
Test input must always be set to
LOW
VIl
VIh
0.8 × VS
VIl
Rev. A1, 15-Oct-98
23 (25)
Preliminary Information
U3741BM
Package Information
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
13038
1
10
24 (25)
Rev. A1, 15-Oct-98
Preliminary Information
U3741BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances ( ODSs).
The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of
ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency ( EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively.
TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
Rev. A1, 15-Oct-98
25 (25)
Preliminary Information