MCP3001
2.7V 10-Bit A/D Converter with SPI™ Serial Interface
Features
10-bit resolution
±1 LSB max DNL
±1 LSB max INL
On-chip sample and hold
SPI™ serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
200 ksps sampling rate at 5V
75 ksps sampling rate at 2.7V
Low power CMOS technology
- 5 nA typical standby current, 2 µA max
- 500 µA max active current at 5V
• Industrial temp range: -40°C to +85°C
• 8-pin PDIP, SOIC, MSOP and TSSOP packages
Package Types
PDIP, MSOP, SOIC, TSSOP
VREF
1
IN+
2
IN–
3
VSS
4
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
Description
The Microchip Technology Inc. MCP3001 is a successive approximation 10-bit A/D converter (ADC) with onboard sample and hold circuitry. The device provides a
single pseudo-differential input. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are both specified at ±1 LSB max. Communication with the device is
done using a simple serial interface compatible with the
SPI protocol. The device is capable of sample rates up
to 200 ksps at a clock rate of 2.8 MHz. The MCP3001
operates over a broad voltage range (2.7V - 5.5V).
Low current design permits operation with a typical
standby current of only 5 nA and a typical active current
of 400 µA. The device is offered in 8-pin PDIP, MSOP,
TSSOP and 150 mil SOIC packages.
8
VDD
7
CLK
6
DOUT
5
CS/SHDN
Illustration not to scale
Functional Block Diagram
VDD
VREF
Applications
•
•
•
•
MCP3001
•
•
•
•
•
•
•
•
•
VSS
DAC
Comparator
IN+
IN-
10-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN
CLK
Shift
Register
DOUT
SPI™ is a trademark of Motorola Inc.
© 2007 Microchip Technology Inc.
DS21293C-page 1
MCP3001
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
PIN FUNCTION TABLE
Name
Function
VDD
+2.7V to 5.5V Power Supply
VSS
Ground
IN+
Positive Analog Input
Ambient temp. with power applied .....-65°C to +125°C
IN-
Negative Analog Input
ESD protection on all pins (HBM)........................> 4kV
CLK
Serial Clock
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or
any other conditions above those indicated in the operational
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device
reliability.
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
VREF
Reference Voltage Input
VDD.........................................................................7.0V
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
Storage temperature ..........................-65°C to +150°C
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 14*fSAMPLE,
unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25°C, unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
tCONV
—
—
10
clock
cycles
Conditions
Conversion Rate:
Conversion Time
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
1.5
—
—
clock
cycles
200
75
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
DC Accuracy:
Resolution
10
bits
Integral Nonlinearity
INL
—
±0.5
±1
LSB
Differential Nonlinearity
DNL
—
±0.25
±1
LSB
Offset Error
—
—
±1.5
LSB
Gain Error
—
—
±1
LSB
THD
—
-76
—
dB
VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion
(SINAD)
SINAD
—
61
—
dB
VIN = 0.1V to 4.9V@1 kHz
Spurious Free Dynamic Range
SFDR
—
80
—
dB
VIN = 0.1V to 4.9V@1 kHz
Voltage Range
VREF
0.25
—
VDD
V
Note 2
Current Drain
IREF
—
90
0.001
150
3
µA
µA
CS = VDD = 5V
No missing codes over temperature
Dynamic Performance:
Total Harmonic Distortion
Reference Input:
Note 1: This parameter is guaranteed by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
DS21293C-page 2
© 2007 Microchip Technology Inc.
MCP3001
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 14*fSAMPLE,
unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25°C, unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
—
85
—
°C/W
—
163
—
°C/W
—
206
—
°C/W
—
°C/W
Conditions
Temperature Ranges:
Thermal Package Resistance:
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-TSSOP
θJA
θJA
θJA
θJA
—
Analog Inputs:
Input Voltage Range (IN+)
IN+
IN-
—
VREF+IN-
V
Input Voltage Range (IN-)
IN-
VSS-100
—
VSS+100
mV
—
0.001
±1
µA
Switch Resistance
RSS
—
1K
—
Ω
See Figure 4-1
Sample Capacitor
CSAMPLE
—
20
—
pF
See Figure 4-1
VIH
0.7 VDD
—
—
V
Leakage Current
Digital Input/Output:
Data Coding Format
High Level Input Voltage
Straight Binary
Low Level Input Voltage
VIL
—
—
0.3 VDD
V
High Level Output Voltage
VOH
4.1
—
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
—
—
0.4
V
IOL = 1 mA, VDD = 4.5V
ILI
-10
—
10
µA
VIN = VSS or VDD
Input Leakage Current
Output Leakage Current
ILO
-10
—
10
µA
VOUT = VSS or VDD
CIN, COUT
—
—
10
pF
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Clock Frequency
fCLK
—
—
2.8
1.05
MHz
MHz
Clock High Time
tHI
160
—
—
ns
Pin Capacitance
(all inputs/outputs)
Timing Parameters:
Clock Low Time
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
tLO
160
—
—
ns
tSUCS
100
—
—
ns
CLK Fall To Output Data Valid
tDO
—
—
125
200
ns
ns
VDD = 5V, See Figure 1-2
VDD = 2.7, See Figure 1-2
CLK Fall To Output Enable
tEN
—
—
125
200
ns
ns
VDD = 5V, See Figure 1-2
VDD = 2.7, See Figure 1-2
CS Rise To Output Disable
tDIS
—
—
100
ns
See test circuits, Figure 1-2
(Note 1)
CS Disable Time
tCSH
350
—
—
ns
DOUT Rise Time
tR
—
—
100
ns
See test circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
—
—
100
ns
See test circuits, Figure 1-2
(Note 1)
CS Fall To First Rising CLK Edge
Note 1: This parameter is guaranteed by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
© 2007 Microchip Technology Inc.
DS21293C-page 3
MCP3001
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 14*fSAMPLE,
unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25°C, unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
Conditions
Operating Voltage
VDD
2.7
—
5.5
V
Operating Current
IDD
—
400
210
500
µA
µA
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
—
0.005
2
µA
CS = VDD = 5.0V
Power Requirements:
Note 1: This parameter is guaranteed by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.
tCSH
CS
tSUCS
tHI
tLO
CLK
tEN
tDO
tR
HI-Z
DOUT
FIGURE 1-1:
Null BIT
MSB OUT
tDIS
tF
LSB
HI-Z
Serial Timing.
DS21293C-page 4
© 2007 Microchip Technology Inc.
MCP3001
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
3 kΩ
Test Point
DOUT
3 kΩ
DOUT
VDD/2
tEN Waveform
30 pF
CL = 30 pF
tDIS Waveform 1
VSS
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
Voltage Waveforms for tEN
CS
tF
tR
tDIS Waveform 2
1
CLK
2
3
4
B9
DOUT
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
CS
CLK
tDO
VIH
DOUT
Waveform 1*
90%
tDIS
DOUT
DOUT
Waveform 2†
10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled
by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
© 2007 Microchip Technology Inc.
DS21293C-page 5
MCP3001
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate, TA = 25°C
0.4
0.4
Positive INL
0.2
INL (LSB)
0.2
INL (LSB)
VDD = VREF = 2.7V
0.3
0.3
0.1
0.0
-0.1
Negative INL
-0.2
0.0
-0.1
-0.3
-0.4
-0.4
25
50
Negative INL
-0.2
-0.3
0
Positive INL
0.1
0
75 100 125 150 175 200 225 250
25
Sample Rate (ksps)
Integral Nonlinearity (INL) vs. Sample
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
100
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
1.0
VDD = VREF = 2.7V
0.8
0.6
Positive INL
Negative INL
fSAMPLE = 75 ksps
0.4
Positive INL
0.2
0.0
-0.2
-0.4
Negative INL
-0.6
-0.8
-1.0
0
1
2
3
4
5
6
0.0
0.5
1.0
VREF (V)
FIGURE 2-2:
1.5
2.0
2.5
3.0
VREF (V)
Integral Nonlinearity (INL) vs. VREF.
FIGURE 2-5:
(VDD = 2.7V).
Integral Nonlinearity (INL) vs. VREF
0.50
0.5
0.4
VDD = V REF = 5V
0.40
V DD = VREF = 2.7V
0.3
fSAMPLE = 200 ksps
0.30
fSAMPLE = 75 ksps
0.20
INL (LSB)
0.2
INL (LSB)
75
Sample Rate (ksps)
INL (LSB)
INL (LSB)
FIGURE 2-1:
Rate.
50
0.1
0.0
-0.1
0.10
0.00
-0.10
-0.2
-0.20
-0.3
-0.30
-0.4
-0.40
-0.5
-0.50
0
128
256
384
512
640
768
896
1024
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
(Representative Part).
DS21293C-page 6
0
128
256
384
512
640
768
896
1024
Digital Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, VDD = 2.7V).
© 2007 Microchip Technology Inc.
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C
0.4
0.4
fSAMPLE = 75 ksps
Positive INL
0.2
0.2
INL (LSB)
INL (LSB)
VDD = VREF = 2.7V
0.3
0.3
0.1
0.0
-0.1
Negative INL
0.0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
Positive INL
0.1
Negative INL
-0.4
-50
-25
0
25
50
75
100
-50
-25
0
Integral
Nonlinearity
(INL)
vs.
0.4
0.3
0.3
DNL (LSB)
DNL (LSB)
Positive DNL
0.0
-0.1
Negative DNL
(INL)
vs.
Positive DNL
0.1
0.0
-0.1
Negative DNL
-0.2
-0.3
-0.3
-0.4
-0.4
0
25
50
75
100
125
150
175 200
225
250
0
25
Sample Rate (ksps)
FIGURE 2-8: Differential
Sample Rate.
Nonlinearity
50
(DNL)
vs.
FIGURE 2-11: Differential
Sample Rate (VDD = 2.7V).
1.0
1.0
0.8
0.6
0.8
Nonlinearity
Positive DNL
0.0
-0.2
-0.4
100
Negative DNL
-0.6
-0.8
(DNL)
vs.
VDD = VREF = 2.7V
fSAMPLE = 75 ksps
0.6
0.4
0.2
75
Sample Rate (ksps)
DNL (LSB)
DNL (LSB)
100
VDD = VREF = 2.7V
0.2
0.2
-0.2
75
FIGURE 2-10: Integral
Nonlinearity
Temperature (VDD = 2.7V).
0.4
0.1
50
Temperature (°C)
Temperature (°C)
FIGURE 2-7:
Temperature.
25
0.4
Positive DNL
0.2
0.0
-0.2
Negative DNL
-0.4
-0.6
-0.8
-1.0
-1.0
0
1
2
3
4
5
0.0
Differential
Nonlinearity
© 2007 Microchip Technology Inc.
1.0
1.5
2.0
2.5
3.0
VREF(V)
VREF (V)
FIGURE 2-9:
VREF.
0.5
(DNL)
vs.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF
(VDD = 2.7V).
DS21293C-page 7
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C
0.5
0.5
0.4
0.4
fSAMPLE = 200 ksps
0.3
0.2
DNL (LSB)
DNL (LSB)
0.3
VDD = VREF = 5V
0.1
0.0
-0.1
-0.2
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
VDD = VREF = 2.7V
fSAMPLE = 75 ksps
-0.5
0
128
256
384
512
640
768
896
1024
0
128
256
384
Digital Code
512
640
768
896
1024
Digital Code
FIGURE 2-13: Differential Nonlinearity
Code (Representative Part).
(DNL)
vs.
FIGURE 2-16: Differential Nonlinearity
Code (Representative Part, VDD = 2.7V).
0.3
0.3
0.2
0.2
(DNL)
vs.
VDD = VREF = 2.7V
fSAMPLE = 75 ksps
Positive DNL
DNL (LSB)
DNL (LSB)
Positive DNL
0.1
0.0
-0.1
0.1
0.0
-0.1
Negative DNL
Negative DNL
-0.2
-0.2
-0.3
-0.3
-50
-25
0
25
50
75
100
-50
-25
Nonlinearity
(DNL)
vs.
FIGURE 2-17: Differential
Temperature (VDD = 2.7V).
1.0
50
75
100
Nonlinearity
(DNL)
vs.
8
0.8
VDD = 2.7V
0.6
7
fSAMPLE = 75 ksps
Offset Error (LSB)
Gain Error (LSB)
25
Temperature (°C)
Temperature (°C)
FIGURE 2-14: Differential
Temperature.
0
0.4
0.2
0.0
-0.2
-0.4
VDD = 5V
-0.6
fSAMPLE = 200 ksps
-0.8
V DD = 5V
6
fSAMPLE = 200 ksps
5
4
V DD = 2.7V
3
fSAMPLE = 75 ksps
2
1
0
-1.0
0
1
2
3
VREF(V)
FIGURE 2-15: Gain Error vs. VREF.
DS21293C-page 8
4
5
0.0
1.0
2.0
3.0
4.0
5.0
VREF (V)
FIGURE 2-18: Offset Error vs. VREF.
© 2007 Microchip Technology Inc.
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C
1.0
0.0
VDD = V REF = 2.7V
0.9
V DD = V REF = 5V
fSAMPLE = 75 ksps
0.8
fSAMPLE = 200 ksps
Offset Error (LSB)
Gain Error (LSB)
0.1
-0.1
-0.2
-0.3
V DD = V REF = 5V
0.7
0.6
0.5
V DD = VREF = 2.7V
0.4
fSAMPLE = 75 ksps
0.3
0.2
0.1
fSAMPLE = 200 ksps
0.0
-0.4
-50
-25
0
25
50
75
-50
100
-25
0
FIGURE 2-19: Gain Error vs. Temperature.
60
SNR (dB)
50
fSAMPLE = 75 ksps
V DD = V REF = 5V
fSAMPLE = 200 ksps
20
SINAD (dB)
70
60
VDD = V REF = 2.7V
10
100
50
V DD = VREF = 2.7V
40
fSAMPLE = 75 ksps
30
VDD = V REF = 5V
fSAMPLE = 200 ksps
20
10
0
0
1
10
100
1
10
Input Frequency (kHz)
0
-10
-20
-30
-40
100
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input
Frequency.
FIGURE 2-23: Signal to Noise Ratio and Distortion
(SINAD) vs. Input Frequency.
80
70
V DD = VREF = 2.7V
V DD = VREF = 5V
fSAMPLE = 75 ksps
fSAMPLE = 200 ksps
-50
-60
-70
-80
-90
-100
SINAD (dB)
THD (dB)
75
FIGURE 2-22: Offset Error vs. Temperature.
70
30
50
Temperature (°C)
Temperature (°C)
40
25
60
VDD = VREF = 5V
50
fSAMPLE = 200 ksps
40
30
20
VDD = VREF = 2.7V
10
fSAMPLE = 75 ksps
0
1
10
100
Input Frequency (kHz)
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
Input Frequency.
© 2007 Microchip Technology Inc.
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
FIGURE 2-24: Signal to Noise
(SINAD) vs. Input Signal Level.
and
Distortion
DS21293C-page 9
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C
10.0
9.9
ENOB (rms)
ENOB (rms)
9.8
9.7
V DD = VREF = 5V
9.6
VDD = V REF = 2.7V
9.5
fSAMPLE = 200 ksps
fSAMPLE = 75 ksps
9.4
9.3
9.2
9.1
9.0
0.0
1.0
2.0
3.0
4.0
10.0
9.8
9.6
9.4
9.2
VDD = VREF = 5V
fSAMPLE = 200 ksps
9.0
8.8
8.6
8.4
8.2
8.0
VDD = VREF = 2.7V
fSAMPLE = 75 ksps
1
5.0
10
Input Frequency (kHz)
VREF (V)
V DD = V REF = 5V
fSAMPLE = 200 ksps
50
40
30
20
10
0
V DD = V REF = 2.7V
fSAMPLE = 75 ksps
1
10
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
Input Frequency.
Power Supply Rejection (dB)
SFDR (dB)
FIGURE 2-25: Effective Number of Bits (ENOB) vs.
VREF.
100
90
80
70
60
0
-10
VDD = VREF = 5V
-20
fSAMPLE = 200 ksps
-30
-40
-50
-60
-70
-80
1
10
Dynamic
Range
fSAMPLE = 200 ksps
fINPUT = 10.0097 kHz
4096 points
40000
60000
80000
100000
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10 kHz Input
(Representative Part).
DS21293C-page 10
10000
FIGURE 2-29: Power Supply Rejection (PSR) vs.
Ripple Frequency.
VDD = VREF = 5V
20000
1000
Ripple Frequency (kHz)
Amplitude (dB)
Amplitude (dB)
FIGURE 2-26: Spurious Free
(SFDR) vs. Input Frequency.
0
100
100
Input Frequency (kHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
VDD = VREF = 2.7V
fSAMPLE = 75 ksps
fINPUT = 1.00708 kHz
4096 points
0
5000
10000 15000 20000 25000 30000 35000
Frequency (Hz)
FIGURE 2-30: Frequency Spectrum of 1 kHz Input
(Representative Part, VDD = 2.7V).
© 2007 Microchip Technology Inc.
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C
500
450
400
IREF (µA)
IDD (µA)
350
300
250
200
150
VREF = V DD
100
All points at fCLK = 2.8 MHz except
50
at VREF = VDD = 2.5V, fCLK =1.05 MHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
120
110
100
90
80
70
60
50
40
30
20
10
0
VREF = VDD
All points at fCLK = 2.8 MHz except
at VREF = VDD = 2.5V, fCLK = 1.05 MHz
2.0
6.0
2.5
3.0
3.5
VDD (V)
FIGURE 2-31: IDD vs. VDD.
450
400
IREF (µA)
IDD (µA)
350
VDD = VREF = 5V
250
200
150
VDD = VREF = 2.7V
100
50
0
10
100
1000
120
110
100
90
80
70
60
50
40
30
20
10
0
10000
10
100
IREF (µA)
IDD (µA)
10000
VDD = V REF = 5V
100
90
80
fCLK = 2.8 MHz
fCLK = 2.8 MHz
70
60
50
40
30
20
V DD = VREF = 2.7V
fCLK = 1.05 MHz
0
1000
FIGURE 2-35: IREF vs. Clock Frequency.
VDD = V REF = 5V
-25
6.0
VDD = VREF = 2.7V
120
110
-50
5.5
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency.
300
250
200
150
100
50
0
5.0
V DD = VREF = 5V
Clock Frequency (kHz)
600
550
500
450
400
350
4.5
FIGURE 2-34: IREF vs. VDD.
500
300
4.0
VDD (V)
V DD = V REF = 2.7V
fCLK = 1.05 MHz
10
0
25
50
Temperature (°C)
FIGURE 2-33: IDD vs. Temperature.
© 2007 Microchip Technology Inc.
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-36: IREF vs. Temperature.
DS21293C-page 11
MCP3001
Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C
60
2.0
Analog Input Leakage (nA)
VREF = CS = VDD
50
IDDS (pA)
40
30
20
10
0
1.8
V DD = V REF = 5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-25
0
25
50
75
100
6.0
Temperature (°C)
V DD (V)
FIGURE 2-39: Analog Input Leakage Current vs.
Temperature.
FIGURE 2-37: IDDS vs. VDD.
100.00
VDD = VREF = CS = 5V
IDDS (nA)
10.00
1.00
0.10
0.01
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-38: IDDS vs. Temperature.
DS21293C-page 12
© 2007 Microchip Technology Inc.
MCP3001
3.0
PIN DESCRIPTIONS
3.1
IN+
Positive analog input. This input can vary from IN- to
VREF + IN-.
3.2
IN-
Negative analog input. This input can vary ±100 mV
from VSS.
3.3
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.4
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.5
DOUT (Serial Data output)
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch, (RSS) impedance, directly affecting the time that is required to
charge the capacitor, CSAMPLE. Consequently, a larger
source impedance increases the offset, gain, and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational amplifier such as the MCP601, which has a closed loop output impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above Vss,
then the 3FFh code will not be seen unless the IN+
input level goes above VREF level.
4.2
Reference Input
The reference input (VREF) determines the analog input
voltage range and the LSB size, as shown below.
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
4.0
DEVICE OPERATION
The MCP3001 A/D converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens
and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit
digital output code. Conversion rates of 200 ksps are
possible on the MCP3001. See Section 6.2 for information on minimum clock rates. Communication with the
device is done using a 3-wire SPI-compatible interface.
4.1
V REF
LSB Size = ------------1024
As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is a function of the analog input signal and the reference input as shown
below.
1024*VIN
Digital Output Code = -----------------------V REF
Analog Inputs
The MCP3001 provides a single pseudo-differential
input. The IN+ input can range from IN- to (VREF +IN-).
The IN- input is limited to ±100 mV from the VSS rail.
The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and
IN- inputs.
For the A/D Converter to meet specification, the charge
holding capacitor, CSAMPLE must be given enough time
to acquire a 10-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
© 2007 Microchip Technology Inc.
where:
VIN = analog input voltage = V(IN+) - V(IN-)
VREF = reference voltage
When using an external voltage reference device, the
system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a
direct effect on the operation of the ADC.
DS21293C-page 13
MCP3001
VDD
RSS
Sampling
Switch
VT = 0.6V
CHx
CPIN
7 pF
VA
VT = 0.6V
SS
ILEAKAGE
±1 nA
RS = 1 kΩ
CSAMPLE
= DAC capacitance
= 20 pF
VSS
Legend
VA
RSS
CHx
CPIN
VT
ILEAKAGE
SS
RS
CSAMPLE
FIGURE 4-1:
=
=
=
=
=
=
signal source
source impedance
input channel pad
input pin capacitance
threshold voltage
leakage current at the pin
due to various junctions
sampling switch
sampling switch resistor
sample/hold capacitance
=
=
=
Analog Input Model.
Clock Frequency (MHz)
4.0
3.5
V DD = VREF = 5V
3.0
fSAMPLE = 200 ksps
2.5
2.0
1.5
V DD = V REF = 2.7V
fSAMPLE = 75 ksps
1.0
0.5
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input
Resistance (RS) to maintain less than a 0.1LSB
deviation in INL from nominal conditions.
DS21293C-page 14
© 2007 Microchip Technology Inc.
MCP3001
5.0
SERIAL COMMUNICATIONS
Communication with the device is done using a standard SPI compatible serial interface. Initiating communication with the MCP3001 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate communication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 10 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 10 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
If it is desired, the CS can be raised to end the conversion period at any time during the transmission. Faster
conversion rates can be obtained by using this technique if not all the bits are captured before starting a
new cycle. Some system designers use this method by
capturing only the highest order 8 bits and ‘throwing
away’ the lower 2 bits.
tCYC
tCSH
CS
Power
Down
tSUCS
CLK
DOUT
tDATA**
tCONV
tSAMPLE
NULL
HI-Z
BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
NULL
BIT B9 B8
B7 B6
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data,
followed by zeros indefinitely. See Figure below.
** tDATA: during this time, the bias current and the comparator powers down and the reference input becomes a
high impedance node.
FIGURE 5-1:
Communication with MCP3001 (MSB first Format).
tCYC
tCSH
CS
tSUCS
Power Down
CLK
tSAMPLE
DOUT
HI-Z
tCONV
tDATA**
NULL
BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator powers down and the reference input becomes a
high impedance node leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2:
Communication with MCP3001 (LSB first Format).
© 2007 Microchip Technology Inc.
DS21293C-page 15
MCP3001
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3001 with
Microcontroller SPI Ports
ler’s receive buffer will contain two unknown bits (the
output is at high impedance for the first two clocks), the
null bit and the highest order five bits of the conversion.
After the second eight clocks have been sent to the
device, the MCU receive register will contain the lowest
order five bits and the B1-B4 bits repeated as the ADC
has begun to shift out LSB first data with the extra
clocks. Typical procedure would then call for the lower
order byte of data to be shifted right by three bits to
remove the extra B1-B4 bits. The B9-B5 bits are then
rotated 3 bits to the right with B7-B5 rotating from the
high order byte to the lower order byte. Easier manipulation of the converted data can be obtained by using
this method.
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3001. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3001 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3001 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3001. Figure 6-1 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the ADC on the falling edge of the third clock pulse. After the first eight
clocks have been sent to the device, the microcontrol-
Figure 6-2 shows SPI Mode 1,1 communication which
requires that the clock idles in the high state. As with
mode 0,0, the ADC outputs data on the falling edge of
the clock and the MCU latches data from the ADC in on
the rising edge of the clock.
CS
MCU latches data from ADC
on rising edges of SCLK
1
CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out of
ADC on falling edges
DOUT
HI-Z
NULL B9
BIT
B8
B7
B6
B4
B5
B3
B2
B1
B0
B1
B2
B3 B4
HI-Z
LSB first data begins
to come out
?
?
0
B9
B8
B7
B6
B5
B4
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-1:
B3
B2
B1
B0
B1
B2
B3
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication with the MCP3001 using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from ADC
on rising edges of SCLK
1
CLK
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
Data is clocked out of
ADC on falling edges
DOUT
HI-Z
NULL B9
BIT
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
HI-Z
LSB first data begins
to come out
?
?
0
B9
B8
B7
B6
B5
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-2:
B4
B3
B2
B1
B0
B1
B2
B3
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication with the MCP3001 using 8-bit segments (Mode 1,1: SCLK idles high).
DS21293C-page 16
© 2007 Microchip Technology Inc.
MCP3001
6.2
Maintaining Minimum Clock Speed
When the MCP3001 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst case condition), the part will maintain
proper charge on the sample cap for 700 µs at
VDD = 2.7V and 1.5 ms at VDD = 5V. This means that at
VDD = 2.7V, the time it takes to transmit the first 14
clocks must not exceed 700 µs. Failure to meet this criterion may induce linearity errors into the conversion
outside the rated specifications.
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the ADC is not a low impedance
source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals
that may be aliased back into the conversion results.
This is illustrated in Figure 6-3 where an op amp is
used to drive, filter and gain the analog input of the
MCP3001. This amplifier provides a low impedance
source for the converter input and a low pass filter,
which eliminates unwanted high frequency noise.
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
6.4
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using ADC, refer to AN-688 “Layout Tips for
12-Bit A/D Converter Applications”.
VDD
Connection
Device 4
Device 1
VDD
4.096V
Reference
0.1 µF
Device 3
10 µF
Device 2
10 µF
MCP1541
CL
1 µF
VREF
IN+
FIGURE 6-4: VDD traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
MCP3001
VIN
R1
C1
MCP601
IN-
+
R2
-
C2
R3
R4
FIGURE 6-3: The MCP601 operational amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3001.
© 2007 Microchip Technology Inc.
DS21293C-page 17
MCP3001
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Example:
MCP3001
I/PNNN e3
0736
8-Lead SOIC (150 mil)
Example:
MCP3001
ISN e3 0736
XXXXXXXX
XXXXYYWW
NNN
NNN
Example:
8-Lead MSOP
3001I e3
XXXXXX
YWWNNN
725NNN
Example:
8-Lead TSSOP
XXXX
3001 e3
YYWW
0716
NNN
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS21293C-page 18
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
MCP3001
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
8
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.348
.365
.400
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
© 2007 Microchip Technology Inc.
DS21293C-page 19
MCP3001
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
β
MILLMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
Overall Width
E
Molded Package Width
E1
3.90 BSC
Overall Length
D
4.90 BSC
1.75
6.00 BSC
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
1.04 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
DS21293C-page 20
© 2007 Microchip Technology Inc.
MCP3001
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.75
0.85
0.95
Standoff
A1
0.00
–
0.15
Overall Width
E
Molded Package Width
E1
3.00 BSC
Overall Length
D
3.00 BSC
Foot Length
L
Footprint
L1
1.10
4.90 BSC
0.40
0.60
0.80
0.95 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.08
–
0.23
Lead Width
b
0.22
–
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B
© 2007 Microchip Technology Inc.
DS21293C-page 21
MCP3001
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
2.90
3.00
3.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
DS21293C-page 22
© 2007 Microchip Technology Inc.
MCP3001
APPENDIX A:
REVISION HISTORY
Revision C (January 2007)
This revision includes updates to the packaging
diagrams.
© 2007 Microchip Technology Inc.
DS21293C-page 23
NOTES:
DS21293C-page 24
© 2007 Microchip Technology Inc.
MCP3001
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
X
/XX
Temperature
Range
Package
MCP3001: 10-Bit Serial A/D Converter
MCP3001T: 10-Bit Serial A/D Converter
(Tape and Reel) (SOIC and TSSOP only)
Temperature Range:
I
= -40°C to +85°C
Package:
P
SN
MS
ST
=
=
=
=
Examples:
a)
MCP3001-I/P: Industrial Temperature,
PDIP package.
b)
MCP3001-I/SN: Industrial Temperature,
SOIC package.
c)
MCP3001-I/ST: Industrial Temperature,
TSSOP package.
d)
MCP3001-I/MS: Industrial Temperature,
MSOP package.
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic Micro Small Outline (MSOP), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
© 2007 Microchip Technology Inc.
DS21293C-page25
MCP3001
NOTES:
DS21293C-page26
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS21293C-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS21293C-page 28
© 2007 Microchip Technology Inc.