MCP3201
2.7V 12-Bit A/D Converter with SPI™ Serial Interface
Features
12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3201-B)
±2 LSB max INL (MCP3201-C)
On-chip sample and hold
SPI™ serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at VDD = 5V
50ksps max. sampling rate at VDD = 2.7V
Low power CMOS technology
500 nA typical standby current, 2 µA max.
400 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP, PDIP, SOIC and TSSOP packages
Package Types
MSOP, PDIP, SOIC, TSSOP
VREF
1
IN+
2
IN–
3
VSS
4
MCP3201
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8
VDD
7
CLK
6
DOUT
5
CS/SHDN
Functional Block Diagram
VDD
VREF
VSS
Applications
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
Description
The Microchip Technology Inc. MCP3201 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The
device provides a single pseudo-differential input. Differential Nonlinearity (DNL) is specified at ±1 LSB, and
Integral Nonlinearity (INL) is offered in ±1 LSB
(MCP3201-B) and ±2 LSB (MCP3201-C) versions.
Communication with the device is done using a simple
serial interface compatible with the SPI protocol. The
device is capable of sample rates of up to 100 ksps at
a clock rate of 1.6 MHz. The MCP3201 operates over
a broad voltage range (2.7V - 5.5V). Low current
design permits operation with typical standby and
active currents of only 500 nA and 300 µA, respectively. The device is offered in 8-pin MSOP, PDIP,
TSSOP and 150 mil SOIC packages.
© 2007 Microchip Technology Inc.
DAC
Comparator
IN+
IN-
12-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN
CLK
Shift
Register
DOUT
DS21290D-page 1
MCP3201
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
PIN FUNCTION TABLE
Name
Function
VDD
+2.7V to 5.5V Power Supply
VDD.........................................................................7.0V
VSS
Ground
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
IN+
Positive Analog Input
IN-
Negative Analog Input
CLK
Serial Clock
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
VREF
Reference Voltage Input
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
ESD protection on all pins (HBM)....................... > 4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE
unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
tCONV
—
—
12
clock
cycles
Conditions
Conversion Rate:
Conversion Time
1.5
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
—
—
Integral Nonlinearity
INL
—
—
Differential Nonlinearity
DNL
clock
cycles
100
50
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
±0.75
±1
±1
±2
LSB
LSB
MCP3201-B
MCP3201-C
—
±0.5
±1
LSB
No missing codes over
temperature
Offset Error
—
±1.25
±3
LSB
Gain Error
—
±1.25
±5
LSB
DC Accuracy:
Resolution
12
bits
Dynamic Performance:
Total Harmonic Distortion
Signal to
(SINAD)
Noise
and
Distortion
Spurious Free Dynamic Range
THD
—
-82
—
dB
VIN = 0.1V to 4.9V@1 kHz
SINAD
—
72
—
dB
VIN = 0.1V to 4.9V@1 kHz
SFDR
—
86
—
dB
VIN = 0.1V to 4.9V@1 kHz
Reference Input:
Voltage Range
0.25
—
VDD
V
Note 2
Current Drain
—
—
100
.001
150
3
µA
µA
CS = VDD = 5V
—
VREF+IN-
V
Analog Inputs:
Input Voltage Range (IN+)
IN+
IN-
Input Voltage Range (IN-)
IN-
VSS-100
Leakage Current
Switch Resistance
Note 1:
2:
3:
RSS
VSS+100
mV
—
0.001
±1
µA
—
1K
—
W
See Figure 4-1
This parameter is established by characterization and not 100% tested.
See graph that relates linearity performance to VREF level.
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 for more information.
DS21290D-page 2
© 2007 Microchip Technology Inc.
MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE
unless otherwise noted.
Parameter
Sample Capacitor
Sym
Min
Typ
Max
Units
CSAMPLE
—
20
—
pF
VIH
0.7 VDD
—
—
V
Conditions
See Figure 4-1
Digital Input/Output:
Data Coding Format
High Level Input Voltage
Straight Binary
Low Level Input Voltage
VIL
—
—
0.3 VDD
V
High Level Output Voltage
VOH
4.1
—
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
—
—
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
µA
VOUT = VSS or VDD
CIN, COUT
—
—
10
pF
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
fCLK
—
—
—
—
1.6
0.8
MHz
MHz
Clock High Time
tHI
312
—
—
ns
Clock Low Time
tLO
312
—
—
ns
tSUCS
100
—
—
ns
Pin Capacitance
(all inputs/outputs)
Timing Parameters:
Clock Frequency
CS Fall To First Rising CLK Edge
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
CLK Fall To Output Data Valid
tDO
—
—
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
—
—
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
CS Disable Time
tCSH
625
—
—
ns
DOUT Rise Time
tR
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
VDD
2.7
—
5.5
V
IDD
—
—
300
210
400
—
µA
µA
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
IDDS
—
0.5
2
µA
CS = VDD = 5.0V
Power Requirements:
Operating Voltage
Operating Current
Standby Current
Temperature Ranges:
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Package Resistance:
Thermal Resistance, 8L-PDIP
qJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
qJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
qJA
—
206
—
°C/W
Thermal Resistance, 8L-TSSOP
qJA
—
124
—
°C/W
Note 1:
2:
3:
This parameter is established by characterization and not 100% tested.
See graph that relates linearity performance to VREF level.
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 for more information.
© 2007 Microchip Technology Inc.
DS21290D-page 3
MCP3201
tCSH
CS
tSUCS
tHI
tLO
CLK
tEN
HI-Z
DOUT
FIGURE 1-1:
tDO
NULL BIT
tDIS
tR
tF
HI-Z
LSB
MSB OUT
Serial Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
3 kΩ
Test Point
DOUT
3 kΩ
tDIS Waveform 2
VDD/2
tEN Waveform
DOUT
30 pF
CL = 30 pF
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
Voltage Waveforms for tEN
CS
tF
tR
tDIS Waveform 1
VSS
1
CLK
2
3
4
B9
DOUT
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
CS
CLK
tDO
VIH
DOUT
Waveform 1*
90%
tDIS
DOUT
DOUT
Waveform 2†
10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled
by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
DS21290D-page 4
© 2007 Microchip Technology Inc.
MCP3201
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
1.0
2.0
Positive INL
0.8
1.0
INL (LSB)
0.4
INL (LSB)
VDD = V REF = 2.7V
1.5
0.6
0.2
0.0
-0.2
Negative INL
-0.4
Positive INL
0.5
0.0
-0.5
Negative INL
-1.0
-0.6
-1.5
-0.8
-2.0
-1.0
0
25
50
75
100
125
0
150
20
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
2.0
1.5
1.5
INL (LSB)
0.0
V DD = 2.7V
Negative INL
Positive INL
0.5
0.0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
Negative INL
-2.0
0
1
2
3
4
5
0.0
0.5
1.0
VREF (V)
FIGURE 2-2:
1.5
2.0
2.5
3.0
VREF (V)
Integral Nonlinearity (INL) vs. VREF.
FIGURE 2-5:
(VDD = 2.7V).
Integral Nonlinearity (INL) vs. VREF
1.0
1.0
0.8
0.8
VDD = VREF = 2.7V
0.6
0.6
FSAMPLE = 50 ksps
0.4
0.4
INL (LSB)
INL (LSB)
100
FSAMPLE = 50 ksps
1.0
Positive INL
-0.5
80
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
2.0
0.5
60
Sample Rate (ksps)
1.0
INL (LSB)
40
0.2
0.0
-0.2
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048
2560 3072
3584 4096
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
(Representative Part).
© 2007 Microchip Technology Inc.
0
512
1024 1536
2048 2560 3072
3584 4096
Digital Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, VDD = 2.7V).
DS21290D-page 5
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
1.0
1.0
0.8
V DD = VREF = 2.7V
0.6
0.6
FSAMPLE = 50 ksps
0.4
0.4
Positive INL
INL (LSB)
INL (LSB)
0.8
0.2
0.0
Negative INL
-0.2
-0.4
Positive INL
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
Negative INL
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
Integral
Nonlinearity
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-7:
Temperature.
0
(INL)
vs.
FIGURE 2-10: Integral
Nonlinearity
Temperature (VDD = 2.7V).
1.0
2.0
0.8
1.5
(INL)
vs.
VDD = VREF = 2.7V
0.6
1.0
Positive DNL
DNL (LSB)
DNL (LSB)
0.4
0.2
0.0
-0.2
Negative DNL
-0.4
Positive DNL
0.5
0.0
-0.5
Negative DNL
-1.0
-0.6
-1.5
-0.8
-1.0
-2.0
0
25
50
75
100
125
150
0
20
Nonlinearity
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8: Differential
Sample Rate.
40
(DNL)
vs.
FIGURE 2-11: Differential
Sample Rate (VDD = 2.7V).
3.0
3.0
2.0
2.0
Nonlinearity
(DNL)
vs.
DNL (LSB)
DNL (LSB)
VDD = 2.7V
1.0
Positive DNL
0.0
Negative DNL
-1.0
FSAMPLE = 50 ksps
Positive DNL
1.0
0.0
Negative DNL
-1.0
-2.0
-3.0
-2.0
0
1
2
3
4
0.0
5
Differential
DS21290D-page 6
Nonlinearity
1.0
1.5
2.0
2.5
3.0
VREF(V)
VREF (V)
FIGURE 2-9:
VREF.
0.5
(DNL)
vs.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF
(VDD = 2.7V).
© 2007 Microchip Technology Inc.
MCP3201
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
DNL (LSB)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
0.2
0.0
-0.2
-0.4
FSAMPLE = 50 ksps
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
V DD = V REF = 2.7V
-1.0
0
512
1024 1536 2048 2560 3072 3584 4096
0
512
1024 1536
Digital Code
Digital Code
FIGURE 2-13: Differential Nonlinearity
Code (Representative Part).
(DNL)
vs.
FIGURE 2-16: Differential Nonlinearity
Code (Representative Part, VDD = 2.7V).
1.0
1.0
0.8
0.8
0.2
0.0
-0.2
Negative DNL
-0.4
(DNL)
vs.
V DD = VREF = 2.7V
FSAMPLE = 50 ksps
0.6
Positive DNL
DNL (LSB)
DNL (LSB)
0.6
0.4
2048 2560 3072 3584 4096
Positive DNL
0.4
0.2
0.0
-0.2
Negative DNL
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
Temperature (°C)
FIGURE 2-14: Differential
Temperature.
0
25
50
75
100
Temperature (°C)
Nonlinearity
(DNL)
vs.
FIGURE 2-17: Differential
Temperature (VDD = 2.7V).
Nonlinearity
(DNL)
vs.
20
5
18
Offset Error (LSB)
Gain Error (LSB)
4
VDD = 2.7V
3
FSAMPLE = 50 ksps
2
1
0
VDD = 5V
-1
FSAMPLE = 100 ksps
16
VDD = 5V
14
FSAMPLE = 100 ksps
12
10
8
VDD = 2.7V
6
FSAMPLE = 50ksps
4
2
-2
0
0
1
2
3
VREF(V)
FIGURE 2-15: Gain Error vs. VREF.
© 2007 Microchip Technology Inc.
4
5
0
1
2
3
4
5
VREF (V)
FIGURE 2-18: Offset Error vs. VREF.
DS21290D-page 7
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
2.0
1.0
1.8
0.6
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
0.4
Offset Error (LSB)
Gain Error (LSB)
0.8
0.2
0.0
-0.2
-0.4
-0.6
VDD = VREF = 5V
FSAMPLE = 100 ksps
-0.8
-25
0
25
50
75
VDD = V REF = 5V
1.4
FSAMPLE = 100 ksps
1.2
1.0
0.8
VDD = V REF = 2.7V
0.6
FSAMPLE = 50 ksps
0.4
0.2
0.0
-1.0
-50
1.6
-50
100
-25
0
Temperature (°C)
75
100
FIGURE 2-22: Offset Error vs. Temperature.
100
100
90
VDD = VREF = 5V
90
80
FSAMPLE = 100 ksps
80
SINAD (dB)
70
SNR (dB)
50
Temperature (°C)
FIGURE 2-19: Gain Error vs. Temperature.
60
50
VDD = VREF = 2.7V
40
FSAMPLE = 50 ksps
30
VDD = VREF = 5V
FSAMPLE = 100 ksps
70
60
50
VDD = VREF = 2.7V
40
FSAMPLE = 50 ksps
30
20
20
10
10
0
0
1
10
1
100
10
Input Frequency (kHz)
100
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input
Frequency.
FIGURE 2-23:
Signal to Noise and Distortion
(SINAD) vs. Input Frequency.
0
80
-10
VDD = VREF = 5V
70
-20
FSAMPLE = 100 ksps
60
-40
VDD = VREF = 2.7V
-50
FSAMPLE = 50 ksps
SINAD (dB)
-30
THD (dB)
25
-60
-70
-80
-90
50
VDD = VREF = 2.7V
40
FSAMPLE = 50 ksps
30
20
10
VDD = V REF = 5V, FSAMPLE = 100 ksps
0
-100
1
10
100
Input Frequency (kHz)
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
Input Frequency.
DS21290D-page 8
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
FIGURE 2-24:
Signal to Noise and Distortion
(SINAD) vs. Input Signal Level.
© 2007 Microchip Technology Inc.
MCP3201
12.0
12.00
11.75
11.50
11.25
11.00
10.75
10.50
10.25
10.00
9.75
9.50
9.25
9.00
V DD = 5V
11.5
FSAMPLE = 100 ksps
11.0
VDD = VREF = 5V
FSAMPLE =100 ksps
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
ENOB (rms)
ENOB (rms)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
10.5
10.0
9.5
9.0
VDD = 2.7V
8.5
FSAMPLE = 50 ksps
8.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
VREF (V)
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs.
VREF.
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
Input Frequency.
0
V DD = VREF = 5V, FSAMPLE = 100 ksps
90
SFDR (dB)
80
70
60
50
40
V DD = VREF = 2.7V
30
FSAMPLE = 50 ksps
20
10
0
1
10
100
Power Supply Rejection (dB)
100
-10
-20
-30
-40
-50
-60
-70
-80
1
Input Frequency (kHz)
FIGURE 2-26: Spurious Free
(SFDR) vs. Input Frequency.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Dynamic
Range
FSAMPLE = 100 ksps
FINPUT = 9.985kHz
4096 points
10000
20000
30000
40000
50000
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10 kHz input
(Representative Part).
© 2007 Microchip Technology Inc.
100
1000
10000
FIGURE 2-29: Power Supply Rejection (PSR) vs.
Ripple Frequency.
V DD = VREF = 5V
0
10
Ripple Frequency (kHz)
Amplitude (dB)
Amplitude (dB)
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
FINPUT = 998.76 Hz
4096 points
0
5000
10000
15000
20000
25000
Frequency (Hz)
FIGURE 2-30: Frequency Spectrum of 1 kHz input
(Representative Part, VDD = 2.7V).
DS21290D-page 9
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
500
100
VREF = V DD
450
at VREF = VDD = 2.5V, FCLK = 800 kHz
70
IREF (µA)
IDD (µA)
All points at FCLK = 1.6 MHz, except
80
at VREF = V DD = 2.5V, FCLK = 800 kHz
350
VREF = VDD
90
All points at FCLK = 1.6 MHz, except
400
300
250
200
60
50
40
150
30
100
20
50
10
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
3.5
5.0
5.5
6.0
FIGURE 2-34: IREF vs. VDD.
FIGURE 2-31: IDD vs. VDD.
400
100
VDD = VREF = 5V
90
350
80
VDD = V REF = 5V
300
70
IREF (µA)
IDD (µA)
4.5
VDD (V)
VDD (V)
250
200
VDD = V REF = 2.7V
150
60
50
40
V DD = VREF = 2.7V
30
100
20
50
10
0
0
10
100
1000
10
10000
100
1000
10000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-35: IREF vs. Clock Frequency.
FIGURE 2-32: IDD vs. Clock Frequency.
400
100
350
300
VDD = VREF = 5V
90
VDD = VREF = 5V
FCLK = 1.6 MHz
80
FCLK = 1.6 MHz
70
250
IREF (µA)
IDD (µA)
4.0
200
VDD = VREF = 2.7V
150
60
50
40
30
FCLK = 800 kHz
100
VDD = VREF = 2.7V
20
FCLK = 800 kHz
10
50
0
0
-50
-25
0
25
50
Temperature (°C)
FIGURE 2-33: IDD vs. Temperature.
DS21290D-page 10
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-36: IREF vs. Temperature.
© 2007 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C
80
2.0
Analog Input Leakage (nA)
VREF = CS = VDD
70
IDDS (pA)
60
50
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.8
V DD = V REF = 5V
1.6
FCLK = 1.6 MHz
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
75
100
Temperature (°C)
VDD (V)
FIGURE 2-39: Analog Input Leakage Current vs.
Temperature.
FIGURE 2-37: IDDS vs. VDD.
100.00
VDD = V REF = CS = 5V
IDDS (nA)
10.00
1.00
0.10
0.01
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-38: IDDS vs. Temperature.
© 2007 Microchip Technology Inc.
DS21290D-page 11
MCP3201
3.0
PIN DESCRIPTIONS
3.1
IN+
Positive analog input. This input can vary from IN- to
VREF + IN-.
3.2
IN-
Negative analog input. This input can vary ±100 mV
from VSS.
3.3
Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.4
Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.5
Serial Data Output (DOUT)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
4.0
DEVICE OPERATION
The MCP3201 A/D Converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens
and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit
digital output code. Conversion rates of 100 ksps are
possible on the MCP3201. See Section 6.2 for information on minimum clock rates. Communication with the
device is done using a 3-wire SPI-compatible interface.
4.1
Analog Inputs
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to
charge the capacitor (CSAMPLE). Consequently, a larger
source impedance increases the offset, gain, and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational amplifier such as the MCP601, which has a closed loop output impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above
Vss, then the FFFh code will not be seen unless the
IN+ input level goes above VREF level.
4.2
Reference Input
The reference input (VREF) determines the analog input
voltage range and the LSB size, as shown below.
V REF
LSB Size = ------------4096
As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is a function of the analog input signal and the reference input as shown
below.
4096*VIN
Digital Output Code = -----------------------V REF
where:
VIN = analog input voltage = V(IN+) - V(IN-)
VREF = reference voltage
When using an external voltage reference device, the
system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a
direct effect on the operation of the A/D Converter.
The MCP3201 provides a single pseudo-differential
input. The IN+ input can range from IN- to VREF
(VREF +IN-). The IN- input is limited to ±100 mV from the
VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the
IN+ and IN- inputs.
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough time
to acquire a 12-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
DS21290D-page 12
© 2007 Microchip Technology Inc.
MCP3201
VDD
RSS
VT = 0.6V
CHx
CPIN
7 pF
VA
Sampling
Switch
VT = 0.6V
SS
ILEAKAGE
±1 nA
RS = 1 kΩ
CSAMPLE
= DAC capacitance
= 20 pF
VSS
LEGEND
VA
Rss
CHX
CPIN
VT
ILEAKAGE
SS
Rs
CSAMPLE
FIGURE 4-1:
=
=
=
=
=
=
=
=
=
Signal Source
Source Impedance
Input Channel Pad
Input Pin Capacitance
Threshold Voltage
Leakage Current At The Pin
Due To Various Junctions
Sampling Switch
Sampling Switch Resistor
Sample/hold Capacitance
Analog Input Model.
Clock Frequency (MHz)
1.8
1.6
VDD = VREF = 5V
1.4
1.2
1.0
0.8
0.6
VDD = VREF = 2.7V
0.4
0.2
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input
Resistance (RS) to maintain less than a 0.1 LSB
deviation in INL from nominal conditions.
© 2007 Microchip Technology Inc.
DS21290D-page 13
MCP3201
5.0
SERIAL COMMUNICATIONS
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 12 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
Communication with the device is done using a standard SPI-compatible serial interface. Initiating communication with the MCP3201 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate communication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 12 clocks will output the result of the convertCYC
TCSH
CS
POWER
DOWN
TSUCS
CLK
HI-Z
DOUT
tDATA**
tCONV
TSAMPLE
NULL
BIT B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
HI-Z
B0*
NULL
BIT B11 B10
B9
B8
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure below.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with MCP3201 using MSB first Format.
tCYC
tCSH
CS
tSUCS
POWER DOWN
CLK
tSAMPLE
DOUT
tDATA**
tCONV
HI-Z
NULL
BIT
B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0 B1
B2 B3
B4
B5
B6 B7 B8 B9 B10 B11*
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2:
Communication with MCP3201 using LSB first Format.
DS21290D-page 14
© 2007 Microchip Technology Inc.
MCP3201
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3201 with
Microcontroller SPI Ports
controller’s receive buffer will contain two unknown bits
(the output is at high impedance for the first two
clocks), the null bit and the highest order five bits of the
conversion. After the second eight clocks have been
sent to the device, the MCU receive register will contain
the lowest order seven bits and the B1 bit repeated as
the A/D Converter has begun to shift out LSB first data
with the extra clock. Typical procedure would then call
for the lower order byte of data to be shifted right by one
bit to remove the extra B1 bit. The B7 bit is then transferred from the high order byte to the lower order byte,
and then the higher order byte is shifted one bit to the
right as well. Easier manipulation of the converted data
can be obtained by using this method.
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3201. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3201 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3201 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3201. Figure 6-1 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the A/D Converter
on the falling edge of the third clock pulse. After the first
eight clocks have been sent to the device, the micro-
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D
Converter on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out of A/D
Converter on falling edges
DOUT
HI-Z
NULL B11 B10
BIT
B9
B7
B8
B6
B5
B4
B3
B2
B1
B0
B1 B2
HI-Z
LSB first data begins
to come out
?
?
0
B11 B10 B9
B8
B7
B6
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-1:
B5
B4
B3
B2
B1
B0
B1
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D
Converter on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out of A/D
Converter on falling edges
DOUT
HI-Z
NULL B11 B10
BIT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
HI-Z
LSB first data begins
to come out
?
?
0
B11 B10 B9
B8
B7
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-2:
B6
B5
B4
B3
B2
B1
B0
B1
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
© 2007 Microchip Technology Inc.
DS21290D-page 15
MCP3201
6.2
Maintaining Minimum Clock Speed
When the MCP3201 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst case condition), the part will maintain
proper charge on the sample capacitor for at least
1.2 ms after the sample period has ended. This means
that the time between the end of the sample period and
the time that all 12 data bits have been clocked out
must not exceed 1.2 ms (effective clock frequency of
10 kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire
conversion cycle, the A/D Converter does not require a
constant clock speed or duty cycle, as long as all timing
specifications are met.
6.3
Buffering/Filtering the Analog Inputs
6.4
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is
also recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results. This is illustrated in Figure 6-3 where an op
amp is used to drive the analog input of the MCP3201.
This amplifier provides a low impedance source for the
converter input and a low pass filter, which eliminates
unwanted high frequency noise.
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
VDD
Connection
Device 4
Device 1
Device 3
Device 2
VDD
10 µF
4.096V
Reference
0.1 µF
10 µF
MCP1541
CL
FIGURE 6-4: VDD traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
1 µF
VREF
IN+
MCP3201
VIN
R1
C1
MCP601
IN-
+
R2
-
C2
R3
R4
FIGURE 6-3: The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3201.
DS21290D-page 16
© 2007 Microchip Technology Inc.
MCP3201
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Example:
MCP3201
I/PNNN e3
0725
8-Lead SOIC (150 mil)
Example:
MCP3201
ISN e3 0725
NNN
XXXXXXXX
XXXXYYWW
NNN
Example:
8-Lead MSOP
3201I e3
XXXXXX
YWWNNN
725NNN
Example:
8-Lead TSSOP
XXXX
3201 e3
YYWW
0725
NNN
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS21290D-page 17
MCP3201
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
8
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.348
.365
.400
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
DS21290D-page 18
© 2007 Microchip Technology Inc.
MCP3201
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
MILLMETERS
MIN
N
Pitch
e
Overall Height
A
β
NOM
MAX
8
1.27 BSC
–
–
1.75
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
Overall Width
E
6.00 BSC
Molded Package Width
E1
3.90 BSC
Overall Length
D
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
4.90 BSC
1.04 REF
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
© 2007 Microchip Technology Inc.
DS21290D-page 19
MCP3201
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.75
0.85
0.95
Standoff
A1
0.00
–
0.15
Overall Width
E
Molded Package Width
E1
3.00 BSC
Overall Length
D
3.00 BSC
Foot Length
L
Footprint
L1
1.10
4.90 BSC
0.40
0.60
0.80
0.95 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.08
–
0.23
Lead Width
b
0.22
–
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B
DS21290D-page 20
© 2007 Microchip Technology Inc.
MCP3201
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
2.90
3.00
3.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
© 2007 Microchip Technology Inc.
DS21290D-page 21
MCP3201
NOTES:
DS21290D-page 22
© 2007 Microchip Technology Inc.
MCP3201
APPENDIX A:
REVISION HISTORY
Revision D (January 2007)
This revision includes updates to the packaging
diagrams.
© 2007 Microchip Technology Inc.
DS21290D-page 23
MCP3201
NOTES:
DS21290D-page 24
© 2007 Microchip Technology Inc.
MCP3201
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
PART NO.
Device
Device:
/XX
Temperature
Range
Package
MCP3201: 12-Bit A/D Converter w/SPI Interface
MCP3201T: 12-Bit A/D Converter w/SPI Interface
(Tape and Reel) (SOIC and TSSOP only)
Temperature Range:
I
= -40°C to +85°C
Package:
MS
P
SN
ST
=
=
=
=
Examples:
a)
MCP3201-I/P: Industrial Temperature,
PDIP package.
b)
MCP3201-I/SN: Industrial Temperature,
SOIC package.
c)
MCP3201-I/ST: Industrial Temperature,
TSSOP package.
d)
MCP3201-I/MS: Industrial Temperature,
MSOP package.
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
© 2007 Microchip Technology Inc.
DS21290D-page25
MCP3201
NOTES:
DS21290D-page 26
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS21290D-page 27
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12/08/06
DS21290D-page 28
© 2007 Microchip Technology Inc.