TI LC541A

SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
•
FEATURES
2
20
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
20
A2
A1
OE1
VCC
1
2
19 OE2
3
18 Y1
4
17 Y2
16 Y3
15 Y4
5
6
14 Y5
13 Y6
7
8
12 Y7
9
10
A3
A4
A5
A6
A7
4
3 2
1 20 19
18
5
6
17
16
7
15
14
9 10 11 12 13
8
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
1
SN54LVC541A . . . FK PACKAGE
(TOP VIEW)
SN74LVC541A . . . RGY PACKAGE
(TOP VIEW)
GND
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
ABC
OE2
SN54LVC541A . . . J OR W PACKAGE
SN74LVC541A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
•
VCC
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
11
Y8
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.1 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
OE1
•
•
•
•
DESCRIPTION/ORDERING INFORMATION
The SN54LVC541A octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC541A octal
buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
ORDERING INFORMATION
PACKAGE (1)
TA
QFN – RGY
Tube of 25
SN74LVC541ADW
Reel of 2000
SN74LVC541ADWR
SOP – NS
Reel of 2000
SN74LVC541ANSR
LVC541A
SSOP – DB
Reel of 2000
SN74LVC541ADBR
LC541A
Tube of 70
SN74LVC541APW
Reel of 2000
SN74LVC541APWR
Reel of 250
SN74LVC541APWT
TVSOP – DGV
Reel of 2000
SN74LVC541ADGVR
LC541A
CDIP – J
Tube of 20
SNJ54LVC541AJ
SNJ54LVC541AJ
CFP – W
Tube of 85
SNJ54LVC541AW
SNJ54LVC541AW
LCCC – FK
Tube of 55
SNJ54LVC541AFK
SNJ54LVC541AFK
TSSOP – PW
–55°C to 125°C
(1)
TOP-SIDE MARKING
SN74LVC541ARGYR
SOIC – DW
–40°C to 85°C
ORDERABLE PART NUMBER
Reel of 1000
LC541A
LVC541A
LC541A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The 'LVC541A devices are ideal for driving bus lines or buffering memory address registers.
These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board
layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output enable (OE1 or OE2)
input is high, all eight outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
A
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
OE1
OE2
A1
1
19
2
18
To Seven Other Channels
2
Y1
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
DB
θJA
Package thermal impedance
package (4)
70
DGV package (4)
92
DW package (4)
58
NS package (4)
60
PW package (4)
83
RGY package (5)
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature range
V
°C/W
37
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
3
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
Recommended Operating Conditions (1)
SN54LVC541A
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
Low-level input voltage
1.7
2
Input voltage
VO
Output voltage
0.35 × VCC
0.7
0.8
High-level output current
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
TA
(1)
4
Low-level output current
Operating free-air temperature
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
VCC = 1.65 V
IOL
V
0.8
VCC = 1.65 V
IOH
V
2
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
UNIT
1.5
VCC = 1.65 V to 1.95 V
VCC = 2.7 V to 3.6 V
SN74LVC541A
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
–55
125
–40
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
mA
°C
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
(1)
(2)
VCC – 0.2
1.2
2.3 V
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
V
1.65 V to 3.6 V
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
±5
±5
µA
VI = 0 to 5.5 V
3.6 V
Ioff
VI or VO = 5.5 V
0
IOZ
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
UNIT
VCC – 0.2
IOH = –8 mA
IOL = 100 µA
ICC
MIN TYP (1) MAX
1.65 V
IOH = –24 mA
II
SN74LVC541A
MIN TYP (1) MAX
IOH = –4 mA
IOH = –12 mA
VOL
SN54LVC541A
1.65 V to 3.6 V
IOH = –100 µA
VOH
VCC
3.6 V
2.7 V to 3.6 V
V
±10
µA
±15
±10
µA
10
10
10
10
500
500
µA
µA
Ci
VI = VCC or GND
3.3 V
4
4
pF
Co
VO = VCC or GND
3.3 V
5.5
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC541A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MAX
MIN
MAX
tpd
A
Y
5.6
1
5.1
ns
ten
OE
Y
7.5
1
7
ns
tdis
OE
Y
7.7
1
7
ns
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
5
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC541A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
1
15.7
1
7.8
1
5.6
1.5
5.1
ns
ten
OE
Y
1
17.5
1
10.5
1
7.5
1.5
7
ns
tdis
OE
Y
1
16.5
1
9
1
7.7
1.5
7
ns
1
ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
tsk(o)
UNIT
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
6
Power dissipation capacitance
per buffer/driver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
65
58
33
2
2
2
UNIT
pF
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M – JANUARY 1993 – REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9759501Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9759501QRA
ACTIVE
CDIP
J
20
1
TBD
1
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
TBD
A42
N / A for Pkg Type
TBD
Call TI
5962-9759501QSA
ACTIVE
CFP
W
20
SN74LVC541ADBLE
OBSOLETE
SSOP
DB
20
SN74LVC541ADBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADGVRE4
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ADWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ANSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ANSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ANSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWLE
OBSOLETE
TSSOP
PW
20
SN74LVC541APWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC541ARGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
TBD
Addendum-Page 1
Call TI
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC541ARGYRG4
ACTIVE
QFN
RGY
20
SNJ54LVC541AFK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54LVC541AJ
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
SNJ54LVC541AW
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
1000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-2-260C-1YEAR
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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