EM680FV8A Low Power, 1Mx8 SRAM Document Title 1M x 8 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date 0.0 Initial Draft May 10, 2007 1.0 1’st Revision Change I/O information from I/O0~ I/O16 to I/O0~7 May 19, 2007 2.0 2’nd Revision Product code change from EM680FV8AW to EM680FV8A June 1, 2007 2.1 2.1 Revision EMLSI Product information update 2.2 2.2 Revision Fix typo error Nov. 12, 2007 2.3 2.3 Revision Update bonding pad information Nov. 14, 2007 Emerging Memory & Logic Solutions Inc. Remark June 14, 2007 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM680FV8A Low Power, 1Mx8 SRAM 1 56 PAD DIAGRAM FEATURES - Process Technology : 0.15µm Full CMOS - Organization : 1M x 8 bit - Power Supply Voltage => EM680FV8A : 2.7V ~ 3.6V - Low Data Retention Voltage : 1.5V (Min.) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns EM680FV8A (Dual C/S) GENERAL PHYSICAL SPECIFICATIONS - Backside die surface of polished bare silicon - Typical Die Thickness = 725um +/-15um - Typical top-level metallization : => Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms - Topside Passivation : => Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms - Wafer diameter : 8 inch y +x 29 28 (0, 0) EMLSI LOGO FUNCTIONAL BLOCK DIAGRAM PAD DESCRIPTION Function CS1, CS2 Chip select inputs OE WE A0~A19 Output Enable input Write Enable input Name Vcc Power Supply Vss Ground NC Pre-charge Circuit Function A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 No Connected Address Inputs I/O0~I/O7 Data Inputs/outputs VCC Row Select Name I/O0 ~ I/O7 Data Cont VSS Memory Array 2048 x 4096 I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 A19 WE OE CS1 CS2 Control Logic BONDING INSTRUCTIONS The 8M full CMOS LP SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates. EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity. 2 EM680FV8A Low Power, 1Mx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Symbol Voltage on Any Pin Relative to Vss Minimum Unit VIN, VOUT -0.2 to 4.0V V Voltage on Vcc supply relative to Vss VCC -0.2 to 4.0V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 o C * Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O Mode Power H X X X High-Z Deselected Stand by X L X X High-Z Deselected Stand by L H H H High-Z Output Disabled Active L H L H Data Out Read Active L H X L Data In Write Active Note: X means don’t care. (Must be low or high state) 3 EM680FV8A Low Power, 1Mx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Type Max Supply voltage VCC 2.7 3.3 3.6 V Ground VSS 0 0 0 V Input high voltage VIH 2.2 - VCC + 0.22) V Input low voltage VIL -0.23) - 0.6 V 1. 2. 3. 4. Unit TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Ouput capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=VSS to VCC -1 - 1 uA Output leakage current ILO CS1=VIH or OE=VIH or WE=VIL VIO=VSS to VCC -1 - 1 uA Operating power supply ICC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL - - 2 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1<0.2V, CS2>VCC-0.2V VIN<0.2V or VIN>VCC-0.2V - - 4 mA ICC2 Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH Others VIN=VIL or VIH - - 45 35 25 mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.2 - - V Standby Current (TTL) ISB - - 0.5 mA - 2 15 uA Average operating current Standby Current (CMOS) ISB1 45ns 55ns 70ns CS1=VIH, CS2=VIL Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) or 0V<CS2<0.2V (CS2 controlled) Other inputs=0 ~ VCC (Typ. condition : VCC=3.3V @ 25oC) LF (Max. condition : VCC=3.6V @ 85oC) NOTES 1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested. 4 EM680FV8A Low Power, 1Mx8 SRAM VTM3) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) R12) Input Pulse Level : 0.4 to 2.4V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) R22) CL1) 1. Including scope and Jig capacitance R2=3150 ohm 2. R1=3070 ohm, 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ1,2, tOLZ, tOHZ, tWHZ) READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Symbol 45ns 55ns 70ns Min Max Min Max Min Max Unit Read cycle time tRC 45 - 55 - 70 - ns Address access time tAA - 45 - 55 - 70 ns Chip select to output tco1, tco2 - 45 - 55 - 70 ns tOE - 30 - 35 - 35 ns tLZ1, tLZ2 5 - 5 - 5 - ns Output enable to low-Z output tOLZ 5 5 - ns Chip disable to high-Z output tHZ1, tHZ2 0 20 0 20 0 25 ns tOHZ 0 20 0 20 0 25 ns tOH 10 - 10 - 10 - ns Output enable to valid output Chip select to low-Z output Output disable to high-Z output Output hold from address change 5 WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Symbol 45ns 55ns 70ns Unit Min Max Min Max Min Max tWC 45 - 55 - 70 - ns tCW1, tCW2 45 - 45 - 60 - ns Address setup time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 45 - 60 - ns Write pulse width tWP 45 - 45 - 55 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to ouput high-Z tWHZ 0 20 0 20 0 25 ns Data to write time overlap tDW 25 Data hold from write time tDH 0 - 0 End write to output low-Z tOW 5 - 5 Write cycle time Chip select to end of write 30 5 30 - ns 0 - ns 5 - ns EM680FV8A Low Power, 1Mx8 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA tOH tCO1,2 CS1 CS2 tHZ1,2 tOE OE Data Out High-Z tOHZ tOLZ Data Valid tLZ1,2 NOTES (READ CYCLE) 1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to device interconnection. 6 EM680FV8A Low Power, 1Mx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW1,2(2) tWR(4) CS1 CS2 tAW tWP(1) WE tAS(3) Data in High-Z High-Z Data Valid tWHZ Data out tDH tDW tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED) tWC Address tAS(3) tWR(4) tCW1,2(2) CS1 CS2 tAW tWP(1) WE tDW Data in Data out Data Valid High-Z High-Z 7 tDH EM680FV8A Low Power, 1Mx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED) tWC Address tWR(4) tCW1,2(2) CS1 tAS(3) tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high or CS2 going low. 8 EM680FV8A Low Power, 1Mx8 SRAM DATA RETENTION CHARACTERISTICS Parameter Symbol VCC for Data Retention VDR Data Retention Current IDR Chip Deselect to Data Retention Time tSDR Operation Recovery Time tRDR Test Condition Min Typ Max Unit CS1 ≥ Vcc-0.2V 1) 1.5 - 3.6 V - - 4 uA 0 - - tRC - - VCC=1.5V, CS1 ≥ Vcc-0.2V 1) See data retention wave form NOTES 1. CS1 ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V (CS1 controlled) or CS2 ≤ 0.2V (CS2 controlled) DATA RETENTION WAVE FORM CS1 Controlled tSDR Data Retention Mode tRDR Vcc 2.7V 2.2V VDR CS1 > Vcc-0.2V CS1 GND CS2 Controlled Data Retention Mode Vcc 2.7V CS2 tRDR tSDR VDR 0.4V CS2 < 0.2V GND 9 ns EM680FV8A Low Power, 1Mx8 SRAM SRAM PART CODING SYSTEM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 11. Power 2. Product Type 10. Speed 3. Density 4. Function 9. Package 5. Technology 8. Generation 6. Operating Voltage 7. Organization 1. Memory Component EM --------------------- Memory 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 2. Product Type 6 ------------------------ SRAM 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 5. Technology F ------------------------- Full CMOS 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------- 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 45ns 55ns 70ns 85ns 100ns 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power 10