EMLSI EMLS232UAW-6E

EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
Document Title
512K x 32 x 4Banks Low Power SDRAM Specificaton
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Apr 7 , 2006
Draft
0.1
DC parameter values are changed
Jul 21 , 2006
Advanced
0.2
DC parameter values are changed.
Wafer spec & PAD allocation are attached.
PAD coordinates are not fixed (TBD).
Special MRS mode (Wrap off) supported.
Sep 2 , 2006
Advanced
0.3
Pad allocation changed.
(NC Pad added to right bottom)
Sep 21 , 2006
Advanced
0.4
Pad coordinates are updated.
Dec 6 , 2006
Advanced
0.5
Pad allocation changed. (BA0,BA1)
Dec 19 , 2006
Advanced
0.6
DC parameter values are revised.
Sep 10 , 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
512K x 32Bit x 4 Banks Low Power SDRAM
FEATURES
GENERAL DESCRIPTION
1.8V power supply.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length(1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
Special Function Support.
. PASR(Partial Array Self Refresh).
. Internal auto TCSR (Temperature Compensated Self Refresh)
. DS (Driver Strength)
. Deep power down
DQM for masking.
Auto refresh.
64 refresh period (4K cycle).
Commercial Temperature Operation (-0 ~ 70 )
Extended Temperature Operation (-25 ~ 85 )
The EMLS232UA series is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 534,288 words by 32 bits,
fabricated with Ramsway’s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock and I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
lengths and programmable latencies allow the same device to be
useful for a variety of high bandwidth and high performance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
EMLS232UAW-6(E)
133
(CL3), 100
(CL2)
Interface
Package
LVCMOS
Wafer Biz.
NOTE :
1. In case of 40 Frequency, CL1 can be supported.
2. Ramsway are not designed or manufactured for use in a device or system that is used under circumstance in which human life is
potentially at stake. Please contact to the memory marketing team in ramsway when considering the use of a product
contained herein for any specific purpose, such as medical,aerospace, nuclear, military, vehicular or undersea repeater use.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
General Wafer Specifications
Process Technology : 0.125um Trench DRAM Process
Wafer thickness : 725 +/- 25um
Typical Pad Open Size : 70.2um x 70.2um
Minimum Pad Pitch : 93.6um
Wafer Diameter : 8-inch
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
PAD FUNCTION DESCRIPTION
Pad
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,
Column address : CA0 ~ CA7
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0~DQM3
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ n
Data input/output
Data inputs/outputs are multiplexed on the same pins.: DQ0 ~ 31
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved
noise immunity
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
Bank Select
512K x 32
Output Buffer
512K x 32
Sense AMP
LCBR
512K x 32
LDQM
DQi
Column Decoder
Col. Buffer
Row Buffer
LRAS
Row Decoder
Refresh Counter
ADD
Address Register
CLK
512K x 32
LWE
LCKE
Latency & Burst Length
Programming Register
LRAS
LCBR
LWE
LWCBR
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM0~DQM3
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VIN,VOUT
-1.0 ~ 2.6
V
VDD, VDDQ
-1.0 ~ 2.6
V
TSTG
-55 ~ +150
Power dissipation
PD
1.0
Short circuit current
IOS
50
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
W
NOTE :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25oC~ 85oC for Extended, 0oC~ 70oC for Commercial)
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD
1.7
1.8
1.95
V
1
VDDQ
1.7
1.8
1.95
V
1
Input logic high voltage
VIH
0.8 x VDDQ
1.8
VDDQ + 0.3
V
2
Input logic low voltage
VIL
-0.3
0
0.3
V
3
Output logic high voltage
VOH
0.9 x VDDQ
-
-
V
IOH = -0.1
Output logic low voltage
VOL
-
-
0.2
V
IOL = 0.1
ILI
-2
-
2
Supply voltage
Input leakage current
4
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD.
2.VIH (max) = 2.2V AC. The overshoot voltage duration is
3
3.VIL (min) = -1.0V AC. The undershoot voltage duration is
3 .
4.Any input 0V
VIN
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5.Dout is disabled, 0V
VOUT
VDDQ.
CAPACITANCE
(VDD = 1.8V, TA = 23
, f=1
, VREF =0.9V
Pin
50
)
Symbol
Min
Max
CCLK
1.5
3.5
CIN
1.5
3.0
Address
CADD
1.5
3.0
DQ0 ~ DQ31
COUT
2.0
4.5
Clock
RAS, CAS, WE, CS, CKE, DQM0~DQM3
Unit
Note
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
DC CHARACTERISRICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0oC~ 70oC for Extended, -25oC~ 85oC for Commercial)
Parameter
Symbol
Operating Current
(One Bank Active)
ICC1
Version
Test Condition
133MHz
Active mode; Burst length = 2; Read or Write;
tRC
tRC(min); CL=3; tCC=10
IO= 0
Unit
65
Note
1
Precharge Standby Current in power-down
mode
Precharge Standby Current in non power-down
mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode (One Bank Active)
ICC2P
CKE
VIL(max), tCC=10
0.15
ICC2PS
CKE & CLK
ICC2N
CKE
VIH(min), CS
VIH(min), tCC = 10
Input signals are changed one time during 20
VIL(max), tCC =
0.15
15
ICC2NS
ICC3P
CKE
VIH(min), CLK
Input signals are stable
VIL(max), tCC =
VIL(max), tCC = 10
CKE
2
0.5
ICC3PS
CKE & CLK
ICC3N
CKE
VIH(min), CS
VIH(min), tCC = 10
Input signals are changed one time during 20
ICC3NS
VIL(max), tCC =
0.5
CKE
VIH(min), CLK
Input signals are stable
20
VIL(max), tCC =
10
Operating Current
(Burst Mode)
ICC4
IO = 0
Page burst, CL=3, Read or Write, tCC = 10
4Banks Activated
Refresh Current
ICC5
tARFC
Self Refresh Current
Deep Power Down
mode current
ICC6
CKE
tARFC(min), tCC = 10
75
80
0.2V
ICC7
2
Internal Auto
TCSR
Max
15
Max
45
Max
70
Max
85
4 Banks
210
220
230
250
2 Banks
160
170
180
190
1 Bank
130
135
140
150
10
1
NOTE :
1.Measured with outputs open.
2.Refresh period is 64 .
3.Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
AC OPERATING TEST CONDITIONS
(VDD = 1.7V ~ 1.95V, TA = 0
~ 70
for Commercial, -25
~85
for Extendedl)
Parameter
Value
0.9
AC input levels(Vih/Vil)
VDDQ / 0.2
V
VDDQ
V
0.5
Input timing measurement reference level
Input rise and fall time
Unit
tr/tf = 1/1
Output timing measurement reference level
0.5
Output load condition
See Figure 2
10.6
VDDQ
V
1.8V
Vtt=0.5
13.9
50
VOH (DC) =VDDQ - 0.2V, IOH = -0.1
VOL (DC) = 0.2V, IOL = 0.1
Output
20
Output
Z0=50
CL
VDDQ
20
10
5
2.5
(Full DS)
(Half DS)
(Quarter DS)
(Octant DS)
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Row active to row active delay
tRRD(min)
15
RAS to CAS delay
tRCD(min)
22.5
tRP(min)
22.5
tRAS(min)
45
tRAS(max)
70,000
Row cycle time
tRC(min)
67.5
Last data in to row precharge
tRDL(min)
15
Last data in to Active delay
tDAL(min)
tRDL + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Auto refresh cycle time
tARFC(min)
80
Exit self refresh to active command
tSRFX(min)
120
Col. address to col. address delay
tCCD(min)
1
Row precharge time
Row active time
Number of valid output data
CAS latency=3
2
Number of valid output data
CAS latency=2
1
Number of valid output data
CAS latency=1
-
Unit
Note
1
1
1
1
1
2
3
CLK
4
ea
5
NOTE :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the
next higher integer.
2. Minimum dealy is required to complete write.
3. Maximum burst refresh cycle: 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
CAS latency=3
tCC
7.5
CAS latency=2
tCC
10
CAS latency=1
tCC
-
CAS latency=3
tAC
6
CAS latency=2
tAC
7
CAS latency=1
tAC
-
CAS latency=3
tOH
2.5
CAS latency=2
tOH
2.5
CAS latency=1
tOH
-
CLK high pulse width
tCH
2.5
CLK low pulse width
tCL
2.5
Input setup time
tSS
2.0
Input hold time
tSH
1
CLK to output in Low-Z
tSLZ
1
CLK cycle time
CLK to valid output delay
Output data hold time
CAS latency=2
1000
Note
1
1,2,3
2
4
4
4
4
2
6
CAS latency=3
CLK to output in Hi-Z
Unit
tSHZ
CAS latency=1
7
-
NOTE :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1 , (tr/2-0.5) should be added to the parameter.
3. tAC(max) value is measured at the low Vdd(1.7V) and cold temperature(-25 ).
tAC is measured in the device with half driver strength(CL=10pF) and under the AC output load condition.
4. Assumed input rise and fall time (tr & tf) = 1 .
If tr & tf is longer than 1 , transient time compensation should be considered,
i.e., [(tr + tf)/2-1] should be added to the parameter.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Auto Refresh
Refresh
Entry
Self
Refresh
Exit
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP CODE
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
H
H
L
BA0, 1
H
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Entry
H
L
H
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Entry
H
L
H
X
X
X
X
H
X
X
X
L
V
V
V
L
H
H
L
H
X
X
X
L
V
V
V
Read &
Column
Address
Auto Precharge Disable
Write &
Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Bank Selection
All Banks
Clock Suspend or
Active Power Down
CKEn
L
Bank Active & Row Addr.
Precharge
CKEn-1
Precharge Power
Down Mode
Exit
L
H
Entry
H
L
Deep Power Down
Exit
L
DQM
H
No Operation Command
H
H
X
X
H
X
X
X
L
H
H
H
X
A10/AP
A9 ~ A0
Note
1, 2
3
3
3
3
Row Address
L
H
L
H
Column
Address
(A0~A7)
Column
Address
(A0~A7)
X
V
L
X
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X =Don'
t care, H=Logic High, L=Logic Low)
NOTE :
1. OP Code : Operand Code
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0),
but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
Address
BA0 ~ BA1
A10/AP*1
A9*3
Function
"0" Setting for
Normal MRS
Wrap Mode
0: Wrap on
1: Wrap off
W.B.L
A8
A7
A6
Test Mode
A5
A4
A3
CAS Latency
A2
A1
BT
A0
Burst Length
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Write Burst Length
Mode Select
BA1
A9
Length
1
0
1
Reserved
0
Burst
1
1
0
Reserved
1
Single Bit
1
1
1
Reserved
BA0
0
Mode
setting
for Normal
MRS
0
Full Page Length x32 : 64Mb(256)
Register Programmed with Extended MRS
Address
BA1
Function
BA0
A10/AP
A9
A8
A7
A6
RFU*2
Mode Select
A5
A4
A3
A2
RFU*2
DS
A1
A0
PASR
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
Driver Strength
PASR
BA1
BA0
MODE
A6
A5
Driver Strength
A2
A1
A0
Size of Refreshed Array
0
0
Normal MRS
0
0
Full
0
0
0
Full Banks (default)
0
1
Reserved
0
1
1/2 (default)
0
0
1
Two Banks (Bank 0,1)
1
0
EMRS for Low Power SDRAM
1
0
1/4
0
1
0
One Bank (Bank 0)
1
1
Reserved
1
1
1/8
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Reserved Address
A10/AP
A9
A8
A7
A4
A3
0
0
0
0
0
0
NOTE :
1. If A10/AP is high during MRS cycle, “Wrap off mode” function will be enabled. This mode support only sequential burst type.
2. RFU(Reserved for future use) should stay “0” during MRS cycle.
3. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Low Power SDRAM has PASR option.
2. Low Power SDRAM supports 3 kinds of PASR in self refresh mode : Four banks, Two banks and One bank.
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- Two Banks (Bank0,1)
- One Bank (Bank0)
- Four Banks
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
NOTE :
1. In order to save power consumption,Low power SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range : Max 85 , Max 70 , Max 45 , Max 15
2. If the EMRS for exteranl TCSR is issued by the controller, this EMRS code for TCRS is ignored.
3. It has +/- 5 tolerance.
Temperature Range
Max 85
Max 70
Self Refresh Current (Icc6)
Full Array
1/2 of Full Array
1/4 of Full Array
250
190
150
230
180
140
220
170
135
210
160
130
Unit
Max. 45
Max 15
3
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
-Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a mininmun of 200 .
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is half driver strength and full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
C. BURST SEQUENCE (Wrap on mode)
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
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Rev 0.6