SLLS104I − DECEMBER 1990 − REVISED SEPTEMBER 2004 D D D D D D D description/ordering information The AM26C32 is a quadruple differential line receiver for balanced or unbalanced digital data transmission. The enable function is common to all four receivers and offers a choice of active-high or active-low input. The 3-state outputs permit connection directly to a bus-organized system. Fail-safe design specifies that if the inputs are open, the outputs always are high. 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B AM26C32M . . . FK PACKAGE (TOP VIEW) 1A 1B NC VCC 4B D D ANSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11 Low Power, ICC = 10 mA Typ ±7-V Common-Mode Range With ±200-mV Sensitivity Input Hysteresis . . . 60 mV Typ tpd = 17 ns Typ Operates From a Single 5-V Supply 3-State Outputs Input Fail-Safe Circuitry Improved Replacements for AM26LS32 Available in Q-Temp Automotive − High Reliability Automotive Applications − Configuration Control/Print Support − Qualification to Automotive Standards AM26C32C . . . D, N, OR NS PACKAGE AM26C32I . . . D, N, NS, OR PW PACKAGE AM26C32Q . . . D PACKAGE AM26C32M . . . J OR W PACKAGE (TOP VIEW) 1Y G NC 2Y 2A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A 4Y NC G 3Y 2B GND NC 3B 3A D Meets or Exceeds the Requirements of NC − No internal connection The AM26C32 devices are manufactured using a BiCMOS process, which is a combination of bipolar and CMOS transistors. This process provides the high voltage and current of bipolar with the low power of CMOS to reduce the power consumption to about one-fifth that of the standard AM26LS32, while maintaining ac and dc performance. The AM26C32C is characterized for operation from 0°C to 70°C. The AM26C32I is characterized for operation from −40°C to 85°C. The AM26C32Q is characterized for operation from −40°C to 125°C. The AM26C32M is characterized for operation over the full military temperature range of −55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"# $% $ ! ! & ' $$ ()% $ !* $ #) #$ * ## !% !$ !# + +,--. ## ! $ # &( $% ## & !$. !$ !* $ #) #$ * ## !% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLLS104I − DECEMBER 1990 − REVISED SEPTEMBER 2004 description/ordering information (continued) ORDERING INFORMATION PDIP (N) 0°C to 70°C −40°C −40 C to 85 85°C C −40°C to 125°C −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube of 25 AM26C32CN Tube of 40 AM26C32CD Reel of 2500 AM26C32CDR SOP (NS) Reel of 2000 AM26C32CNSR 26C32 PDIP (N) Tube of 25 AM26C32IN AM26C32IN Tube of 40 AM26C32ID Reel of 2500 AM26C32IDR SOP (NS) Reel of 2000 AM26C32INSR 26C32I TSSOP (PW) Tube of 90 AM26C32IPW 26C32I SOIC (D) Tube of 40 AM26C32QD AM26C32QD CDIP (J) Tube of 25 AM26C32MJ AM26C32MJ CFP (W) Tube of 150 AM26C32MW AM26C32MW SOIC (D) SOIC (D) AM26C32CN AM26C32C AM26C32I LCCC (FK) Tube of 55 AM26C32MFK AM26C32MFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each receiver) DIFFERENTIAL INPUT VID ≥ VIT+ VIT− < VID < VIT+ VID ≤ VIT− X ENABLES OUTPUT Y G G H X H X L H H X ? X L ? H X L X L L L H Z H = high level, L = low level, X = irrelevant Z = high impedance (off), ? = indeterminate 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS104I − DECEMBER 1990 − REVISED SEPTEMBER 2004 logic diagram (positive logic) G G 1A 1B 2A 2B 3A 3B 4A 4B 4 12 2 3 1 1Y 6 5 7 2Y 10 11 9 3Y 14 13 15 4Y Pin numbers shown are for the D, J, N, NS, PW, and W packages. schematics EQUIVALENT OF G OR G INPUT EQUIVALENT OF A OR B INPUT VCC VCC VCC 17 kΩ NOM TYPICAL OF ALL OUTPUTS 1.7 kΩ NOM Input 288 kΩ NOM Input Output GND GND 1.7 kΩ NOM VCC (A inputs) or GND (B inputs) GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLLS104I − DECEMBER 1990 − REVISED SEPTEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI: A or B inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −11 V to 14 V G or G inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Differential input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −14 V to 14 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential output voltage, VOD, are with respect to network GND. Currents into the device are positive and currents out of the device are negative. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions NOM MAX 4.5 5 5.5 UNIT Supply voltage VIL VIC Low-level input voltage 0.8 V Common-mode input voltage ±7 V IOH IOL High-level output current −6 mA Low-level output current 6 mA High-level input voltage 2 AM26C32C TA 4 MIN VCC VIH Operating free-air temperature POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 V V 70 AM26C32I −40 85 AM26C32Q −40 125 AM26C32M −55 125 °C SLLS104I − DECEMBER 1990 − REVISED SEPTEMBER 2004 electrical characteristics over recommended ranges of VCC, VIC, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIT+ Differential input high-threshold voltage VO = VOH(min), IOH = −440 µA VIC = −7 V to 7 V VIC = 0 to 5.5 V VIT− Differential input low-threshold voltage VO = 0.45 V, IOL = 8 mA VIC = −7 V to 7 V VIC = 0 to 5.5 V Vhys Hysteresis voltage (VIT+ − VIT−) VIK VOH Enable input clamp voltage VOL IOZ Low-level output voltage TYP† MAX 0.1 −0.2‡ −0.1‡ Off-state (high-impedance state) output current mV VCC = 4.5 V, VID = 200 mV, II = −18 mA IOH = −6 mA VID = −200 mV, VO = VCC or GND IOL = 6 mA VI = 10 V, VI = −10 V, Other input at 0 V 1.5 Other input at 0 V −2.5 II Line input current IIH IIL High-level enable current Low-level enable current VI = 2.7 V VI = 0.4 V ri Input resistance One input to ground −1.5 3.8 V V 0.2 ±0.5 12 V V 60 High-level output voltage UNIT 0.2 0.3 V ±5 µA mA 20 µA −100 µA 17 kΩ ICC Supply current VCC = 5.5 V 10 15 mA † All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode input voltage. switching characteristics over recommended ranges of operation conditions, CL = 50 pF (unless otherwise noted) TEST CONDITIONS PARAMETER tPLH tPHL Propagation delay time, low- to high-level output tTLH tTHL Output transition time, low- to high-level output tPZH tPZL Output enable time to high level tPHZ tPLZ Output disable time from high level Propagation delay time, high- to low-level output Output transition time, high- to low-level output Output enable time to low level Output disable time from low level † All typical values are at VCC = 5 V, TA = 25°C. See Figure 1 AM26C32C AM26C32I UNIT MIN TYP† MAX MIN TYP† MAX 9 17 27 9 17 27 ns 9 17 27 9 17 27 ns 4 9 4 10 ns 4 9 4 9 ns 13 22 13 22 ns 13 22 13 22 ns 13 22 13 26 ns 13 22 13 25 ns See Figure 1 See Figure 2 See Figure 2 POST OFFICE BOX 655303 AM26C32Q AM26C32M • DALLAS, TEXAS 75265 5 SLLS104I − DECEMBER 1990 − REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION 90% Output A Input 90% 10% Device Under Test B tTHL tTLH VCC 10% tPHL tPLH CL = 50 pF (see Note A) VOH 50% VOL 2.5 V 0V −2.5 V Input TEST CIRCUIT VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 1. Switching Test Circuit and Voltage Waveforms VCC S1 VID = ±2.5 V RL = 1 kΩ G Input G Input A Input Device Under Test B Input tPZL, tPLZ Measurement: S1 to VCC tPZH, tPHZ Measurement: S1 to GND CL = 50 pF (see Note A) TEST CIRCUIT 3V G 1.3 V 0V 3V G (see Note B) 1.3 V 0V tPZH Output (with VID = 2.5 V) tPHZ 50% tPHZ VOH −0.5 V VOH VOL tPZL Output (with VID = −2.5 V) tPZH VOH −0.5 V tPLZ tPZL tPLZ VOH 50% VOL + 0.5 V VOL + 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf = 6 ns. Figure 2. Enable/Disable Time Test Circuit and Output Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9164001Q2A ACTIVE LCCC FK 20 1 TBD 5962-9164001QEA ACTIVE CDIP J 16 1 TBD POST-PLATE Level-NC-NC-NC 5962-9164001QFA ACTIVE CFP W 16 1 AM26C32CD ACTIVE SOIC D 16 40 AM26C32CDBLE OBSOLETE SSOP DB 16 TBD Call TI AM26C32CDE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR AM26C32CDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR AM26C32CDRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR AM26C32CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC AM26C32CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC AM26C32CNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AM26C32CNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AM26C32ID ACTIVE SOIC D 16 CU NIPDAU Level-2-260C-1YEAR AM26C32IDBLE OBSOLETE SSOP DB 16 AM26C32IDG4 ACTIVE SOIC D 16 AM26C32IDR ACTIVE SOIC D AM26C32IDRE4 ACTIVE SOIC AM26C32IDRG4 ACTIVE AM26C32IN A42 SNPB Level-NC-NC-NC TBD A42 SNPB Level-NC-NC-NC Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR Call TI 40 Green (RoHS & no Sb/Br) TBD Call TI 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC AM26C32INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC AM26C32INSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AM26C32INSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AM26C32IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AM26C32IPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AM26C32MFKB ACTIVE LCCC FK 20 1 TBD AM26C32MJB ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC AM26C32MWB ACTIVE CFP W 16 1 TBD A42 SNPB Level-NC-NC-NC AM26C32QD ACTIVE SOIC D 16 40 TBD CU NIPDAU Addendum-Page 1 Call TI POST-PLATE Level-NC-NC-NC Level-1-220C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2005 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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