FREESCALE LP1072

Freescale Semiconductor
Advance Information
Document Number: LP1072
Rev. 0.3, 12/2005
LP1072
802.11a/b/g Baseband System
Solution
1
1.1
Introduction
The LP1070 Family
Freescale Semiconductor’s 802.11 LP1070 family
consists of high-performance, highly optimized PHY
and MAC baseband Wireless LAN processors that fully
implement the IEEE 802.11a, 802.11b and 802.11g PHY
standards. These baseband processors are poised to
revolutionize the Wireless LAN industry by setting new
standards for power consumption, size, cost and
performance.
The LP1070 family is based on Freescale's proprietary
Wireless Broadband Signal Processor™ (WBSP™), an
innovative and revolutionary receiver architecture that
significantly reduces size and power consumption while
providing maximum flexibility to support multiple
wireless standards with no additional overhead.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Functional Description . . . . . . . . . . . . . . . . . 4
4 LP1072 Interfaces . . . . . . . . . . . . . . . . . . . . . 10
5 Timers/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Pinout and Footprint . . . . . . . . . . . . . . . . . . 17
7 DC Electrical Specifications . . . . . . . . . . . . 24
8 Timing Characteristics . . . . . . . . . . . . . . . . . 26
9 Mechanical Dimensions . . . . . . . . . . . . . . . . 29
10 Development Support . . . . . . . . . . . . . . . . . 29
11 Appendix: Comparison of LP1071 and
LP1072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12 Revision History . . . . . . . . . . . . . . . . . . . . . 31
In addition to their superior performance and ultra low
power consumption, the LP1070 processors provide the
customers with the flexibility to tailor the chip
characteristics to their needs. With software control, the
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
PRELIMINARY
Introduction
terminal manufacturers can tune the chip performance to get the exact balance they opt for when it comes
to power consumption and performance.
1.2
General Description
The high-performance LP1072 baseband processor integrates the IEEE 802.11a/b/g PHY and full MAC
functionality with the industry’s lowest power consumption compared to any baseband processor in the
market.
The LP1072 was designed to target embedded devices and small form factor WLAN devices. Its support
for SDIO and CompactFlash+ host interfaces combined with its ultra low power consumption and small
size make it the optimal solution for mobile devices. It has been designed with a generic RF interface that
lets it interface with virtually any RF components in the market. It has been fully tested to interface with
RF solutions from Maxim and Airoha, thus providing terminal manufacturers with added flexibility in
selecting the most appropriate RF parts based on their application and form factor.
The LP1072’s integrated ADC and DAC reduce the terminal manufacturers' bill of material and overall
system cost. The integrated internal memory eliminates the need for external MAC memory, further
reducing cost and saving valuable board space for small form factor devices.
The LP1072 also provides the highest level of WLAN security by fully supporting WPA and AES.
1.3
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Features
Full compliance with 802.11a/b/g
Ultra low power consumption, maximizing battery life and minimizing heat dissipation
Ultra small package: 13.0 x 13.0 x 1.0 (max) mm
Fully embedded ARM7TDMI™ microprocessor for no load on the host processor, leading to
maximum flexibility in supporting different host platforms
Implementations of 802.11e Draft, for support of Quality of Service (QoS) real-time applications
Support for WPA and AES, for enhanced security
Automatic power management to reduce power consumption
On-chip ADC and DAC to reduce system BOM and save on board area
On-Chip PLL for clock generation
On-chip ROM/RAM eliminating the need for external MAC memory
Direct memory access (DMA) to reduce CPU utilization
High throughput achieved using DMA
Support of SDIO host interface
Support of CompactFlash host interface
Support of 16-bit SRAM emulation mode
Serial EEPROM interface for initialization and device booting
Eight General Purpose I/O (GPIO) pins for added flexibility
UART interface to support diagnostic tools and general data transfer
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PRELIMINARY
Specifications
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•
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•
2
JTAG Interface for testing and debugging
Hardware engines for WEP, TKIP and AES support for less processor load
Supports Direct Conversion (Zero-IF) radio architecture, saving RF components thus reducing
BOM cost and simplifying board layout
Generic RF interface that lets it work with virtually an WLAN RF components. Currently fully
tested with RF from Maxim and Airoha.
Total PHY flexibility in meeting customer requirements by providing software-controlled trade-off
between competing performance metrics
Specifications
Table 1. Specifications
Feature
Details
Network Standard Support
IEEE 802.11 a/b/g
Network Architectures
Infrastructure, AdHoc
Data Rates
802.11 a/g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
802.11b:1, 2, 5.5, 11 Mbps
Modulation Techniques
BPSK, QPSK, 16QAM, 64QAM, CCK, OFDM, DSSS
Security
40- and 128-bit WEP, TKIP, WPA, AES
Receiver Sensitivity
(Using Maxim RF)
802.11g 802.11b
6 Mbps:–91.0 dBm1Mbps:–97.1 dBm
9 Mbps: –89.7 dBm2 Mbps: –93.6 dBm
12 Mbps: –87.3 dBm5.5Mbps: –92.2 dBm
18 Mbps: –85.8 dBm11Mbps: –89.5 dBm
24 Mbps:–81.4 dBm
36 Mbps: –78.3 dBm
48 Mbps: –74.8 dBm
54Mbps: –73.0 dBm
Power Consumption
Receive:150 mW avg (@54Mbps)
Listen: 132 mW
Sleep:Less than1 mW
Supply Voltage
I/O: 3.3 ± 0.3 Vdc
Core:1.8 ± 5% Vdc
Operating Temperature
0 oC to +70 oC; < 95% humidity
Host Interfaces
SDIO; compliant with SDIO Card Specifications, Version 1.00
CompactFlash+; compliant with CF+ and Compact Flash Specs Rev 2.0
16-bit SRAM emulation mode
Other Interfaces
JTAG
8 GPIO pins
One UART
Serial EEPROM
Operating System Support
Microsoft Windows CE.net 3.0, 4.2
Microsoft Pocket PC 2002, 2003
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
3
PRELIMINARY
Functional Description
Table 1. Specifications (continued)
3
Feature
Details
Packaging Options
200-pin VFBGA, 13.0 x 13.0 x 1.0(max) mm
Semiconductor Technology
0.18 micron
RF Support
Maxim, Airoha
Certification
Wi-Fi® (incl. WPA), WQHL, FCC Part 15
Functional Description
Figure 1 is a functional block diagram of the LP1072.
LP1072 Chip Boundary
ARM7TDMI
MAC Subsystem
Protocol
Accelerator
Subsystem
Memory
Controller
AHB
ARM
Subsystem
Shared
Memory
On-Chip
RAM/ROM
AHB
ARM
Interface
Bridge
Watchdog
Timer
JTAG
Interrupt
Controller
EEPROM
Interface
APB+
UART
WEP
Engine
Generic
Host
Interface
SDIO
Registers
GPIO
Clock
Control
RMB
Registers
Clock
Gating
Shared
Memory
Controller
DMA
AHB
AES
Engine
802.11
Protocol
Accelerator
AFE
PHY
Subsystem
AFE
Control
ARM
Interface
I/Q ADC
I/Q DAC
MAC-PHY
Interface
Aux ADC
WBSPTM
Aux DAC
Host
Interface
Clock Select
Logic
RSSI
ADC
PLL
CLKIN
(From TCXO)
Figure 1. Functional Block Diagram
3.1
Embedded Processor Subsystem
The embedded Processor Subsystem consists of the following:
• An embedded ARM7TDMI microprocessor running at 88 MHz
• An ARM™ Peripheral Subsystem accessed via an extended APB (APB+) bus
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PRELIMINARY
Functional Description
3.1.1
UART
The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of
up to 115.2 kbps.
3.1.2
JTAG
TBA
3.1.3
Serial EEPROM Interface
The LP1072 supports an external serial EEPROM for storing the boot loader, MAC address, calibration
data and any other vendor-specific data. The LP1072 supports serial EEPROMs of sizes from 8 Kbit
(organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial
EEPROMs from the following vendors have been tested and verified to work with the LP1072:
• ATMEL (http:/www.atmel.com)
• ST Microelectronics (http://www.st.com)
• Microchip Technology (http://www.microchip.com)
• Catalyst Semiconductor (http://www.catsemi.com)
• Integrated Silicon Solutions, Inc. (http://www.issi.com)
The EEPROM is supported through GPIOs. There is no dedicated hardware to support either I2C or SPI
serial EEPROMs.
The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V.
3.1.4
GPIO
To support vendor-specific needs, the LP1072 provides eight bi-directional General Purpose Input Output
(GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset,
the GPIOs default as inputs, i.e. output drivers enables will be inactive.
3.1.5
RMB Registers
This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It
also defines controls for memory address re-mapping.
3.1.6
Watchdog
TBA
3.1.7
Interrupt Controller
TBA
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PRELIMINARY
Functional Description
3.1.8
SDIO Registers
TBA
3.1.9
Clock Control
TBA
3.1.10
Clock Gating
This block contains all the control logic required to gate individual sub-block clocks.
3.2
3.2.1
Media Access Control (MAC) Subsystem
Protocol Accelerator Subsystem (PAS)
The main function of the Protocol Accelerator Subsystem is to provide hardware acceleration functions
for the MAC Software to perform the time critical aspects of the 802.11 protocol.
The PAS contains the following:
• Shared Memory Controller – provided arbitrated access to the shared memory (MAC memory)
• WEP Hardware Engine
• AES Hardware Engine
• 802.11 Protocol Accelerator – for support of time-critical MAC functions
• Generic Host Interface
3.2.2
AES Block
The contents of the AES block are:
• AES encryption/decryption core that performs AES encryption/decryption of a 128bit block.
• Offset Codebook (OCB) mode encipher/decipher wrapper that performs OCB mode key
generation for the AES core.
• DMA controller and Shared Memory Interface that controls the reading/writing of data blocks
from/to the PAS shared memory controller.
• Control Registers, used to configure the operation of the AES block.
3.2.3
WEP Block
TBA
3.3
PHY Subsystem
TBA
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Functional Description
3.4
Analog Front End (AFE)
The Analog Front End (AFE) block consists of three Analog-to-Digital Converters (ADCs) and two
Digital-to-Analog Converters (DACs) as given in Table 2.
Table 2. AFE Components
Component
Description
Resolution
Clock
I/Q ADC
A 2-channel ADC whose digital output serves as input to digital baseband
and whose input is the differential signal from the RF (RX mode).
8-bit
22 Msps
I/Q DAC
A 2-channel DAC whose digital input is from baseband and output is a
differential signal for the RF (TX mode).
8-bit
44 Msps
RSSI ADC
A single ended, single channel ADC
6-bit
10 Msps
Auxiliary ADC
A single ended, single channel ADC
8-bit
1 Msps
Auxiliary DAC
A single ended, single channel DAC
8-bit
20 Msps
3.4.1
I/Q ADC
I/Q ADC specifications are shown in Table 3.
Table 3. I/Q ADC Specifications
Parameter
Condition
Min
Typ
Max
Units
Resolution
—
—
8
—
bit
Maximum Sampling Frequency
—
22
—
—
MHz
Signal Bandwidth
—
—
11
—
MHz
Fixed capacitance
—
1
—
pF
Switched capacitance @Fs
—
1
—
pF
Input impedance
Latency
—
—
4
—
cycles
Integral Nonlinearity (INL)
—
—
±1.0
—
LSB
Differential Nonlinearity (DNL)
—
—
± 0.5
—
LSB
Fin= 1MHz
—
-48.5
—
dB
Fin= 10MHz
—
-47
—
dB
Fin= 1MHz
—
48.5
—
dB
Fin= 10MHz
—
47
—
dB
Fin= 1MHz
—
7.2
—
bit
Fin= 10MHz
—
7.0
—
bit
Gain
—
0.2
—
dB
Phase
—
0.5
—
Degree
-1
—
+1
LSB
Total Harmonic Distortion (THD)
SNR
ENOB
Channel-to-Channel mismatch
DC offset after calibration
—
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7
PRELIMINARY
Functional Description
Table 3. I/Q ADC Specifications (continued)
Parameter
Min
Typ
Max
Units
From Shutdown
—
—
1
ms
From Standby
—
—
10
µs
Condition
Min
Typ
Max
Units
Resolution
—
—
8
—
bit
Maximum Update rate
—
44
—
—
MHz
3dB Signal Bandwidth
—
—
11
—
MHz
Output common-mode voltage
—
0.7
Vcmo1
1.5
V
Load
—
10
—
—
Kohm
—
—
—
5
pF
Integral Nonlinearity (INL)
—
—
±1.0
—
LSB
Differential Nonlinearity (DNL)
—
—
± 0.5
—
LSB
Fin= 1MHz
—
-48.5
—
dB
Fin= 10MHz
—
-47
—
dB
Fin= 1MHz
—
48.5
—
dB
Fin= 10MHz
—
47
—
dB
Fin= 1MHz
—
7.2
—
bit
Fin= 10MHz
—
7.0
—
bit
Gain
—
0.2
—
dB
Phase
—
0.5
—
Degree
-1
—
+1
LSB
From Shutdown
—
—
10
µs
From Standby
—
—
2
µs
Wake-up time
3.4.2
Condition
I/Q DAC
I/Q DAC specifications are shown in Table 4.
Table 4. I/Q DAC
Parameter
Total Harmonic Distortion (THD)
SNR
ENOB
Channel-to-Channel mismatch
DC offset after calibration
Wake-up time
1
—
See Analog input pin for definition of I/Q DAC output common-mode level.
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PRELIMINARY
Functional Description
3.4.3
RSSI ADC
RSSI ADC specifications are shown in Table 5.
Table 5. RSSI ADC Specifications
Parameter
Condition
Min
Typ
Max
Units
Resolution
—
—
6
—
bit
Maximum Sampling Frequency
—
10
—
6
MHz
Input Voltage Range
—
0
—
6
V
Latency
—
—
3
—
cycles
Integral Nonlinearity (INL)
—
—
±1.0
—
LSB
Differential Nonlinearity (DNL)
—
—
± 0.5
—
LSB
—
5.5
—
bit
ENOB
3.4.4
Fin= 100 kHz
Aux ADC
Aux ADC specifications are shown in Table 6.
Table 6. Aux ADC Specifications
Parameter
Condition
Min
Typ
Max
Units
Resolution
—
—
8
—
bit
Maximum Sampling Rate
—
1
—
—
MHz
Input Voltage Range
—
0
—
AVdd
V
Latency
—
—
9
—
cycles
Integral Nonlinearity (INL)
—
—
±1.0
—
LSB
Differential Nonlinearity (DNL)
—
—
± 0.5
—
LSB
ENOB
Fin= 100 kHz
—
7.2
—
bit
Channel-to-Channel mismatch
Gain
—
0.2
—
dB
Phase
—
0.5
—
Degree
From Shutdown
—
—
10
µs
From Standby
—
—
2
µs
Wake-up time
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PRELIMINARY
LP1072 Interfaces
3.4.5
Aux DAC
AUX DAC specifications are shown in Table 7.
Table 7. Aux DAC Specifications
Parameter
Condition
Min
Typ
Max
Units
—
—
8
—
bit
—
20
—
—
MHz
—
0.1
—
2.4
V
—
5
—
—
kOhm
—
—
—
10
pF
Propagation delay (tpd)
—
—
5
—
ns
Settling time (ts)
—
—
80
—
ns
Integral Nonlinearity (INL)
—
—
±1.0
—
LSB
Differential Nonlinearity (DNL)
—
—
± 0.5
—
LSB
Resolution
Maximum Update rate
Output voltage for full scale input
1
Load
ENOB
Fin = 1 MHz
—
7.2
—
bit
Wake-up time
From Shutdown
—
—
10
µs
From Standby
—
—
2
µs
1
Due to saturation of the output buffer, INL and DNL are not applicable for output voltages below 200 mV. Output is monotonic
above 0.1 V.
4
4.1
LP1072 Interfaces
SDIO Host Interface
The LP1072 supports SDIO Card Specifications, Version 1.00 (http//www.sdcard.org). The LP1072 SDIO
host interface supports the I/O mode of the SD Card Specifications.
4.1.1
SDIO Supported Features
The features supported by the LP1072 SDIO host interface are:
• SD 1-Bit Mode
• SD 4-Bit Mode
• Low Speed
• Full Speed (25 MHz)
• Interrupt
• CMD52 during Data Transfer
• CMD53 Multi Block Transfer
• Interrupt during 4-bit Multiple Block Data Transfer
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PRELIMINARY
LP1072 Interfaces
•
4.1.2
Combo Card (I/O mode only)
SDIO Function 0/1
For Function 0 registers descriptions, refer to SDIO Card Specification. For Function 1, the SDIO registers
occupy a 128 Kbyte space as defined in the SDIO specification. Figure 2 illustrates SDIO Function 1
128 Kbyte Memory Map and Table 8 details its registers.
Bit7
0x0000
Bit0
0x0015
Reserved
Reserved
0x0016 Reserved
0x0017 ARM to Host Interrupt
Enable register 0
0x0018 ARM to Host Interrupt
Enable register 1
0x001C SDIO Mailbox semaphore 0
0x001D SDIO Mailbox semaphore 1
0x001E SDIO Mailbox semaphore 2
0x0020
0x000E Watchdog Reset Register
0x000F SDIO Host to Device
Interrupt Register 0
0x0010
0x0011
0x1FFF
0x2000
2 KByte Mailbox
space
RAM0
RAM1
Reserved
RAM2
0x27FF
Reserved
0x2800
0x0012
Reserved
0x0013
ARM to Host Interrupt
Source register 0
ARM to Host Interrupt
Source register 1
0x0014
Reserved
0x200E
0x200F
0x23FF
0x2400
Reserved
0x3FFF
0x4000
8Kbyte Internal Memory
0x5FFF
Figure 2. SDIO Function 1 128 Kbyte Memory Map
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PRELIMINARY
LP1072 Interfaces
Table 8. SDIO Function 1 Registers
Bit
ARM
Access
HOST
Access
Reset
This is a read only bit that when ‘1’ indicates that
the LP1072 ASIC has had a watchdog reset
occur.
R
R
0
—
—
—
—
Each bit in this register is 1 of 8 ARM interrupt
requests from the SDIO Host to the device ARM.
The Host should request an interrupt by writing a
“1” to the corresponding bit in this register. The
register will be read as a “1” until the ARM clears
the register. Once the ARM has cleared the
register then the corresponding bit will be read as
“0” again.
—
RW
0’s
—
RW
0’s
This register contains the interrupt pending status
of the SDIO Host semaphore 0-2 host granted
indication. When the Host requests a semaphore
the corresponding interrupt will be triggered when
the host has been granted the interrupt. Bit 0 is
semaphore 0; bit 1 is semaphore 1; and bit 2 is
semaphore 2. Each bit in this register is ANDed
with the corresponding ARM to SDIO Host
Interrupt enable register. The ANDed bits are then
ORed together to generate a single SDIO Host
interrupt in the cccr register space. To clear a
particular interrupt bit the SDIO Host should write
a “1” to that particular bit in this register.
-⎯
RW
0’s
—
-⎯
-⎯
-⎯
Name
Description
Watchdog Status Register (offset 0x000E)
0
7:1
Wdog_reset
Reserved
SDIO Host to Device Interrupt request register 0 (0x000F)
7:0
Write_sdio_arm_int
Device to SDIO Host Interrupt Source register 0 (0x0013)
7:0
Arm_to_sdio_int_clr[7:0] for
writes.
Arm_to_sdio_int_src[7:0] for
reads.
This register contains the interrupt pending status
of the SDIO Host interrupt from the device. The
device is capable of generating up to 8 individual
requests. Each bit in this register is ANDed with
the corresponding ARM to SDIO Host Interrupt
enable register. The ANDed bits are then ORed
together to generate a single SDIO Host interrupt
in the cccr register space. To clear a particular
interrupt bit the SDIO Host should write a “1” to
that particular bit in this register.
Device to SDIO Host Interrupt Source register 1 (0x0014)
2:0
Arm_to_sdio_int_clr[10:8] for
writes.
Arm_to_sdio_int_src[10:8]
for reads.
7:3
Reserved
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LP1072 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit
ARM
Access
HOST
Access
Reset
-⎯
RW
0’s
Individual bit enables for each of the device to host
interrupt source bits. Setting the corresponding bit
to a “1” enables the interrupt; “0” disables the
interrupt. The SDIO Host can disable all interrupts
by disabling the main SDIO host interrupt in the
CCCR register.
Bit 0 is enable for semaphore 0 granted; bit 1 is
semaphore 1; and bit 2 is semaphore 2.
-⎯
RW
0’s
Reserved
-⎯
-⎯
-⎯
2 bit semaphore register to control whether the
host or the device has access to the shared
mailbox ram 0. The host should write a “01” to this
register to request the shared ram 0. After writing
“01” the host should read this register. If the value
is “01” then the host owns access to the mailbox.
If the value read is “11” then the device owns
access to the mailbox. When the host is done
utilizing the mailbox then it should release
ownership of the mailbox by writing “00” to this
register.
RW
RW
0’s
-⎯
-⎯
-⎯
-⎯
2 bit semaphore register to control whether the
host or the device has access to the shared
mailbox ram 1. The host should write a “01” to this
register to request the shared ram 1. After writing
“01” the host should read this register. If the value
is “01” then the host owns access to the mailbox.
If the value read is “11” then the device owns
access to the mailbox. When the host is done
utilizing the mailbox then it should release
ownership of the mailbox by writing “00” to this
register.
RW
RW
0’s
-⎯
-⎯
-⎯
-⎯
Name
Description
Device to SDIO Host Interrupt Enable 0 (0x0017)
7:0
Arm_to_sdio_inte_en[7:0]
Individual bit enables for each of the device to host
interrupt source bits. Setting the corresponding bit
to a “1” enables the interrupt; “0” disables the
interrupt. The SDIO Host can disable all interrupts
by disabling the main SDIO host interrupt in the
CCCR register.
Device to SDIO Host Interrupt Enable 1 (0x0018)
2:0
Arm_to_sdio_inte_en[10:8]
7:3
-⎯
SDIO Host Mailbox Semaphore 0 Register (offset 0x001C)
1:0
Sdio_mbxp_0_sema
7:2
Reserved
SDIO Host Mailbox Semaphore 1 Register (offset 0x001D)
1:0
Sdio_mbxp_1_sema
7:2
Reserved
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PRELIMINARY
LP1072 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit
ARM
Access
HOST
Access
Reset
2 bit semaphore register to control whether the
host or the device has access to the shared
mailbox ram 2. The host should write a “01” to this
register to request the shared ram 2. After writing
“01” the host should read this register. If the value
is “01” then the host owns access to the mailbox.
If the value read is “11” then the device owns
access to the mailbox. When the host is done
utilizing the mailbox then it should release
ownership of the mailbox by writing “00” to this
register.
RW
RW
0’s
-⎯
-⎯
-⎯
-⎯
Shared SDIO Mailbox. Both the ARM and Host
can use the mailbox for message exchange
between the SDIO device and the SDIO Host.
Prior to accessing the SDIO Mailbox the Host
should request and be granted the mailbox via the
mailbox semaphore 1 register described above.
Once the Host has been granted access to the
mailbox it may read/write the mailbox however it
likes. If the Host has not been granted access to
the mailbox it will not be able to read or write the
mailbox. Once the Host is finished with the
mailbox it should release control of the mailbox as
described in the mailbox semaphore 1 register.
RW
RW
-⎯
RW
RW
-⎯
Name
Description
SDIO Host Mailbox Semaphore 2 Register (offset 0x001E)
1:0
Sdio_mbxp_2_sema
7:2
Reserved
992 byte Mailbox RAM 1 (offset 0x200F to 0x23FF)
7:0
Mbox_rdata_1[15:0]
1 Kbyte Mailbox RAM 2 (offset 0x2400 to 0x27FF)
7:0
Mbox_rdata_2[15:0]
Shared SDIO Mailbox. Both the ARM and Host
can use the mailbox for message exchange
between the SDIO device and the SDIO Host.
Prior to accessing the SDIO Mailbox the Host
should request and be granted the mailbox via the
mailbox semaphore 2 register described above.
Once the Host has been granted access to the
mailbox it may read/write the mailbox however it
likes. If the Host has not been granted access to
the mailbox it will not be able to read or write the
mailbox. Once the Host is finished with the
mailbox it should release control of the mailbox as
described in the mailbox semaphore 2 register.
LP1072 Advance Information, Rev. 0.3
14
Freescale Semiconductor
PRELIMINARY
LP1072 Interfaces
Table 8. SDIO Function 1 Registers (continued)
Bit
Name
Description
ARM
Access
HOST
Access
Reset
-⎯
RW
-⎯
8 Kbyte Internal Memory Buffer RAM (offset 0x4000 to 0x5FFF)
7:0
4.2
Imem_rdat[15:0]
This is an internal memory buffer for specific use
by the SDIO device. Data is read or written to this
memory via SDIO cmd 53 reads or writes. Then,
the SDIO DMA controller is used to move the data
from the internal memory buffer to/from shared
memory under device (ARM) control.
CompactFlash+ Host Interface
The LP1072 supports CF+ and Compact Flash Specification Revision 2.0. The LP1072 CF host interface
supports both the I/O and storage modes of the Compact Flash Specifications. The interface allows an
external host (or an host DMA) to have 8-bit or 16-bit memory and I/O mode access to the device
according to the Compact Flash Specification 2.0.
4.3
SRAM Emulation Mode
The SRAM emulation mode provides an alternative write/read access to the device without using the CF
port (or SDIO) using generic SRAM access cycles. It supports 16-bit memory interface.
This mode is host-dependent and can be enabled and tested for a specific host.
4.4
4.4.1
•
1.
2.
3.
•
•
•
•
•
•
•
RF Interface
Serial Programmable Interface (SPI)
The SPI is composed of 3 signals:
RF_SIF_0_SCLK (serial clock)
RF_SIF_1_CS_N (chip select)
RF_SIF_2_DIN (data input)
The serial information is sent to the RF transceiver in 18 bit bursts framed by chip select. The 18
bits comprises of leading 14 (or less) data bits and trailing 4 address bits
Programming clock edges are ignored until chip select goes active low.
All bits are shifted in on the rising edge of the clock and latched in when chip select returns inactive
high. (permissible for the clock in either state)
The interface can be programmed in any operating mode.
Serial information is clocked in with the most significant bit (MSB) first.
The address bits for the internal registers are decoded on the rising edge of chip select.
The rising edge of chip select initiates an internal parallel load pulse that latches the last 18-bit
serially shifted-in data into the internal register.
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
15
PRELIMINARY
Timers/Reset
5
Timers/Reset
The TCXO generates the 40MHz RFIC 800 mV clipped sine wave reference clock.
The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO
reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL
synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM,
PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the
TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock.
The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock
reference to be driven by an external signal.
Figure 3 illustrates the high level clocking of the LP1072 with the associated pins.
Chip
Boundary
PLL_BYPAS
S
40 MHz
PLL_BYPASS_CLK
88 MHz
TCXO_BYPASS
Clock
Control
Cuircuits
TCXO_BYPASS_CLK
TCXO
40 MHz
PLL
ARM
44 MHz
20 MHz
AFE
22 MHz
FAST_CLK_PWR
XTAL_BYPASS
XTAL_BYPASS_CLK
XTAL
32 kHz
32 kHz
Figure 3. LP1072 Clocks
5.1
System Clock
The LP1072 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal
oscillator (TCXO) running at 40MHz with a frequency resolution of ± 20 ppm or better.
5.2
PLL Block
PLL Bypass
5.3
Low Frequency Clock
The LP1072 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
LP1072 Advance Information, Rev. 0.3
16
Freescale Semiconductor
PRELIMINARY
Pinout and Footprint
6
6.1
Pinout and Footprint
Pinout
S
Table 9. Pin Description
Pad Name
Pad Type
Direction
Description
Pin
VDD_IO
pvdd2dgz
N/A
3.3V I/O power pad (22 mA per pad max current)
K3
VDD_IO
pvdd2dgz
N/A
3.3V I/O power pad (22 mA per pad max current)
P3
VDD_IO
pvdd2dgz
N/A
3.3V I/O power pad (22 mA per pad max current)
M6
VDD_IO
pvdd2dgz
N/A
3.3V I/O power pad (22 mA per pad max current)
N11
VDD_IO
pvdd2dgz
N/A
3.3V I/O power pad (22 mA per pad max current)
R14
VDD_IO
pvdd2dgz
N/A
3.3V I/O power pad (22 mA per pad max current)
E12
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
K5
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
L5
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
L6
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
L8
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
M11
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
K11
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
G11
VSS_IO
pvss2dgz
N/A
I/O ground pad (94mA max current)
F11
VDD_CORE
pvdd1dgz
N/A
1.8V core power pad (31 mA per pad max current)
G1
VDD_CORE
pvdd1dgz
N/A
1.8V core power pad (31 mA per pad max current)
R8
VDD_CORE
pvdd1dgz
N/A
1.8V core power pad (31 mA per pad max current)
M10
VDD_CORE
pvdd1dgz
N/A
1.8V core power pad (31 mA per pad max current)
K15
VDD_CORE
pvdd1dgz
N/A
1.8V core power pad (31 mA per pad max current)
B15
VSS_CORE
pvss1dgz
N/A
Core ground pad (25mA per pad max current)
H5
VSS_CORE
pvss1dgz
N/A
Core ground pad (25mA per pad max current)
L7
VSS_CORE
pvss1dgz
N/A
Core ground pad (25mA per pad max current)
L9
VSS_CORE
pvss1dgz
N/A
Core ground pad (25mA per pad max current)
J11
VSS_CORE
pvss1dgz
N/A
Core ground pad (25mA per pad max current)
E11
VSS_CORE
pvss1dgz
N/A
Core ground pad (25mA per pad max current)
E9
ARM_DBGEN
pdidgz
Input
ARM7TDMI Icebreaker debug enable pin
F3
EMBEDDED_RESET_N
pdisdgz
Input
Embedded board reset
F15
PLL_BYPASS
pdidgz
Input
Bypass the internal PLL and use PLL_BYPASS_CLK
D10
PLL_BYPASS_CLK
pdidgz
Input
PLL bypass clock input
A11
Power and Ground Pads
Clocks and Resets and Mode
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
17
PRELIMINARY
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
Pad Type
Direction
AVDD_PLL
pdiana2p
N/A
Analog 1.8 volt
C1
AVSS_PLL
pdiana2p
N/A
Analog ground
D1
pvdd3p
N/A
3.3 volt power for ESD Diodes
E3
DVDD_PLL
pdiana2p
N/A
1.8 volt digital power for PLL
E1
DVSS_PLL
pdiana2p
N/A
1.8 volt digital ground for PLL
E2
TXCO_BYPASS
pdidgz
Input
Bypass the TCXO and use the TCXO_BYPASS_CLK
C11
TXCO_BYPASS_CLK
pdidgz
Input
TCXO bypass clock
D11
XTAL_BYPASS
pdidgz
Input
Bypass XTAL osc and use XTAL_BYPASS_CLK
D15
XTAL_BYPASS_CLK
pdidgz
Input
XTAL bypass clock
D13
FAST_CLK_POWER
pdo02cdg
Output
Enable the TCXO
C10
XTAL_32K_XIN
pdxoe4dg
Analog
32kHz crystal (NOTE: Must be placed next to PVDD1DGZ.)
C15
Analog
32kHz crystal
C14
TAVDDPOWER
XTAL_32K_XOUT
Description
Pin
RESET_N
pdisdgz
Input
Chip Reset
E13
CHIP_MODE0
pdidgz
Input
G2
CHIP_MODE1
pdidgz
Input
Chip Mode Select
0000 = SDIO normal operation
CHIP_MODE2
pdidgz
Input
CHIP_MODE3
pdidgz
Input
JTAG_RESET
pdudgz
Input
Tap reset
P8
JTAG_CLOCK
pdisdgz
Input
Tap clock
M8
JTAG_DI
pdudgz
Input
Tap data in
R10
JTAG_DO
pdo02cdg
Output
Tap data out
N10
pdudgz
Input
Tap Mode
R11
ARM_GPIO0
pdb04dgz
Bi-dir
General Purpose I/O
R1
ARM_GPIO1
pdb04dgz
Bi-dir
General Purpose I/O
N3
ARM_GPIO2
pdb04dgz
Bi-dir
General Purpose I/O
R3
ARM_GPIO3
pdb04dgz
Bi-dir
General Purpose I/O
N4
ARM_GPIO4
pdb04dgz
Bi-dir
General Purpose I/O
P4
ARM_GPIO5
pdb04dgz
Bi-dir
General Purpose I/O
N5
ARM_GPIO6
pdb04dgz
Bi-dir
General Purpose I/O
P5
ARM_GPIO7
pdb04dgz
Bi-dir
General Purpose I/O
R5
ARM_UART_0_DI
pdb04dgz
Input
UART input data
N7
ARM_UART_0_DO
pdb04dgz
Output
UART output data
P6
ARM_EEPROM_DAT_GPIO
pdb04dgz
Bi-dir
General Purpose I/O dedicated for EEPROM
M7
J1
0001 = CF+ normal operation
H3
All other modes are reserved
K1
JTAG
JTAG_MODE
ARM Sub-system Signals
LP1072 Advance Information, Rev. 0.3
18
Freescale Semiconductor
PRELIMINARY
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
Pad Type
Direction
ARM_EEPROM_CLK_GPIO
pdb04dgz
Bi-dir
Description
General Purpose I/O dedicated for EEPROM
Pin
N8
SDIO Signals (other signals on interface are 1 Vdd and 2 Vss pins)
CD/DAT3 (connector pin 1)
pduw04dgz
Bi-dir
Card detect/data 3
H4
DAT[2] (connector pin 9)
pdu04dgz
Bi-dir
Data 2
K2
DAT[1] (connector pin 8)
pdu04dgz
Bi-dir
Data 1/interrupt
J4
DAT[0] (connector pin 7)
pdu04dgz
Bi-dir
Data 0/busy indication
M1
CMD (connector pin 2)
pdu04dgz
Bi-dir
Command/response
N1
CLK (connector pin 5)
pdisdgz
Input
Clock
N2
CF_D0
pdb04dgz
Bi-dir
CompactFlash data
F2
CF_D1
pdb04dgz
Bi-dir
CompactFlash data
G4
CF_D2
pdb04dgz
Bi-dir
CompactFlash data
G3
CF_D3
pdb04dgz
Bi-dir
CompactFlash data
H1
CF_D4
pdb04dgz
Bi-dir
CompactFlash data
J2
CF_D5
pdb04dgz
Bi-dir
CompactFlash data
H2
CF_D6
pdb04dgz
Bi-dir
CompactFlash data
J3
CF_D7
pdb04dgz
Bi-dir
CompactFlash data
L1
CF_D8
pdb04dgz
Bi-dir
CompactFlash data
K4
CF_D9
pdb04dgz
Bi-dir
CompactFlash data
L2
CF_D10
pdb04dgz
Bi-dir
CompactFlash data
L3
CF_D11
pdb04dgz
Bi-dir
CompactFlash data
M2
CF_D12
pdb04dgz
Bi-dir
CompactFlash data
L4
CF_D13
pdb04dgz
Bi-dir
CompactFlash data
M3
CF_D14
pdb04dgz
Bi-dir
CompactFlash data
P1
CF_D15
pdb04dgz
Bi-dir
CompactFlash data
P2
CF_CE1_N
pdusdgz
Input
CF Card enable even address (8 bit mode)
R2
CF_CE2_N
pdusdgz
Input
Chip Enable odd address (8 bit mode)
M4
CF_A0
pdb04dgz
Bi-dir
CompactFlash address
R4
CF_A1
pdb04dgz
Bi-dir
CompactFlash address
M5
CF_A2
pdb04dgz
Bi-dir
CompactFlash address
N6
CF_A3
pdb04dgz
Bi-dir
CompactFlash address
R6
CF_A4
pdb04dgz
Bi-dir
CompactFlash address
R7
CF_A5
pdb04dgz
Bi-dir
CompactFlash address
P7
CF_A6
pdb04dgz
Bi-dir
CompactFlash address
R9
CF_A7
pdb04dgz
Bi-dir
CompactFlash address
N9
CF + (PC Card I/O Mode)
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
19
PRELIMINARY
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
Pad Type
Direction
CF_A8
pdb04dgz
Bi-dir
CompactFlash address
P9
CF_A9
pdb04dgz
Bi-dir
CompactFlash address
P10
CF_A10
pdb04dgz
Bi-dir
CompactFlash address
R13
CF_OE_N
pdusdgz
Input
CF common or attribute memory indication
N12
CF_IORD_N
pdusdgz
Input
I/O read in conjunction with reg and ce1/2
P12
CF_IOWR_N
pdusdgz
Input
I/O write in conjunction with reg and ce1/2
P13
CF_WE_N
pdusdgz
Input
Common or attribute memory write enable
R15
CF_IREQ_N
pdt04dgz
Output
I/O mode interrupt request (pulsed low or level sensitive)
N14
CF_RESET
pdudgz
Input
Reset
P15
CF_CD1_N
pdt04dgz
Output
Card detect
L13
CF_CD2_N
pdt04dgz
Output
Card detect
K12
CF_INPACK_N
pdt04dgz
Output
Decode indication (not widely implemented)
J12
CF_STSCHG_N
pdo04dgz
Output
Status Change
K14
pdusdgz
Input
Cycle indication
J14
AGND
pdiana2p
N/A
Analog ground Double bonded with Analog Reference
negative supply)
E6
AGNDIQADC
pdiana2p
N/A
Analog ground
E8
AGNDIQDAC
pdiana2p
N/A
Analog ground
D8
AVDD
pdiana2p
N/A
Analog 3.3 volt
A3
AVDDIQADC
pdiana2p
N/A
Analog 3.3 volt
D7
AVDDIQDAC
pdiana2p
N/A
Analog 3.3 volt
A9
VDDIQADC
pvdd3p
N/A
3.3 volt power for ESD Diodes
A4
VSSIQADC
pvss3p
N/A
3.3 volt ground for ESD Diodes
E7
VDDIQDAC
pvdd3p
N/A
3.3 volt power for ESD Diodes
D2
DGND
pvss1dgz
N/A
Digital Ground
B2
DVDD
pvdd1dgz
N/A
Digital 1.8 Volt
C2
IBIAS
pdiana2p
N/A
Pin for monitoring or bypassing bias current, flowing out of
the pin to agnd.
B3
VBG
pdiana2p
N/A
Voltage reference pin for decoupling (equal to 1.25V).
Connect 1uF(ceramic) + 100nF (ceramic) to agndref.
B5
VREFN
pdiana2p
Input
ADC Negative reference for decoupling
A5
VREFP
pdiana2p
Input
ADC Positive reference for decoupling
A7
AUXADCIN_0
pdiana2p
Input
Muxed analog input to auxiliary ADC bit 0
C5
AUXADCIN_1
pdiana2p
Input
Muxed analog input to auxiliary ADC bit 1
D5
AUXADCIN_2
pdiana2p
Input
Muxed analog input to auxiliary ADC bit 2
B4
CF_REG_N
Description
Pin
AFE Interface
LP1072 Advance Information, Rev. 0.3
20
Freescale Semiconductor
PRELIMINARY
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
Pad Type
Direction
Description
Pin
IADCINN
pdiana2p
Input
Negative input of I-ADC
A8
IADCINP
pdiana2p
Input
Positive input of I-ADC
B8
QADCINN
pdiana2p
Input
Negative input of Q-ADC
B6
QADCINP
pdiana2p
Input
Positive input of Q-ADC
C6
RSSIADCIN
pdiana2p
Input
RSSI ADC input
B1
VOCM
pdiana2p
Input
Input pin for definition of IQDAC output common -mode level
D9
AUXDACOUT
pdiana2p
Output
Auxiliary DAC output
C4
IDACOUTP
pdiana2p
Output
Positive output of I-DAC
B9
IDACOUTN
pdiana2p
Output
Negative output of I-DAC
C9
QDACOUTP
pdiana2p
Output
Positive output of Q-DAC
B10
QDACOUTN
pdiana2p
Output
Negative output of Q-DAC
A10
EXT_BIAS
pdiana2p
Input
External Bias for test
D4
AVDD_TCXO
pvdd3p
N/A
Analog 3.3 volt
F4
AVSS_TCXO
pvss3p
N/A
Analog ground
G5
pdiana2p
Input
TCXO reference clock input
F1
RF_ANALOG_LDO
pdb04dgz
Bi-dir
LDO enable for RF VCO power. Driven by PHY controller.
M9
RF_EN
pdb04dgz
Bi-dir
RF enable. Driven by PHY controller.
R12
RF_RXEN
pdb04dgz
Bi-dir
RF Rx enable. Driven by PHY controller.
P11
RF_TXEN
pdb04dgz
Bi-dir
RF Tx enable. Driven by PHY controller.
N13
RF_PAEN1
pdb04dgz
Bi-dir
RF PA enable 1. Driven by PHY controller.
P14
RF_PAEN2
pdb04dgz
Bi-dir
RF PA enable 2. Driven by PHY controller.
M13
RF_SPARE1
pdb04dgz
Bi-dir
RF spare 1 (not used). Driven by PHY controller.
L12
RF_SPARE2
pdb04dgz
Bi-dir
RF spare 2 (not used). Driven by PHY controller.
G13
RF_VGA6
pdb04dgz
Bi-dir
RF VGA setting. Driven by UWA.
M14
RF_VGA5
pdb04dgz
Bi-dir
RF VGA setting. Driven by UWA.
N15
RF_VGA4
pdb04dgz
Bi-dir
RF VGA setting. Driven by UWA.
M15
RF_VGA3
pdo02cdg
Output
RF VGA setting. Driven by UWA.
K13
RF_VGA2
pdo02cdg
Output
RF VGA setting. Driven by UWA.
L14
RF_VGA1
pdo02cdg
Output
RF VGA setting. Driven by UWA.
L15
RF_VGA0
pdo02cdg
Output
RF VGA setting. Driven by UWA.
J13
RF_RXHP
pdo02cdg
Output
RF Rx highpass filter setting. Driven by UWA.
H12
RF_ANTENNA_SEL
pdo02cdg
Output
RF antenna select. Driven by ARM.
H13
RF_ANTENNA_SEL_N
pdo02cdg
Output
RF antenna select. Driven by ARM.
J15
TCXO Squarer
CLKIN
RF Interface Signals
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
21
PRELIMINARY
Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
Pad Type
Direction
RF_SIF_2_DIN
pdo02cdg
Output
RF 3-wire serial interface. Driven by ARM.
G12
RF_SIF_1_CS_N
pdo02cdg
Output
RF 3-wire serial interface. Driven by ARM.
H14
RF_SIF_0_SCLK
pdo02cdg
Output
RF 3-wire serial interface. Driven by ARM.
G15
pdidgz
Input
RF lock detect. Read by ARM.
G14
RF_LOCK_DETECT
6.2
Description
Pin
Pad Descriptions
pdxoe4dg
32 kHz crystal pad (1 pad w/2 pad connections)
pdisdgz
Schmitt triggered input 5 Volt tolerant
pdidgz
5 Volt tolerant input pad
pdudgz
5 Volt tolerant input pad w/internal pullup
pdusdgz
Schmitt Trigger Input Pad, 5V-Tolerant w/pullup
pdddgz
Input Pad With Pulldown, 5-VT IO
pdo02cdg
CMOS 2 mA output
pdo04cdg
CMOS 4 mA output
pdb04dgz
CMOS 3 state output pad w/input (5 volt tolerant)
pdb02dgz
CMOS 3 state output pad w/input (5 volt tolerant)
pdu02sdgz
CMOS 3-State Output Pad with Schmitt Trigger Input and Pullup, 5V-Tolerant
pdd04dgz
CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant
pdd04dgz
CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant
pdd08dgz
CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant
pdt04dgz
CMOS 3-State Output Pad, 5V-Tolerant
pdu02dgz
CMOS 3-State Output Pad with Input and Pullup, 5V-Tolerant
pduw02dgz
3-State Output Pad with Input and Enable Controlled Pull-Up, 5V-Tolerant
pdiana2p
Low Frequency Analog I/O for use with power cut diodes (Note: It is recommended to utilize the
secondary ESD protection circuit: ESND on these pads.
LP1072 Advance Information, Rev. 0.3
22
Freescale Semiconductor
PRELIMINARY
Pinout and Footprint
6.3
Footprint
1
2
3
NC
NC
AVDD
PVDD3P VREFN
_2
B RSSIADC
IN
DGND
IBIAS
AUXADC
IN_2
C
AVDD_
PLL
DVDD
NC
D
AVSS_
PLL
PVDD3P
_1
NC
E
DVDD_
PLL
DVSS_ TAVDD PVSS3P
PLL
POWER
_1
F
CLKIN
CF_D_0
ARM_ AVDD_
DBGEN TCXO
G
VDD_
CORE
_1
CHIP_
MODE
_0
H CF_D_3
CF_D_5
J
A
4
6
7
NC
VREFP
QADCINN
NC
AUXDAC AUXADC QADCINP
OUT
IN_0
NC
EXT_
BIAS
5
VBG
AUXADC
IN_1
NC
AGND
AGND
13
14
15
IADCINN AVDDIQDAC QDACOUTN PLL_
RE_1
BYPASS SERVED
_CLK
8
NC
NC
NC
IADCINP IDACOUTP QDACOUTP
NC
IDACOUTN
10
11
12
RESERVED
NC
NC
NC
VDD_CORE
_5
FAST_CLK TCXO_
_POWER BYPASS
NC
NC
XTAL_
32K_
XOUT
XTAL_32K_
XIN
XTAL_
REBYPASS SERVED
_CLK
XTAL_
BYPASS
GND
VDD_IO_ RESET_N
RE6
SERVED
RESERVED
TAVSSP
OWER
GND
REREREEMBEDDED
SERVED SERVED SERVED _RESET_N
CF_D_2 CF_D_1
AVSS_
TCXO
GND
RF_SIF_
2_DIN
CHIP_ SD_DAT
MODE_
_3
2
GND
GND
RF_
RXHP
CHIP_
MODE
_1
CF_D_4 CF_D_6 SD_DAT
_1
GND
GND
CF_
RF_VGA_ CF_REG
RF_
INPACK_
0
_N
ANTENNA
N
_SEL_N
K
CHIP_
MODE
_3
SD_DAT_ VDD_IO CF_D_8
2
_1
GND
GND
CF_CD2_ RF_VGA_
CF_
N
3
STSCHG
_N
L
CF_D_7
CF_D_9 CF_D_ CF_D_12
10
GND
GND
AVDDIQADC AGNDIQ
DAC_1
9
PVSS3P_2
GND
M SD_DAT_ CF_D_11 CF_D_ CF_CE2 CF_A_1 VDD_IO_3
ARM_
0
13
_N
EEPROM_
DAT_GPIO
N SD_CMD SD_CLK
ARM_
ARM_
GPIO_1 GPIO_3
P CF_D_14 CF_D_15 VDD_IO ARM_
_2
GPIO_4
R
ARM_ CF_CE1_ ARM_ CF_A_0
GPIO_0
N
GPIO_2
AGNDIQ
ADC
VOCM
PLL_
BYPASS
GND
GND
TCXO_
REBYPASS SERVED
_CLK
GND
GND
GND
GND
JTAG_
CLOCK
RF_
ANALOG
_LDO
VDD_CORE
_3
GND
RF_
SPARE2
RF_
RF_SIF_
ANTENNA 1_CS_N
_SEL
RESERVED
VDD_
CORE_4
RF_
CF_CD1_ RF_VGA RF_VGA_1
SPARE1
N
_2
NC
RF_PAEN RF_VGA RF_VGA_4
2
_6
ARM_
GPIO_5
CF_A_2
ARM_
UART
_0_DI
ARM_
EEPROM
_CLK_
GPIO
CF_A_7
JTAG_DO
VDD_IO_ CF_OE_
4
N
RF_
TXEN
ARM_
GPIO
_6
ARM_
UART
_0_DO
CF_A_5
JTAG_
RESET
CF_A_8
CF_A_9
RF_RXE
CF_
N
IORD_N
CF_
IOWR_N
ARM_
GPIO_7
CF_A_3
CF_A_4
VDD_
CORE_2
CF_A_6
JTAG_DI
JTAG_
MODE
RF_
RF_SIF_0_
LOCK_
SCLK
DETECT
RF_EN
CF_IREQ RF_VGA_5
_N
RF_
PAEN1
CF_
RESET
CF_A_10 VDD_IO_ CF_WE_N
5
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
23
PRELIMINARY
DC Electrical Specifications
7
DC Electrical Specifications
7.1
Absolute Maximum Ratings
Table 10. Absolute Maximum Ratings
Parameter
Min
Max
Units
Supply Voltage (3.0 V)
-0.3
4.0
V
Supply Voltage (1.8 V)
-0.3
2.2
V
GND - 0.3
VDD + 0.3
V
DC Output Current
TBD
TBD
mA
Storage Temperature
TBD
TBD
o
Electrostatic Discharge Voltage
TBD
TBD
Input Voltage
C
V
Operating the LP1072 under conditions that exceed Absolute Maximum Ratings may result in permanent
damage to the device. Absolute maximum ratings are limiting values, and are considered individually,
while all other parameters are within their specified operating ranges.
7.2
Recommended Operating Conditions
Recommended operating conditions are shown in Table 11.
Table 11. Recommended Operating Conditions
Parameter
Symbol
Min
Max
Units
Supply I/O Voltage
VDD_IO
3.0
3.6
V
Supply Core Voltage
VDD_C
1.71
1.89
V
70
oC
Operating Temperature
TA
0
Thermal dissipation (for multi-layer PCB) is shown in Table 12.
Table 12. Thermal Dissipation (for multi-layer PCB)
# PCB Layers
1 (1s)
# PCB Vias
PCB Trace
Density
θJA (°C/W)
ΨJT
θJC
0 m/s
1 m/s
2 m/s
(°C/W)
(°C/W)
0
JEDEC
96.1
68.9
59.6
1.0
6.5
36
JEDEC
81.7
60.2
52.6
0.9
6.2
0
6%
66.9
51.3
45.8
0.7
6.0
2 (2s)
LP1072 Advance Information, Rev. 0.3
24
Freescale Semiconductor
PRELIMINARY
DC Electrical Specifications
7.3
DC Characteristics
DC characteristics are shown in Table 13.
Table 13. DC Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Units
Pre-driver Supply Voltage
VDD
—
1.62
1.8
1.98
V
I/O Supply Voltage
VD33
—
3.0
3.3
3.6
V
Low-level input voltage
VIL
—
-0.3
—
0.8
V
High-level input voltage
VIH
—
2.0
—
5.5
V
Threshold point
VT
—
1.46
1.58
1.75
V
Schmitt Trigger Low to High Thresh
VT+
Schmitt
1.47
1.50
1.50
V
Schmitt Trigger High to Low Thresh
VT-
Schmitt
0.90
0.94
0.96
V
VI =VD33 or 0V
-10
—
10
µA
VOH = VSS
-10
—
10
µA
VOL = VDD
-10
—
10
µA
Input Leakage Current
3-state leak current
II
IOZ
Output low voltage
VOL
IOL = 2,4,…, 24mA
—
—
0.4
V
Output high voltage
VOH
IOH =2,4,…, 24mA
2.4
—
—
V
Low Level Out Current @VOL=0.4V
IOL
2 mA
2.2
3.3
3.8
mA
4 mA
4.5
6.6
7.6
mA
8 mA
TBA
TBA
TBA
mA
12 mA
1
19.7
22.7
mA
16 mA
TBA
TBA
TBA
mA
24 mA
2
39.5
45.4
mA
2 mA
TBA
TBA
TBA
mA
4 mA
TBA
TBA
TBA
mA
8 mA
12.3
24.8
38
mA
12 mA
18.5
37.1
56.9
mA
16 mA
22.7
49.5
75.9
mA
24 mA
36.9
74.3
113.9
mA
High Level Out Current
@VOH=2.4V
IOH
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
25
PRELIMINARY
Timing Characteristics
8
8.1
8.1.1
Timing Characteristics
AFE Interface
I/Q ADC
Figure 4. Timing of the Pipelining Operation in I/Q ADC
8.1.2
I/Q DAC
Figure 5. Timing Diagram of the I/Q DAC Inputs and Outputs
LP1072 Advance Information, Rev. 0.3
26
Freescale Semiconductor
PRELIMINARY
Timing Characteristics
8.1.3
RSSI ADC
Figure 6. Timing of the RSSI ADC Pipelining Operation
Figure 7. Timing of the Aux ADC Successive Approximation Operation
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
27
PRELIMINARY
Timing Characteristics
8.1.4
Auxiliary DAC
Figure 8. Conversion Cycle in Normal Operation for Aux DAC
Table 14. Aux DAC Timing Parameters
Symbol
tpd
ts
Parameter
Min
Typ
Max
Units
Propagation delay
—
5
—
ns
Settling time
—
80
—
ns
LP1072 Advance Information, Rev. 0.3
28
Freescale Semiconductor
PRELIMINARY
Mechanical Dimensions
9
Mechanical Dimensions
The LP1072 is a 200-pin Very-thin Fine-pitch Ball Grid Array (VFBGA) package. All dimensions are mm.
Figure 9. LP1072 Package
10 Development Support
In addition to the LP1072 baseband and MAC, Freescale provides developers with reference designs,
development platform, software drivers, system development software, testing and debugging tools and a
full set of technical documentation that includes:
• User Guide
• Data Sheet
• Schematics
• Gerber Files
• Application Notes
Freescale also provides multi-interface reference designs to aid device manufacturers with today's
demanding time-to-market requirements.
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
29
PRELIMINARY
Appendix: Comparison of LP1071 and LP1072
11 Appendix: Comparison of LP1071 and LP1072
Table 15. Comparison of LP1071 and LP1072
Item
LP1071
Network Standard Support
LP1072
IEEE 802.11 a/b/g
Network Architectures
Infrastructure, AdHoc
Data Rates
802.11 a/g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
802.11b: 1, 2, 5.5, 11 Mbps
Modulation Techniques
BPSK, QPSK, 16QAM, 64QAM, CCK, OFDM, DSSS
Security
40- and 128-bit WEP, TKIP, WPA, AES
Receiver Sensitivity1
802.11g802.11b
6 Mbps:–91.0 dBm1 Mbps:–97.1 dBm
9 Mbps: –89.7 dBm2 Mbps:–93.6 dBm
12 Mbps: –87.3 dBm5.5Mbps:–92.2 dBm
18 Mbps: –85.8 dBm11Mbps:–89.5 dBm
24 Mbps: –81.4 dBm
36 Mbps: –78.3 dBm
48 Mbps: –74.8 dBm
54Mbps: –73.0 dBm
Power Consumption
Receive:150 mW avg (@54Mbps)
Listen:132 mW
Sleep:Less than 1 mW
Supply Voltage
I/O: 3.0 – 3.6 Vdc
Core:1.8 ± 5% Vdc
Operating Temperature
0 oC to +70 oC; < 95% humidity
Host Interface
SDIO
Other Interfaces
JTAG, 8 GPIOs, 1 UART, Serial / EEPROM
Operating System Support
Package
SDIO
CompactFlash Plus (CF+)
16-bit SRAM emulation mode
Microsoft Windows CE.net 3.0 and 4.2
Microsoft Pocket PC 2002, 2003
144-pin VFBGA, 9 x 9 x 1.0 mm
Semiconductor Technology
0.18 micron
RF Support
Reference Designs
Certification
1
200-pin VFBGA, 13 x 13 x 1.0 mm
Airoha, Maxim
SDIO
CF+
Wi-Fi (incl. WPA), WHQL, FCC Part 15
Using Maxim RF
LP1072 Advance Information, Rev. 0.3
30
Freescale Semiconductor
PRELIMINARY
Revision History
12 Revision History
This document’s updated format reflects that Freescale Semiconductor, Inc. acquired CommASIC on
October 20, 2005. Since the release of the previous version of this document (Rev. 0.2), the technical
content has not been updated.
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
31
PRELIMINARY
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Document Number: LP1072
Rev. 0.3
12/2005
PRELIMINARY