FREESCALE MC68HC08JB8AJDW

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Addendum
HC908JB8AD/D
Rev. 0, 4/2002
Freescale Semiconductor, Inc...
Addendum to
MC68HC908JB8
Technical Data
This addendum provides additional information to the
MC68HC908JB8 Technical Data, Rev. 2
(Motorola document number MC68HC908JB8/D),
MC68HC08JB8A
The MC68HC08JB8A is the ROM part equivalent to the MC68HC908JB8. The
entire MC68HC908JB8 data book apply to this ROM device, with exceptions
outlined in this addendum.
Table 1. Summary of MC68HC08JB8A and MC68HC908JB8 Differences
MC68HC08JB8A
MC68HC908JB8
Memory ($DC00–$FBFF)
8,192 bytes ROM
8,192 bytes FLASH
User vectors ($FFF0–$FFFF)
16 bytes ROM
16 bytes FLASH
Registers at $FE08 and $FF09
Not used;
locations are reserved.
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Monitor ROM
($FC00–$FDFF and $FE10–$FFDF)
$FC00–$FDFF: Not used.
$FE10–$FFDF: Used for
testing purposes only.
Used for testing and FLASH
programming/erasing.
OSC1 and OSC2 pins
VDD level (5V logic)
VREG level (3.3V logic)
MCU Block Diagram
Figure 1 shows the block diagram of the MC68HC08JB8A.
Memory Map
The MC68HC08JB8A has 8,192 bytes of user ROM from $DC00 to $FBFF, and
16 bytes of user ROM vectors from $FFF0 to $FFFF. On the MC68HC908JB8,
these memory locations are FLASH memory.
Figure 2 shows the memory map of the MC68HC08JB8A.
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OSC1
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VSS
VDD
IRQ
RST
VREG
(3.3 V)
(1), (3)
(1), (2)
(1) OSC2
(1)
ARITHMETIC/LOGIC
UNIT (ALU)
LS USB
TRANSCEIVER
PTE0/TCLK (3)
PTE1/TCH0 (3)
PTE2/TCH1 (3)
PTE3/D+ (3) (4) (5)
PTE4/D– (3) (4) (5)
PTD1–PTD0 (4) (6)
PTD7–PTD6 (4)
PTD5–PTD2 (4) (5)
PTC7–PTC0 (3)
:
PTA0/KBA0 (3)
PTA7/KBA7 (3)
PTB7–PTB0 (3)
Shaded blocks indicate differences to MC68HC908JB8
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pull-up device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
USB ENDPOINT 0, 1, 2
USB
MODULE
COMPUTER OPERATING PROPERLY
MODULE
POWER-ON RESET
MODULE
LOW VOLTAGE INHIBIT
MODULE
BREAK
MODULE
TIMER INTERFACE
MODULE
KEYBOARD INTERRUPT
MODULE
INTERNAL BUS
Figure 1. MC68HC08JB8A Block Diagram
INTERNAL VOLTAGE REGULATOR
POWER
IRQ
MODULE
SYSTEM INTEGRATION
MODULE
OSCILLATOR
USER ROM VECTORS — 16 BYTES
MONITOR ROM — 464 BYTES
USER RAM — 256 BYTES
USER ROM — 8,192 BYTES
CONTROL AND STATUS REGISTERS — 64 BYTES
CPU
REGISTERS
M68HC08 CPU
DDRA
DDRB
DDRC
DDRD
DDRE
PTA
PTB
PTC
PTD
PTE
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HC908JB8AD/D
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HC908JB8AD/D
MC68HC08JB8A
$0000
↓
$003F
I/O Registers
64 Bytes
$0040
↓
$013F
RAM
256 Bytes
$0140
↓
$DBFF
Unimplemented
56,000 Bytes
$DC00
↓
$FBFF
ROM
8,192 Bytes
$FC00
↓
$FDFF
Unimplemented
512 Bytes
$FE00
Break Status Register (BSR)
$FE01
Reset Status Register (RSR)
$FE02
Reserved
$FE03
Break Flag Control Register (BFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Reserved
$FE06
Reserved
$FE07
Reserved
$FE08
Reserved
$FE09
Reserved
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address High Register (BRKH)
$FE0D
Break Address Low Register (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
Reserved
$FE10
↓
$FFDF
Monitor ROM
464 Bytes
$FFE0
↓
$FFEF
Reserved
16 Bytes
$FFF0
↓
$FFFF
ROM Vectors
16 Bytes
Figure 2. MC68HC08JB8A Memory Map
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Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08JB8A.
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On the MC68HC908JB8, these two locations are the FLASH control register
and the FLASH block protect register respectively.
Monitor ROM
The monitor program (monitor ROM: $FE10–$FFDF) on the MC68HC08JB8A
is for device testing only. $FC00–$FDFF are unused.
Electrical
Specifications
Electrical specifications for the MC68HC908JB8 apply to the MC68HC08JB8A,
except for the parameters indicated below.
DC Electrical
Characteristics
Table 2. DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Regulator output voltage
VREG
3.0
3.3
3.6
V
Output high voltage (ILoad = –2.0 mA)
PTA0–PTA7, PTB0–PTB7, PTC0–PTC7,
PTE0–PTE2
VOH
VREG –0.8
—
—
V
Output low voltage
(ILoad = 1.6 mA) All I/O pins
(ILoad = 25 mA) PTD0–PTD1 in ILDD mode
(ILoad = 10 mA) PTE3–PTE4 with USB disabled
VOL
—
—
—
—
—
—
0.4
0.5
0.4
Input high voltage
All ports, OSC1
IRQ, RST
VIH
0.7 × VREG
0.7 × VDD
—
—
VREG
VDD
V
Input low voltage
All ports, OSC1
IRQ, RST
VIL
VSS
VSS
—
—
0.3 × VREG
0.3 × VDD
V
Output low current (VOL = 2.0 V)
PTD2–PTD5 in LDD mode
IOL
12 (17)
17 (22)
22 (27)
mA
—
—
—
—
6.0 (5.0)
5.5 (4.5)
4.0 (3.0)
3.0 (2.5)
7.5
6.5
5.0
4.0
mA
mA
mA
mA
—
30
100
µA
V
VDD supply current, VDD = 5.25V, fOP = 3MHz
Run, with low speed USB(3)
Run, with USB suspended(3)
Wait, with low speed USB(4)
Wait, with USB suspended(4)
Stop(5)
0 °C to 70°C
IDD
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MC68HC08JB8A
Table 2. DC Electrical Characteristics
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Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
I/O ports Hi-Z leakage current
IIL
—
—
± 10
µA
Input current
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
POR re-arm voltage(6)
VPOR
0
—
100
mV
POR rise-time ramp rate(7)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VDD+VHI
1.4 × VDD
2 × VDD
V
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4 (with USB module disabled)
D– (with USB module enabled)
RPU
LVI reset
VLVR
25
4
1.2
40
5
1.5
55
6
2.0
kΩ
2.8 (2.4)
3.3 (2.7)
3.8 (3.0)(8)
V
1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. CL = 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait IDD
5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ ± 5% between VREG
and D– pins and 15 kΩ ± 5% termination resistor on D+ pin; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VREG is reached.
8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.
Memory
Characteristics
Table 3. Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
Max
Unit
VRDR
1.3
—
V
Notes:
Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.
Addendum to MC68HC908JB8 Technical Data
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MC68HC08JB8A
Order Numbers
These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).
Table 4. MC68HC08JB8A Order Numbers
Package
Operating
temperature range
MC68HC08JB8AJP
20-pin PDIP
0 °C to +70 °C
MC68HC08JB8AJDW
20-pin SOIC
0 °C to +70 °C
MC68HC08JB8AADW
28-pin SOIC
0 °C to +70 °C
MC68HC08JB8AFB
44-pin QFP
0 °C to +70 °C
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MC order number
MC68HC08JB8A and MC68HC08JB8 Differences
The MC68HC08JB8A and MC68HC08JB8 are identical devices, except for the
following:
Table 5. MC68HC08JB8A and MC68HC08JB8 Differences
MC68HC08JB8A
OSC1 and OSC2 pins
VDD level (5V logic)
Output low current on PTD2–PTD5
in LDD mode
Operating IDD currents
MC68HC08JB8
VREG level (3.3V logic)
See Table 2 . DC Electrical Characteristics.
The numbers in parenthesis are MC68HC08JB8 values.
LVI trip points
Addendum to MC68HC908JB8 Technical Data
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NOTES
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NOTES
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
Rev. 0
4/2003
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