ETC HC908JB16AD

Freescale Semiconductor, Inc.
Addendum
HC908JB16AD/D
Rev. 1, 8/2002
Freescale Semiconductor, Inc...
Addendum to
MC68HC908JB16
Technical Data
This addendum provides update and additional information to the
MC68HC908JB16 Technical Data, Rev. 1
(Motorola document number MC68HC908JB16/D),
pertaining to the following:
•
MC68HC908JB16
– Update to VREG LVI trip point
– 20-pin SOIC package
•
MC68HC908JB12
•
MC68HC08JB16
MC68HC908JB16
This section updates data sheet information and introduces the 20-pin SOIC
package for the MC68HC908JB16.
VREG LVI Trip Point
Page 318, entry for minimum VREG LVI trip point voltage has been updated.
From:
Characteristic
VREG LVI trip point voltage
Symbol
Min
Typ
Max
Unit
VLVR
2.0
2.2
2.6
V
VLVR
1.9
2.2
2.6
V
To:
VREG LVI trip point voltage
© Motorola, Inc., 2003
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HC908JB16AD/D
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20-Pin SOIC
Order Number: MC68HC908JB16JDW
VSS
1
20
RST
OSC1
2
19
PTA0/KBA0
OSC2
3
18
PTA1/KBA1
VREG
4
17
PTA2/KBA2
VDD
5
16
PTA3/KBA3
PTD0/1
6
15
PTA4/KBA4
PTE1/T1CH01
7
14
PTA5/KBA5
PTE3/D+
8
13
PTA6/KBA6
Internal pads are unconnected.
PTE4/D–
9
12
PTA7/KBA7
PTC0/TxD
10
11
IRQ
PTD0/1 pin: PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin,
and has 50mA sink capability when configured as an output.
Pin direction must be configured such that DDRD0 = DDRD1.
Pins not available on 20-pin package:
PTC1/RxD
PTE0/TCLK
PTD2
PTE2/T2CH01
PTD3
CGMXFC1
CGMXFC2
PTD4
CGMOUT1
CGMOUT2
PTD5
VREGA0
VREGA1
VSSA0
VSSA1
VDDA
Figure 1. 20-Pin SOIC Pin Assignment
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
K
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
Figure 2. 20-Pin SOIC Mechanical Dimensions (Case No. 751D)
2
Addendum to MC68HC908JB16 Technical Data
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HC908JB16AD/D
MC68HC908JB12
MC68HC908JB12
This section introduces the MC68HC908JB12, a derivative of the
MC68HC908JB16. The entire MC68HC908JB16 data book, including the
updates in this addendum, applies to this device, with exceptions outlined
below.
Table 1. Summary of MC68HC908JB12 and MC68HC908JB16 Differences
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MC68HC908JB12
MC68HC908JB16
FLASH Memory
12,288 bytes
($CA00–$F9FF)
16,384 bytes
($BA00–$F9FF)
Dual Clock Generator Module
Not implemented.
$0051–$0059 unimplemented.
Available in 32-pin LQFP only.
Available Packages(1)
—
28-pin SOIC
20-pin SOIC
32-pin LQFP
28-pin SOIC
20-pin SOIC
Notes:
1. The pin assignments are identical for both devices; see data sheet.
MCU Block Diagram
Figure 3 shows the structure of the MC68HC908JB12.
Memory Map
Figure 4 shows the memory map of the MC68HC908JB12.
Dual Clock
Generator Module
The dual 27-MHz clock generator module on the MC68HC908JB16 is not
designed in the MC68HC908JB12, hence, register locations from $0051 to
$0059 are unimplemented. Information in the data book relating to the CGM do
not apply to the MC68HC908JB12.
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VDD
VSS
VREG (3.3V)
(3) IRQ
RST
(1) OSC2
(1) OSC1
(2)
ARITHMETIC/LOGIC
UNIT (ALU)
POWER AND INTERNAL
VOLTAGE REGULATORS
IRQ
MODULE
SYSTEM INTEGRATION
MODULE
OSCILLATOR
USER FLASH VECTORS — 48 BYTES
MONITOR ROM — 1,472 BYTES
USER RAM — 384 BYTES
USER FLASH MEMORY — 12,288 BYTES
LS USB
TRANSCEIVER
(3)
(3), (4)
PTE0/TCLK (3), (6)
PTE1/T1CH01 (3)
PTE2/T2CH01 (3), (6)
PTE3/D+
PTE4/D– (3), (4)
PTD0 (4), (7)
PTD1 (4), (7)
PTD2 (4), (6)
PTD3 (4), (6)
PTD4 (4), (6)
PTD5 (4), (6)
PTC0/TxD (3)
PTC1/RxD (3), (6)
PTA7/KBA7
:
PTA0/KBA0
(6) Pins available on 28-pin package only.
(7) On 20-pin package, PTD0 and PTD1 are bonded as a single PTD0/1 pin.
(1) Pins have 3V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pullup device.
(4) Pins are open-drain when configured as output.
USB ENDPOINT 0, 1, 2
USB MODULE
2-CHANNEL TIMER INTERFACE
MODULE 2
2-CHANNEL TIMER INTERFACE
MODULE 1
COMPUTER OPERATING
PROPERLY MODULE
POWER-ON RESET
MODULE
LOW VOLTAGE INHIBIT
MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
BREAK
MODULE
KEYBOARD INTERRUPT
MODULE
DDRA
INTERNAL BUS
Figure 3. MC68HC908JB12 Block Diagram
CONTROL AND STATUS REGISTERS — 128 BYTES
CPU
REGISTERS
M68HC08 CPU
PTA
PTC
DDRD
DDRC
PTD
PTE
4
DDRE
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HC908JB16AD/D
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HC908JB16AD/D
MC68HC908JB12
$0000
↓
$007F
I/O Registers
128 Bytes
$0080
↓
$01FF
RAM
384 Bytes
$0200
↓
$C9FF
Unimplemented
51,200 Bytes
$CA00
↓
$F9FF
FLASH Memory
12,288 Bytes
$FA00
↓
$FDFF
Monitor ROM 1
1,024 Bytes
$FE00
SIM Break Status Register (SBSR)
$FE01
SIM Reset Status Register (SRSR)
$FE02
Reserved
$FE03
SIM Break Flag Control Register (SBFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Interrupt Status Register 2 (INT2)
$FE06
Reserved
$FE07
Reserved
$FE08
FLASH Control Register (FLCR)
$FE09
FLASH Block Protect Register (FLBPR)
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address Register High (BRKH)
$FE0D
Break Address Register Low (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
Reserved
$FE10
↓
$FFCF
Monitor ROM 2
448 Bytes
$FFD0
↓
$FFFF
FLASH Vectors
48 Bytes
Figure 4. MC68HC908JB12 Memory Map
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HC908JB16AD/D
Pullup on PTE3/D+
and PTE4/D– Pins
On the MC68HC908JB12, control over the pullup devices on PTE3/D+ and
PTE4/D– pins are shown in Table 2.
Freescale Semiconductor, Inc...
Table 2. Pullup Control on PTE3/D+ and PTE4/D– Pins
PULLEN
($001A)
USBEN
($0038)
PTExP
($001D)
PTE4IE
($001C)
PTE3/D+ pin
PTE4/D– pin
0
0
0
0
—
—
0
0
1
0
5kΩ pullup to VDD
5kΩ pullup to VDD (1)
0
0
0
1
—
5kΩ pullup to VDD (1)
0
0
1
1
5kΩ pullup to VDD
5kΩ pullup to VDD (1)
0
1
X
X
—
—
1
1
X
X
—
1.5kΩ pullup to VREG
1
0
X
0
—
1.5kΩ pullup to VREG
1
0
X
1
Do not set this configuration.
Notes:
1. External interrupt function is also enabled on PTE4/D– pin.
Electrical
Specifications
Electrical specifications for the MC68HC908JB16 apply to the
MC68HC908JB12, except for the USB reset timing:
Signaling Levels
Bus State
Reset
Order Numbers
Transmit
Receive
D+ and D– < VIL (max) for ≥ 8µs (MC68HC908JB16)
D+ and D– < VIL (max) for ≥ 125µs (MC68HC908JB12)
NA
These are MC order numbers for MC68HC908JB12.
Table 3. MC68HC908JB12 Order Numbers
Package
Operating
Temperature Range
MC68HC908JB12JDW
20-pin SOIC
0 °C to +70 °C
MC68HC908JB12DW
28-pin SOIC
0 °C to +70 °C
MC Order Number
6
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Freescale Semiconductor, Inc.
HC908JB16AD/D
MC68HC08JB16
MC68HC08JB16
This section introduces the MC68HC08JB16, the ROM part equivalent to the
MC68HC908JB16. The entire MC68HC908JB16 data book applies to this
ROM device, with exceptions outlined below.
Table 4. Summary of MC68HC08JB16 and MC68HC908JB16 Differences
Freescale Semiconductor, Inc...
MC68HC08JB16
MC68HC908JB16
Memory ($BA00–$F9FF)
16,384 bytes ROM
16,384 bytes FLASH
User vectors ($FFD0–$FFFF)
48 bytes ROM
48 bytes FLASH
Registers at $FE08 and $FE09
Not used;
locations are reserved
FLASH related registers.
$FE08 — FLCR
$FE09 — FLBPR
Monitor ROM 1 ($FA00–$FDFF)
Unimplemented
Monitor ROM 2 ($FE10–$FFCF)
Used for testing purposes only.
Used for testing and FLASH
programming/erasing.
Dual Clock Generator Module
Currently not available.
Available in 32-pin LQFP only.
Available Packages(1)
32-pin LQFP currently not available.
28-pin SOIC
20-pin SOIC
32-pin LQFP
28-pin SOIC
20-pin SOIC
Notes:
1. The pin assignments are identical for both devices; see data sheet.
MCU Block Diagram
Figure 5 shows the block diagram of the MC68HC08JB16.
Memory Map
Figure 6 shows the memory map of the MC68HC08JB16.
Reserved Registers
The two registers at $FE08 and $FF09 are reserved locations on the
MC68HC08JB16.
On the MC68HC908JB16, these two locations are the FLASH control register
and the FLASH block protect register respectively.
Monitor ROM
MOTOROLA
The monitor program (monitor ROM, $FE10–$FFCF) on the MC68HC08JB16
is for device testing only.
Addendum to MC68HC908JB16 Technical Data
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7
(1) OSC2
(1) OSC1
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DDA
SSA1
VSSA0
(5) V
(5)
(5) V
VDD
VSS
VREG (3.3V)
VREGA0 (3.3V)
(5) V
REGA1 (3.3V)
(5)
RST
(3) IRQ
(2)
CGMXFC1
(1), (5) CGMOUT1
(5) CGMXFC2
(1), (5)
CGMOUT2
(5)
ARITHMETIC/LOGIC
UNIT (ALU)
LS USB
TRANSCEIVER
Shaded blocks indicate differences to MC68HC908JB16
(1) Pins have 3V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pull-up device.
(4) Pins are open-drain when configured as output.
(5) Pins available on 32-pin package only.
(6) Pins available on 28-pin package only.
USB ENDPOINT 0, 1, 2
USB MODULE
2-CHANNEL TIMER INTERFACE
MODULE 2
2-CHANNEL TIMER INTERFACE
MODULE 1
COMPUTER OPERATING
PROPERLY MODULE
POWER-ON RESET
MODULE
LOW VOLTAGE INHIBIT
MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
BREAK
MODULE
KEYBOARD INTERRUPT
MODULE
INTERNAL BUS
Figure 5. MC68HC08JB16 Block Diagram
POWER AND INTERNAL
VOLTAGE REGULATORS
IRQ
MODULE
SYSTEM INTEGRATION
MODULE
DUAL CLOCK
GENERATOR MODULE
OSCILLATOR
USER ROM VECTORS — 48 BYTES
MONITOR ROM — 448 BYTES
USER RAM — 384 BYTES
USER ROM — 16,384 BYTES
CONTROL AND STATUS REGISTERS — 128 BYTES
CPU
REGISTERS
M68HC08 CPU
DDRD
DDRA
DDRE
PTA
PTC
DDRC
PTD
8
PTE
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(3)
(3), (4)
PTE0/TCLK (3)
PTE1/T1CH01 (3)
PTE2/T2CH01 (3)
PTE3/D+
PTE4/D– (3), (4)
PTD0 (4)
PTD1 (4), (6)
PTD2 (4), (6)
PTD3 (4), (6)
PTD4 (4), (6)
PTD5 (4), (6)
PTC0/TxD (3)
PTC1/RxD (3)
PTA7/KBA7
:
PTA0/KBA0
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HC908JB16AD/D
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Freescale Semiconductor, Inc...
HC908JB16AD/D
MC68HC08JB16
$0000
↓
$007F
I/O Registers
128 Bytes
$0080
↓
$01FF
RAM
384 Bytes
$0200
↓
$B9FF
Unimplemented
47,104 Bytes
$BA00
↓
$F9FF
ROM
16,384 Bytes
$FA00
↓
$FDFF
Unimplemented
1,024 Bytes
$FE00
SIM Break Status Register (SBSR)
$FE01
SIM Reset Status Register (SRSR)
$FE02
Reserved
$FE03
SIM Break Flag Control Register (SBFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Interrupt Status Register 2 (INT2)
$FE06
Reserved
$FE07
Reserved
$FE08
Reserved
$FE09
Reserved
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address Register High (BRKH)
$FE0D
Break Address Register Low (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
Reserved
$FE10
↓
$FFCF
Monitor ROM
448 Bytes
$FFD0
↓
$FFFF
ROM Vectors
48 Bytes
Figure 6. MC68HC08JB16 Memory Map
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Electrical
Specifications
Electrical specifications for the MC68HC908JB16 apply to the
MC68HC08JB16, except for the following:
FLASH Memory
Characteristics
The FLASH memory electrical characteristics do not apply to the
MC68HC08JB16 ROM device.
ROM MC Order
Numbers
These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).
Freescale Semiconductor, Inc...
Table 5. ROM MC Order Numbers
Package
Operating
Temperature Range
MC68HC08JB16JDW
20-pin SOIC
0 °C to +70 °C
MC68HC08JB16DW
28-pin SOIC
0 °C to +70 °C
MC Order Number
10
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HC908JB16AD/D
NOTES
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NOTES
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© Motorola, Inc. 2003
HC908JB16AD/D
Rev. 1
8/2003
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