FREESCALE MC68HC705JD

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC705J2/D
Rev. 2
HC05
MC68HC705J2
TECHNICAL
DATA
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
MC68HC705J2
Freescale Semiconductor, Inc...
HCMOS MICROCONTROLLER UNIT
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NOTE
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Paragraph
Freescale Semiconductor, Inc...
1.1
1.2
Title
Page
SECTION 1
INTRODUCTION
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
SECTION 2
PIN DESCRIPTIONS
2.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.1
Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.2
Ceramic Resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.3
External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3
IRQ/VPP (External Interrupt Request/Programming Voltage) . . . . . . . . . . . . . . 2-4
2.4
3.1
3.2
3.3
SECTION 3
PARALLEL I/O
I/O Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
SECTION 4
CENTRAL PROCESSOR UNIT
4.1
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.2
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.5
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.5.1
Half-Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.5.2
Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.5.3
Negative Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.5.4
Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.1.5.5
Carry/Borrow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2
Arithmetic/Logic Unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.1
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.2
WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Title
Page
SECTION 5
RESETS AND INTERRUPTS
5.1
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2.1
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.1.1
Timer Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.1.2
Real-Time Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.2
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.3
Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
SECTION 6
MEMORY
6.1
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1
Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.2
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.3
EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.3.1
EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.3.2
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.1.4
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.2
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
7.1
7.2
7.3
SECTION 7
TIMER
Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Timer Control and Status Register (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
COP Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
SECTION 8
BOOTLOADER MODE
8.1
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1
External EPROM Downloading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2
Host Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
9.1
9.2
9.3
iv
SECTION 9
MC68HC05J1 EMULATION MODE
Bootloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
MC68HC05J1 Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
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TABLE OF CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Title
Page
SECTION 10
INSTRUCTION SET
10.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.4 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.1.8 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.2.5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
11.3
11.4
11.5
11.6
11.7
SECTION 11
ELECTRICAL SPECIFICATIONS
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
DC Electrical Characteristics (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . 11-3
DC Electrical Characteristics (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Control Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Control Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
12.1
12.2
12.3
SECTION 12
MECHANICAL SPECIFICATIONS
Plastic Dual In-Line Package (DIP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Ceramic DIP (Cerdip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Rev. 2
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vi
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Rev. 2
Freescale Semiconductor, Inc.
1
2
LIST OF FIGURES
Freescale Semiconductor, Inc...
Figure
Title
Page
1-1
MC68HC705J2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2-1
2-2
2-3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Crystal/Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3-1
3-2
3-3
3-4
3-5
Parallel I/O Port Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-2
4-3
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
STOP Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
WAIT Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
5-1
5-2
5-3
5-4
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Trigger Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-2
6-3
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
EPROM Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
7-1
7-2
7-3
7-4
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control and Status Register (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-2
Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
9-1
MC68HC05J1 Emulation Mode Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . 9-2
3-2
3-3
3-3
3-4
3-4
5-2
5-3
5-5
5-6
7-1
7-2
7-2
7-4
11-1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11-2 Typical High-Side Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11-3 Typical Low-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
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vii
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Freescale Semiconductor, Inc.
LIST OF FIGURES
Figure
2
3
4
Freescale Semiconductor, Inc...
5
6
11-4
11-5
11-6
11-7
11-8
11-9
Title
Page
Typical Supply Current vs Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Maximum Supply Current vs Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . 11-6
External Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
STOP Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
External Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
12-1 MC68HC705J2P (Case 738-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12-2 MC68HC705J2DW (Case 751D-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12-3 MC68HC705J2S (Case 732-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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Freescale Semiconductor, Inc.
LIST OF TABLES
Freescale Semiconductor, Inc...
Table
Title
Page
3-1
I/O Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
7-1
Real-Time Interrupt Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
8-1
Bootloader Function Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Jump and Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
11-1
11-2
11-3
11-4
11-5
11-6
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . .
Control Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 2
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11-1
11-1
11-3
11-4
11-7
11-8
ix
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Rev. 2
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1
2
SECTION 1
INTRODUCTION
Freescale Semiconductor, Inc...
3
The MC68HC705J2 is a member of the low-cost, high-performance M68HC05
Family of 8-bit microcontroller units (MCUs). The high-density, complementary
metal-oxide semiconductor (HCMOS) M68HC05 Family is based on the
customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family
use the popular M68HC05 central processor unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
4
The MC68HC705J2 is an expansion of the MC68HC05J1 design. On-chip memory
is enhanced with 2 Kbytes of erasable, programmable ROM (EPROM), 112 Kbytes
of RAM, and a bootloader ROM.
7
1.1 Features
5
6
8
9
The MCU features include the following:
10
•
Popular M68HC05 CPU
•
Memory-Mapped Input/Output (I/O) Registers
•
2064 Bytes of User EPROM Including 16 User Vector Locations
•
112 Bytes of Static RAM (SRAM)
•
14 Bidirectional I/O Pins
•
Fully Static Operation With No Minimum Clock Speed
•
On-Chip Oscillator With Crystal/Ceramic Resonator Connections
•
15-Bit Multifunction Timer
•
Real-Time Interrupt Circuit
•
Bootloader ROM
•
Power-Saving STOP, WAIT, and Data Retention Modes
•
MC68HC05J1 Emulation Mode
17
•
Selectable Edge-Sensitive or Edge- and Level-Sensitive External Interrupt
Trigger
18
•
Selectable Computer Operating Properly (COP) Timer
•
8 x 8 Unsigned Multiply Instruction
•
One Time Programmable 20-Pin Dual-in-Line Package (DIP)
11
12
13
14
15
16
19
20
INTRODUCTION
Rev. 2
1-1
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1
2
•
One Time Programmable 20-Pin Small Outline Integrated Circuit (SOIC)
•
Windowed 20-Pin Cerdip
1.2 Structure
3
Figure 1-1 shows the organization of the MC68HC705J2 EPROM MCU.
4
5
7
SRAM — 112 BYTES
7
8
0
M68HC05
CPU
IRQ/VPP
ACCUMULATOR
7
9
RESET
0
RST
INDEX REGISTER
15
7
5
0 0 0 0 0 0 0 0 1 1
10
PORT A
BOOTLOADER ROM — 239 BYTES
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORT B
6
DATA DIRECTION A
Freescale Semiconductor, Inc...
USER EPROM — 2064 BYTES
PB5
PB4
PB3
PB2
PB1
PB0
0
STACK POINTER
11
0
DATA DIRECTION B
15
11
0 0 0 0 0
PROGRAM COUNTER
7
0
1 1 1 H I N Z C
12
CONDITION CODE REGISTER
13
OSC1
OSC2
14
OSCILLATOR
DIVIDE
BY 2
f op
COP TIMER
AND
ILLEGAL ADDRESS DETECT
15
V DD
VSS
16
17
15-STAGE
MULTIFUNCTION TIMER
POWER
Figure 1-1. MC68HC705J2 Block Diagram
18
19
20
INTRODUCTION
1-2
Rev. 2
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1
2
SECTION 2
PIN DESCRIPTIONS
3
This section describes the function of each pin. Figure 2-1 shows the pin
assignments.
4
Freescale Semiconductor, Inc...
5
6
OSC1
1
20
RESET
OSC2
2
19
IRQ/VPP
PB5
3
18
PA0
8
PB4
4
17
PA1
9
PB3
5
16
PA2
10
PB2
6
15
PA3
PB1
PB0
7
14
8
VDD
9
VSS
10
13
12
11
PA4
PA5
PA6
PA7
7
OSC1
1
20
RESET
OSC2
2
19
IRQ/VPP
PB5
3
18
PA0
PB4
4
17
PA1
PB3
5
16
PA2
PB2
6
15
PA3
PB1
7
14
PA4
PB0
VDD
8
13
PA5
9
12
PA6
VSS
10
11
PA7
11
12
13
14
15
DIP/CERDIP
SOIC
16
Figure 2-1. Pin Assignments
17
18
19
20
PIN DESCRIPTIONS
Rev. 2
2-1
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1
2.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates from a
single 5-V power supply.
2
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, take special care to provide good power supply bypassing at the
MCU. Use bypass capacitors with good high-frequency characteristics, and
position them as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily loaded the MCU pins are.
3
4
Freescale Semiconductor, Inc...
5
6
2.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip oscillator.
Connect any of the following to the OSC1 and OSC2 pins:
7
8
9
A crystal (Refer to Figure 2-2.)
•
A ceramic resonator (Refer to Figure 2-2)
•
An external clock signal (Refer to Figure 2-3)
The MCU divides the frequency, fosc, of the oscillator or external clock source by
two to produce the internal operating frequency, fop.
10
11
•
2.2.1 Crystal
The circuit in Figure 2-2 shows a typical crystal oscillator circuit for a parallel
resonant crystal. Follow the crystal supplier's recommendations, as the crystal
parameters determine the external component values required to provide
maximum stability and reliable start-up. The load capacitance values used in the
oscillator circuit design should include all stray layout capacitances. Mount the
crystal and components as close as possible to the pins for start-up stabilization
and to minimize output distortion.
12
13
14
15
2.2.2 Ceramic Resonator
16
In cost-sensitive applications, use a ceramic resonator in place of the crystal. Use
the circuit in Figure 2-2 for a ceramic resonator, and follow the resonator
manufacturer's recommendations, as the resonator parameters determine the
external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include all
stray layout capacitances.
17
18
19
20
PIN DESCRIPTIONS
2-2
Rev. 2
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STOP
1
2
OSC1
3
OSC2
4.7 M
4
5
XTAL
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37 pF
37 pF
6
7
Figure 2-2. Crystal/Ceramic Resonator Connections
8
2.2.3 External Clock
An external clock from another CMOS-compatible device can drive the OSC1 input,
with the OSC2 pin not connected, as Figure 2-3 shows.
9
10
11
STOP
12
13
OSC1
OSC2
14
NOT CONNECTED
15
EXTERNAL
CMOS CLOCK
16
Figure 2-3. External Clock Connections
17
18
19
20
PIN DESCRIPTIONS
Rev. 2
2-3
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2.3 RESET
1
A zero on the RESET pin forces the MCU to a known start-up state. See 5.1
Resets for more information.
2
3
2.4 IRQ/VPP (External Interrupt Request/Programming Voltage)
The IRQ/VPP pin has the following functions:
4
Applying asynchronous external interrupt signals (See 5.2 Interrupts.)
•
Applying the programming voltage for programming the EPROM (See
6.1.3.1 EPROM Programming and 8.1.1 External EPROM Downloading.)
Freescale Semiconductor, Inc...
5
•
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN DESCRIPTIONS
2-4
Rev. 2
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1
2
SECTION 3
PARALLEL I/O
3
This section describes the two bidirectional I/O ports.
4
3.1 I/O Port Function
5
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The 14 I/O pins form two I/O ports. Each I/O pin is programmable as an input or an
output. The contents of a port data direction register (DDR) determine the data
direction for the port. Writing a 1 to a DDR bit enables the output buffer for the
associated port pin; a 0 disables the output buffer. A reset initializes all implemented
DDR bits to 0, configuring all I/O pins as inputs.
6
7
8
9
NOTE
Connect any unused inputs and I/O pins to an appropriate logical level,
either VDD or VSS. Although the I/O ports do not require termination for
proper operation, termination reduces the possibility of electrostatic
damage.
10
11
12
A reset does not initialize the two port data registers. The port data registers for ports
A and B are at addresses $0000 and $0001. To avoid undefined levels, write the data
registers before writing the data direction registers.
With an I/O port pin programmed as an output, reading the pin actually reads the
value of the output data latch and not the voltage on the pin itself. When a pin is
programmed as an input, reading the port bit reads the voltage level on the I/O pin.
The output data latch can always be written, regardless of the state of its DDR bit.
Refer to Figure 3-1 for typical port circuitry, and to Table 3-1 for a summary of I/O pin
functions.
13
14
15
16
17
18
19
20
PARALLEL I/O
Rev. 2
3-1
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1
DATA DIRECTION
REGISTER
BIT
CONNECTIONS TO INTERNAL
DATA BUS
2
3
4
5
LATCHED
OUTPUT DATA
BIT
[1]
I/O
PIN
[3]
Freescale Semiconductor, Inc...
[2]
6
[1] Output buffer enables latched output to drive I/O pin when DDR bit is 1 (output mode).
[2] Input buffer enabled when DDR bit is 0 (input mode).
[3] Input buffer enabled when DDR bit is 1 (output mode).
7
Figure 3-1. Parallel I/O Port Circuit
8
9
Table 3-1. I/O Pin Functions
10
11
12
R/W
DDR Bit
0
0
The I/O pin is an input. Data is written into the output data latch.
I/O Pin Function
0
1
Data is written into the output data latch, which drives the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is an output. The output data latch is read.
NOTE: R/W is an internal MCU signal.
13
14
15
16
17
18
19
20
PARALLEL I/O
3-2
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3.2 Port A
Port A is an 8-bit general-purpose bidirectional I/O port. The contents of DDRA
determine whether each pin is an input or an output. Figure 3-2 and Figure 3-3 show
the port A data register and DDRA.
1
2
PORTA — Port A Data Register
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
3
4
NOT CHANGED BY RESET
Freescale Semiconductor, Inc...
Figure 3-2. Port A Data Register
5
PA7–PA0 — Port A Data Bits
These read/write bits are software-programmable. Data direction of each bit is
under the control of the corresponding DDRA bit.
DDRA — Port A Data Direction Register
RESET:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
0
0
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
6
7
8
9
10
Figure 3-3. Port A Data Direction Register
11
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
12
13
14
15
16
17
18
19
20
PARALLEL I/O
Rev. 2
3-3
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3.3 Port B
1
Port B is a 6-bit general-purpose bidirectional I/O port. The contents of DDRB
determine whether each pin is an input or an output. Figure 3-4 and Figure 3-5
show the port B data register and DDRB.
2
3
PORTB — Port B Data Register
4
Bit 7
6
5
4
3
2
1
Bit 0
0
0
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
5
$0001
NOT CHANGED BY RESET
Freescale Semiconductor, Inc...
Figure 3-4. Port B Data Register
6
PB5–PB0 — Port B Data Bits
7
These read/write bits are software-programmable. Data direction of each bit is
under the control of the corresponding DDRA bit.
8
DDRB — Port B Data Direction Register
9
10
RESET:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 3-5. Port B Data Direction Register
11
DDRB7–DDRB0 — Port B Data Direction Bits
12
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
13
14
15
16
17
18
19
20
PARALLEL I/O
3-4
Rev. 2
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1
2
SECTION 4
CENTRAL PROCESSOR UNIT
3
This section describes the registers, aithmetic/logic unit (ALU), and low-power modes
of the M68HC05 central processor unit (CPU).
5
4.1 CPU Registers
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4
Figure 4-1 shows the five CPU registers. These are hard-wired registers within the
CPU and are not part of the memory map.
6
7
7
0
8
A
ACCUMULATOR (A)
9
7
0
10
X
INDEX REGISTER (X)
15
0
6
0
0
0
0
0
0
0
1
5
11
0
1
12
SP
STACK POINTER (SP)
15
0
12 11*
0
0
0
8
7
PCH
PCL
7
1
13
0
1
5
4
1
H
PROGRAM COUNTER (PC)
14
0
I
N
Z
C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
15
16
ZERO PLAN
NEGATIVE FLAG
17
INTERRUPT MASK
HALF-CARRY FLAG
18
*Bit 11 of the program counter is fixed at 0 in MC68HC05J1 emulation mode.
19
Figure 4-1. Programming Model
20
CENTRAL PROCESSOR UNIT
Rev. 2
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4.1.1 Accumulator
1
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and results of arithmetic and nonarithmetic
operations.
2
3
4.1.2 Index Register
4
The 8-bit index register can perform two functions:
Freescale Semiconductor, Inc...
5
6
Indexed addressing
•
Temporary storage
In indexed addressing, the CPU uses the byte in the index register to determine
the conditional address of the operand.
7
The index register can also serve as an auxiliary accumulator for temporary
storage.
8
9
•
4.1.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next free
location on the stack. During a reset or after the reset stack pointer (RSP)
instruction, the stack pointer contents are preset to $00FF. The address in the
stack pointer decrements as data is pushed onto the stack and increments as data
is pulled from the stack.
10
11
12
The ten most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If
subroutines and interrupts use more than 64 stack locations, the stack pointer
wraps around to address $00C0 and begins writing over the previously stored data.
A subroutine uses two stack locations; an interrupt uses five locations.
13
14
15
16
17
18
19
20
CENTRAL PROCESSOR UNIT
4-2
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4.1.4 Program Counter
The program counter is a 16-bit register that contains the address of the next
instruction or operand to be fetched. The four most significant bits of the program
counter are permanently fixed at 0000. In MC68HC05J1 emulation mode, the five
most significant bits are fixed at 00000.
Normally, the address in the program counter automatically increments to the next
sequential memory location every time an instruction or operand is fetched. Jump,
branch, and interrupt operations load the program counter with an address other than
that of the next sequential location.
2
3
4
5
4.1.5 Condition Code Register
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1
The condition code register is an 8-bit register whose three most significant bits are
permanently fixed at 111. The condition code register contains the interrupt mask
and four flags that indicate the results of the instruction just executed. The following
paragraphs describe the functions of the condition code register.
6
7
8
4.1.5.1 Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the
accumulator during an ADD or ADC operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations.
9
10
11
4.1.5.2 Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request occurs while the
interrupt mask is zero, the CPU saves the CPU registers on the stack, sets the
interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs
while the interrupt mask is set, the interrupt request is latched. Normally, the CPU
processes the latched interrupt as soon as the interrupt mask is cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is
set and can be cleared only by a software instruction.
12
13
14
15
16
4.1.5.3 Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical operation, or
data manipulation produces a negative result. Bit 7 of the negative result is
automatically set, so the negative flag can be used to check an often-tested bit by
assigning it to bit 7 of a register or memory location. Loading the accumulator with
the contents of that register or location then sets or clears the negative flag according
to the state of the tested bit.
17
18
19
20
CENTRAL PROCESSOR UNIT
Rev. 2
4-3
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4.1.5.4 Zero Flag
1
The CPU sets the zero flag when an arithmetic operation, logical operation, or data
manipulation produces a $00.
2
3
4.1.5.5 Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry
out of bit 7 of the accumulator. Some logical operations and data manipulation
instructions also clear or set the carry/borrow flag.
4
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5
4.2 Arithmetic/Logic Unit (ALU)
6
The ALU performs the arithmetic and logical operations defined by the instruction
set.
7
The binary arithmetic circuits decode instructions and set up the ALU for the
selected operation. Most binary arithmetic is based on the addition algorithm,
carrying out subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within the ALU.
The multiply instruction (MUL) requires 11 internal processor cycles to complete
this chain of operations.
8
9
10
11
4.3 Low-Power Modes
The following paragraphs describe the STOP and WAIT modes. (Refer also to 6.2
Data Retention Mode.)
12
13
4.3.1 STOP Mode
The STOP instruction puts the MCU in its lowest power-consumption mode. In
STOP mode, the following events occur:
14
15
•
The CPU clears TOF and RTIF, the timer interrupt flags in the timer control
and status register, removing any pending timer interrupts.
16
•
The CPU clears TOIE and RTIE, the timer interrupt enable bits in the timer
control and status register, disabling further timer interrupts.
17
•
The CPU clears the divide-by-four timer prescaler.
•
The CPU clears the interrupt mask in the condition code register, enabling
external interrupts.
•
The internal oscillator stops, halting all internal processing, including
operation of the timer and the COP timer.
18
19
The STOP instruction does not affect any other registers or any I/O lines.
20
CENTRAL PROCESSOR UNIT
4-4
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The following conditions bring the MCU out of STOP mode:
•
•
An external interrupt. An external interrupt automatically loads the program
counter with the contents of locations $0FFA and $0FFB, the locations of the
vector address of the external interrupt service routine.
A reset signal on the RESET pin. A reset automatically loads the program
counter with the contents of locations $0FFE and $0FFF, the locations of the
vector address of the reset service routine.
Refer to Figure 11-7 in SECTION 11 ELECTRICAL SPECIFICATIONS for STOP
recovery timing.
1
2
3
4
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5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CENTRAL PROCESSOR UNIT
Rev. 2
4-5
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Figure 4-2 shows the sequence of events caused by the STOP instruction.
1
2
STOP
3
4
CLEAR TIMER INTERRUPT FLAGS AND
TIMER INTERRUPT ENABLE BITS.
CLEAR TIMER PRESCALER.
CLEAR CCR INTERRUPT MASK.
STOP OSCILLATOR.
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5
6
NO
7
RESET
?
YES
8
NO
9
EXTERNAL
INTERRUPT
?
YES
10
11
12
TURN ON OSCILLATOR.
DELAY 4064 CYCLES
TO STABILIZE.
13
14
(1) FETCH RESET VECTOR or
(2) SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET CCR INTERRUPT MASK.
c. VECTOR TO INTERRUPT
SERVICE ROUTINE.
15
16
Figure 4-2. STOP Instruction Flowchart
17
18
19
20
CENTRAL PROCESSOR UNIT
4-6
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4.3.2 WAIT Mode
The WAIT instruction puts the MCU in an intermediate power-consumption mode.
In WAIT mode, the following events occur:
•
All CPU clocks stop.
•
The CPU clears the interrupt mask in the condition code register, enabling
external interrupts and timer interrupts.
The WAIT instruction does not affect any other registers or any I/O lines. The timer
and COP timer remain active in WAIT mode.
Freescale Semiconductor, Inc...
2
3
4
5
The following conditions bring the MCU out of WAIT mode:
•
1
A timer interrupt. If a real-time interrupt or a timer overflow interrupt occurs
during WAIT mode, the MCU loads the program counter with the contents of
locations $0FF8 and $0FF9, the locations of the vector address of the timer
interrupt service routine.
6
•
An external interrupt. An external interrupt automatically loads the program
counter with the contents of locations $0FFA and $0FFB, the locations of the
vector address of the external interrupt service routine.
8
•
A COP timer reset. A timeout of the COP timer during WAIT mode resets
the MCU. The programmer can enable real-time interrupts so the MCU can
periodically exit WAIT mode to reset the COP timer.
7
9
10
A reset signal on the RESET pin during WAIT mode resets the MCU.
11
A COP timer reset or a reset signal on the RESET pin automatically loads the
program counter with the contents of locations $0FFE and $0FFF, the locations of
the vector address of the reset service routine.
12
•
13
Figure 4-3 shows the sequence of events caused by the WAIT instruction.
14
15
16
17
18
19
20
CENTRAL PROCESSOR UNIT
Rev. 2
4-7
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1
2
WAIT
3
4
OSCILLATOR ACTIVE.
TIMER CLOCKS ACTIVE.
STOP CPU CLOCKS.
CLEAR CCR INTERRUPT MASK.
Freescale Semiconductor, Inc...
5
6
RESET
?
7
NO
YES
EXTERNAL
INTERRUPT
?
8
YES
9
YES
10
NO
INTERNAL
TIMER
INTERRUPT
?
NO
11
RESTART
CPU CLOCK.
12
13
(1) FETCH RESET VECTOR or
(2) SERVICE INTERRUPT.
a. SAVE CPU REGS ON STACK.
b. SET I-BIT IN CCR.
c. VECTOR TO INTERRUPT
SERVICE ROUTINE.
14
15
16
Figure 4-3. WAIT Instruction Flowchart
17
18
19
20
CENTRAL PROCESSOR UNIT
4-8
Rev. 2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
1
2
SECTION 5
RESETS AND INTERRUPTS
3
This section describes how resets reinitialize the MCU and how interrupts temporarily
change the normal processing sequence.
5
5.1 Resets
Freescale Semiconductor, Inc...
4
A reset immediately stops the operation of the instruction being executed. A reset
initializes certain control bits to known conditions and loads the program counter with
a user-defined reset vector address. The following conditions produce a reset:
•
Initial power-up (power-on reset)
•
A logical zero applied to the RESET pin (external reset)
•
Timeout of the COP timer (COP reset)
•
An opcode fetch from an address not in the memory map (illegal address reset)
6
7
8
9
10
A reset does the following things to reinitialize the MCU:
•
Clears all implemented data direction register bits so that the corresponding
I/O pins are inputs
11
•
Loads the stack pointer with $FF
12
•
Sets the interrupt mask, inhibiting interrupts
•
Clears the TOFE and RTIE bits in the timer control and status register
•
Clears the STOP latch, enabling the CPU clocks
•
Clears the WAIT latch, waking the CPU from the WAIT mode
•
Loads the program counter with the user-defined reset vector
13
14
15
16
5.1.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The power-on reset
is strictly for power-up conditions and cannot be used to detect drops in power supply
voltage.
17
18
19
20
RESETS AND INTERRUPTS
Rev. 2
5-1
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A 4064 tcyc (internal clock cycle) delay after the oscillator becomes active allows
the clock generator to stabilize. If the RESET pin is at a logical zero at the end of
4064 tcyc, the MCU remains in the reset condition until the signal on the RESET pin
goes to a logical one.
1
2
3
5.1.2 External Reset
A zero applied to the RESET pin for one and one-half tcyc generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
4
Freescale Semiconductor, Inc...
5
5.1.3 Computer Operating Properly (COP) Reset
6
A timeout of the COP timer generates a COP reset. The COP timer is part of a
software error detection system and must be cleared periodically to start a new
timeout period. (See 7.3 COP Timer.) To clear the COP timer and prevent a COP
reset, write a zero to bit 0 (COPR) of the COP control register at location $0FF0
before the COP timer times out. The COP control register is a write-only register
that returns the contents of an EPROM location when read. See Figure 5-1.
7
8
9
COPR — COP Control Register
10
RESET
11
$0FF0
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
COPR
—
—
—
—
—
—
—
0
Figure 5-1. COP Control Register
12
COPR — COP Reset
13
COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP
timer from resetting the MCU.
14
5.1.4 Illegal Address Reset
15
An opcode fetch from an address that is not in the EPROM (locations
$0700–$0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.
16
17
18
19
20
RESETS AND INTERRUPTS
5-2
Rev. 2
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5.2 Interrupts
An interrupt temporarily stops normal processing to process a particular event.
Unlike a reset, an interrupt does not stop the operation of the instruction being
executed. An interrupt takes effect when the current instruction completes its
execution. An interrupt saves the CPU registers on the stack and loads the program
counter with a user-defined interrupt vector address. The following conditions
produce an interrupt:
•
Timer overflow or real-time interrupt request (timer interrupts)
•
A logical zero applied to the IRQ pin (external interrupt)
•
SWI instruction (software interrupt)
1
2
3
4
5
Freescale Semiconductor, Inc...
The CPU does the following things to begin servicing an interrupt:
•
Stores the contents of the CPU registers on the stack as shown in Figure 5-2
6
7
8
TOWARD LOWER ADDRESSES
(LOWEST STACK ADDRESS IS $00C0)
STACK
7
9
0
CONDITION CODE REGISTER
10
INDEX REGISTER
RETURN
INTERRUPT
ACCUMULATOR
11
PROGRAM COUNTER HIGH
12
PROGRAM COUNTER LOW
13
UNSTACK
TOWARD HIGHER ADDRESSES
(HIGHEST STACK ADDRESS IS $00FF)
14
Figure 5-2. Interrupt Stacking Order
15
•
Sets the interrupt mask to prevent further interrupts
16
•
Loads the program counter with the contents of the appropriate interrupt vector
locations:
– $0FF8 and $0FF9 (timer interrupt vector)
– $0FFA and $0FFB (external interrupt vector)
– $0FFC and $0FFD (software interrupt vector)
17
18
19
20
RESETS AND INTERRUPTS
Rev. 2
5-3
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The return from interrupt (RTI) instruction causes the CPU to recover the CPU
registers from the stack as shown in Figure 5-2.
1
2
5.2.1 Timer Interrupts
The timer generates two kinds of interrupts:
3
4
Freescale Semiconductor, Inc...
Real-time interrupt
A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set while
the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the
timer control and status register. See 7.2 Timer Control and Status Register
(TCSR).
8
5.2.1.2 Real-Time Interrupts
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while
the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer
control and status register. See 7.2 Timer Control and Status Register (TCSR).
10
11
12
•
5.2.1.1 Timer Overflow Interrupts
7
9
Timer overflow interrupt
Setting the interrupt mask in the condition code register disables timer interrupts.
5
6
•
5.2.2 External Interrupt
When a falling edge occurs on the IRQ pin, an external interrupt request is latched.
When the CPU completes its current instruction, it tests the external interrupt latch.
If the interrupt latch is set and the interrupt mask in the condition code register is
reset, the CPU then begins the interrupt sequence. The CPU clears the interrupt
latch while it fetches the interrupt vector, so that another external interrupt request
can be latched during the interrupt service routine. As soon as the interrupt mask
is cleared (usually during the return from interrupt), the CPU can recognize the new
interrupt request.
13
14
15
16
Figure 5-3 shows the sequence of events caused by an interrupt.
17
18
19
20
RESETS AND INTERRUPTS
5-4
Rev. 2
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1
FROM
RESET
2
YES
3
INTERRUPT
MASK SET
?
4
NO
Freescale Semiconductor, Inc...
EXTERNAL
INTERRUPT
?
YES
CLEAR IRQ
REQUEST
LATCH.
5
6
NO
TIMER
INTERRUPT
?
YES
7
STACK PCL, PCH, X, A, CCR.
SET INTERRUPT MASK.
NO
8
LOAD PC WITH VECTOR:
MC68HC705J2 NATIVE MODE
TIMER: $0FF8, $0FF9
EXTERNAL: $0FFA, $0FFB
SOFTWARE: $0FFC, $0FFD
9
MC68HC05J1 EMULATION MODE
TIMER: $07F8, $07F9
EXTERNAL: $07FA, $07FB
SOFTWARE: $07FC, $07FD
10
11
12
FETCH NEXT
INSTRUCTION.
13
SWI
INSTRUCTION
?
YES
14
NO
RTI
INSTRUCTION
?
15
YES
RESTORE REGISTERS
FROM STACK
CCR, A, X, PCH, PCL.
16
NO
17
EXECUTE
INSTRUCTION.
18
Figure 5-3. Interrupt Flowchart
19
20
RESETS AND INTERRUPTS
Rev. 2
5-5
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Either an edge-sensitive or an edge- and level-sensitive external interrupt trigger
is programmable in the mask option register. Figure 5-4 shows the internal logic
of this programmable option.
1
2
3
LEVEL SENSITIVE TRIGGER
(MOR OPTION)
4
5
Freescale Semiconductor, Inc...
INTERRUPT MASK
VDD
D
6
C
IRQ
Q
R
EXTERNAL
INTERRUPT
REQUEST
Q
RESET
7
EXTERNAL INTERRUPT
BEING SERVICED
(VECTOR FETCH)
8
9
Figure 5-4. External Interrupt Trigger Option
10
The edge- and level-sensitive trigger option allows multiple external interrupt
sources to be wire-ORed to the IRQ pin. With the level-sensitive trigger option, an
external interrupt request is latched as long as any source is holding the IRQ pin
low.
11
12
Setting the interrupt mask in the condition code register disables external
interrupts.
13
14
5.2.3 Software Interrupt
The software interrupt (SWI) instruction causes a nonmaskable interrupt.
15
16
17
18
19
20
RESETS AND INTERRUPTS
5-6
Rev. 2
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1
2
SECTION 6
MEMORY
3
This section describes the organization of the on-chip memory.
4
Freescale Semiconductor, Inc...
6.1 Memory Map
5
The CPU can address 4 Kbytes of memory space. The program counter normally
advances one address at a time through the memory, reading the program
instructions and data. The EPROM portion of memory holds the program
instructions, fixed data, user-defined vectors, and service routines. The RAM portion
of memory holds variable data. I/O registers are memory-mapped so that the CPU
can access their locations in the same way that it accesses all other memory
locations.
Figure 6-1 is a memory map of the MCU. Figure 6-2 is a more detailed memory map
of the 32-byte I/O register section.
6
7
8
9
10
6.1.1 Input/Output Section
The first 32 addresses of the memory space, $0000–$001F, are defined as the I/O
section. These are the addresses of the I/O control registers, I/O status registers,
and I/O data registers.
11
12
13
6.1.2 RAM
The MCU has 112 bytes of fully static read/write memory for storage of variable and
temporary data during program execution. RAM addresses $00C0–$00FF serve as
the stack. The CPU uses the stack to save CPU register contents before processing
an interrupt or subroutine call. The stack pointer decrements during pushes and
increments during pulls.
14
15
16
17
NOTE
18
Be careful if using the stack addresses ($00C0–$00FF) for data
storage or as a temporary work area. The CPU may overwrite data in
the stack during a subroutine or interrupt.
19
20
MEMORY
Rev. 2
6-1
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1
2
$0000
3
$001F
$0020
PORT A DATA REGISTER
PORT B DATA REGISTER
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
UNUSED
UNUSED
TIMER CONTROL AND STATUS REGISTER
TIMER COUNTER REGISTER
UNUSED
•
•
•
UNUSED
EPROM PROGRAMMING REGISTER
UNUSED
UNUSED
RESERVED
I/O REGISTERS
32 BYTES
UNUSED
112 BYTES
4
$008F
$0090
5
Freescale Semiconductor, Inc...
$00BF
$00C0
6
SRAM
112 BYTES
STACK
64 BYTES
7
$00FF
$0100
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
•
•
•
$001B
$001C
$001D
$001E
$001F
UNUSED
1536 BYTES
8
$06FF
$0700
9
10
USER EPROM
2048 BYTES
11
12
$0EFF
$0F00
$0F01
13
14
COP REGISTER *
MASK OPTION REGISTER
USER
EPROM
8 BYTES
BOOTLOADER ROM
239 BYTES
15
TIMER INTERRUPT VECTOR (HIGH)
TIMER INTERRUPT VECTOR (LOW)
EXTERNAL INTERRUPT VECTOR (HIGH)
EXTERNAL INTERRUPT VECTOR (LOW)
SOFTWARE INTERRUPT VECTOR (HIGH)
SOFTWARE INTERRUPT VECTOR (LOW)
RESET VECTOR (HIGH)
RESET VECTOR (LOW)
$0FEF
$0FF0
USER VECTORS
(EPROM)
16 BYTES
16
$0FFF
$0FF0
•
•
•
$0FF7
$0FF8
$0FF9
$0FFA
$0FFB
$0FFC
$0FFD
$0FFE
$0FFF
*WRITING 0 TO BIT 0 OF $0FF0 CLEARS
17
COP TIMER. READING $0FF0 RETURNS
USER EPROM DATA.
18
Figure 6-1. Memory Map
19
20
MEMORY
6-2
Rev. 2
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Bit 7
6
5
4
3
2
1
Bit 0
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTA
1
$0001
0
0
PB5
PB4
PB3
PB2
PB1
PB0
PORTB
2
$0002
—
—
—
—
—
—
—
—
UNUSED
$0003
—
—
—
—
—
—
—
—
UNUSED
$0004
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRA
4
$0005
0
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRB
5
$0006
—
—
—
—
—
—
—
—
UNUSED
$0007
—
—
—
—
—
—
—
—
UNUSED
$0008
TOF
RTIF
TOIE
RTIE
0
0
RT1
RT0
TCSR
7
$0009
Bit 7
6
5
4
3
2
1
Bit 0
TCR
8
$000A
—
—
—
—
—
—
—
—
UNUSED
$000B
—
—
—
—
—
—
—
—
UNUSED
$000C
—
—
—
—
—
—
—
—
UNUSED
•
•
•
•
•
•
3
6
9
10
11
12
$0019
—
—
—
—
—
—
—
—
UNUSED
$001A
—
—
—
—
—
—
—
—
UNUSED
$001B
—
—
—
—
—
—
—
—
UNUSED
$001C
0
0
0
0
0
LATCH
0
EPGM
$001D
—
—
—
—
—
—
—
—
UNUSED
$001E
—
—
—
—
—
—
—
—
UNUSED
16
$001F
—
—
—
—
—
—
—
—
RESERVED
17
$0F00
—
—
—
—
—
J1
IRQ
COP
MOR
COPR
COP
$0FF0
PROG
13
14
15
18
19
Figure 6-2. I/O Registers
20
MEMORY
Rev. 2
6-3
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6.1.3 EPROM
1
Two Kbytes of user EPROM for storage of program instructions and fixed data are
located at addresses $0700–$0EFF. The eight addresses from $0FF8–$0FFF are
EPROM locations reserved for interrupt vectors and reset vectors. Eight additional
EPROM bytes are located at $0FF0–$0FF8. There are two ways to write data to
the EPROM:
2
3
4
Freescale Semiconductor, Inc...
5
6
•
The EPROM programming register contains the control bits for programming
the EPROM on a byte-by-byte basis.
•
The bootloader ROM contains routines to download the contents of an
external memory device to the on-chip EPROM.
6.1.3.1 EPROM Programming
7
The EPROM programming register, shown in Figure 6-3, contains the control bits
for programming the EPROM.
8
PROG — EPROM Programming Register
9
10
RESET
$001C
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
LATCH
0
EPGM
0
0
0
0
0
0
0
0
Figure 6-3. EPROM Programming Register (PROG)
11
LATCH — EPROM Bus Latch
12
This read/write bit causes address and data buses to be latched for EPROM
programming. Clearing the LATCH bit automatically clears the EPGM bit.
1 = Address and data buses configured for EPROM programming
0 = Address and data buses configured for normal operation
13
14
EPGM — EPROM Programming
15
This read/write bit applies programming power to the EPROM. To write the
EPGM bit, the LATCH bit must already be set.
1 = EPROM programming power switched on
0 = EPROM programming power switched off
16
17
Bits 7–3 and 1 — Not used; always read as zeros.
18
19
20
MEMORY
6-4
Rev. 2
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Take the following steps to program a byte of EPROM:
1. Apply 16.5 V to the IRQ/VPP pin.
1
2. Set the LATCH bit.
3. Write to any EPROM address.
2
4. Set the EPGM bit for a time tEPGM to apply the programming voltage.
3
5. Clear the LATCH bit.
4
Freescale Semiconductor, Inc...
6.1.3.2 EPROM Erasing
The erased state of an EPROM bit is zero. Erase the EPROM by exposing it to 15
Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the
ultraviolet light source 1 inch from the EPROM. Do not use a shortwave filter.
5
6
7
NOTE
Windowed packages must have the window covered during
programming and operation.
8
9
10
6.1.4 Bootloader ROM
Addresses $0F01–$0FEF contain the bootloader ROM, which can copy and verify
the contents of an external EPROM to the on-chip EPROM. See SECTION 8
BOOTLOADER MODE.
11
12
13
14
15
16
17
18
19
20
MEMORY
Rev. 2
6-5
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6.2 Data Retention Mode
1
In data retention mode, the MCU retains RAM contents and CPU register contents
at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to
remain in a low power-consumption state during which it retains data, but the CPU
cannot execute instructions.
2
3
To put the MCU in data retention mode:
4
1. Drive the RESET pin to zero.
5
2. Lower the VDD voltage. The RESET line must remain low continuously
during data retention mode.
To take the MCU out of data retention mode:
7
2. Return the RESET pin to logical one.
Freescale Semiconductor, Inc...
6
1. Return VDD to normal operating voltage.
8
9
10
11
12
13
14
15
16
17
18
19
20
MEMORY
6-6
Rev. 2
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Freescale Semiconductor, Inc.
1
2
SECTION 7
TIMER
3
This section describes the operation of the timer and the COP timer. Figure 7-1
shows the organization of the timer system.
4
Freescale Semiconductor, Inc...
5
INTERNAL PROCESSOR
CLOCK
(XTAL ÷ 2)
6
LEAST SIGNIFICANT EIGHT BITS OF 15-STAGE RIPPLE COUNTER
÷2
÷2
÷2
÷2
÷2
÷2
÷2
8
LSB
MSB
÷2
7
FIXED
DIVIDE BY
4
9
TCR $0009
TIMER COUNTER REGISTER
10
INTERRUPT REQUEST
0
RTIE
0
11
TOFE
RTIF
TOF
INTERRUPT CIRCUIT
TIMER CONTROL AND STATUS REGISTER
12
RT0
RT1
TCSR $0008
13
RTI RATE SELECT
POWER-ON
RESET (POR)
÷2
÷2
÷2
÷2
÷2
÷2
14
÷2
15
MOST SIGNIFICANT SEVEN BITS OF 15-STAGE RIPPLE COUNTER
÷2
CLEAR COP TIMER
÷2
÷2
S
Q
16
COP TIMER RESET
17
R
18
Figure 7-1. Timer
19
20
TIMER
Rev. 2
7-1
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7.1 Timer Counter Register (TCR)
1
A 15-stage ripple counter is the core of the timer. The value of the first eight stages
is readable at any time from the read-only timer counter register shown in Figure
7-2 .
2
3
TCR — Timer Counter Register
4
RESET
Freescale Semiconductor, Inc...
5
$0009
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Figure 7-2. Timer Counter Register (TCR)
6
Power-on clears the entire counter chain and begins clocking the counter. After
4064 cycles of the internal clock, the power-on reset circuit is released, clearing the
counter again and allowing the MCU to come out of reset.
7
8
A timer overflow function at the eighth counter stage makes timer interrupts
possible every 1024 internal clock cycles.
9
7.2 Timer Control and Status Register (TCSR)
10
Timer interrupt flags, timer interrupt enable bits, and real-time interrupt rate select
bits are in the read/write timer control and status register.
11
TCSR — Timer Control and Status Register
12
13
RESET
$0008
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
TOIE
RTIE
0
0
RT1
RT0
0
0
0
0
0
0
1
1
Figure 7-3. Timer Control and Status Register (TCSR)
14
15
16
17
18
19
20
TIMER
7-2
Rev. 2
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TOF — Timer Overflow Flag
This clearable, read-only bit becomes set when the first eight stages of the counter
roll over from $FF to $00. TOF generates a timer overflow interrupt request if
TOFE is also set. Clear TOF by writing a zero to it. Writing a one to TOF has no
effect.
RTIF — Real-Time Interrupt Flag
This clearable, read-only bit becomes set when the selected RTI output becomes
active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF
by writing a zero to it. Writing a one to RTIF has no effect.
2
3
4
5
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables timer overflow interrupts.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
Freescale Semiconductor, Inc...
1
6
7
RTIE — Real-Time Interrupt Enable
This read/write bit enables real-time interrupts
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
8
9
Bits 3 and 2 — Not used. Always read as zeros.
10
RT1, RT0 — Real-Time 1 and 0
These read/write bits select one of four real-time interrupt rates. See Table 7-1.
The real-time interrupt rate should be selected by reset initialization software. A
reset sets both RT1 and RT0, selecting the lowest real-time interrupt rate.
Changing the real-time interrupt rate near the end of the RTI period or during a
cycle in which the counter is switching can produce unpredictable results.
Because the selected RTI output drives the COP timer, changing the real-time
interrupt rate also changes the counting rate of the COP timer.
11
12
13
14
15
Table 7-1. Real-Time Interrupt Rate Selection
RT1:RT0
RTI Rate
RTI Period
(fop = 2 MHz)
COP Timeout Period
(-0/+1 RTI Period)
Minimum COP Timeout
Period ( fop = 2 MHz)
16
00
fop ÷ 214
8.2 ms
7 × RTI Period
57.3 ms
01
fop ÷
215
16.4 ms
7 × RTI Period
114.7 ms
17
10
fop ÷ 216
32.8 ms
7 × RTI Period
229.4 ms
11
fop ÷
65.5 ms
7 × RTI Period
458.8 ms
217
18
19
20
TIMER
Rev. 2
7-3
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7.3 COP Timer
1
Three counter stages at the end of the timer make up the computer operating
properly (COP) timer. (See Figure 7-1 .) The COP timer is a software error
detection system that automatically times out and resets the MCU if not cleared
periodically by a program sequence. Writing a zero to bit 0 of the COP register
clears the COP timer and prevents a COP timer reset. (See Figure 7-4.)
2
3
4
COPR — COP Register
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5
6
RESET
$0FF0
MC68HC05J1 Emulation Mode: $07F0
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
COPC
—
—
—
—
—
—
—
0
Figure 7-4. COP Register (COPR)
7
COPC — COP Clear
8
This write-only bit resets the COP timer. Reading address $0FF0 returns the
EPROM data at that address.
9
10
11
12
13
14
15
16
17
18
19
20
TIMER
7-4
Rev. 2
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1
2
SECTION 8
BOOTLOADER MODE
3
This section describes how to use the bootloader ROM to download to the on-chip
EPROM.
5
8.1 Bootloader ROM
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4
The bootloader ROM, located at addresses $0F01–$0FEF, contains routines for
copying to the on-chip EPROM from an external EPROM or from a personal
computer.
In MC68HC705J2 native mode, the bootloader copies to the 2 Kbyte space located
at EPROM addresses $0700–$0EFF, the MOR byte at location $0F00, and the user
vector addresses $0FF0–$0FFF. In MC68HC05J1 emulation mode, the bootloader
copies to the 1 Kbyte space located at EPROM addresses $0300–$06FF, the MOR
byte at location $0700, and the user vector addresses $07F0–$07FF. The addresses
of the copied code must correspond to the internal addresses to which the code is
copied. The bootloader ignores all other addresses.
6
7
8
9
10
11
The COP timer is automatically disabled in bootloader mode.
12
8.1.1 External EPROM Downloading
Figure 8-1 shows the circuit used to download to the on-chip EPROM from a 2764
EPROM. The bootloader circuit includes an external 12-bit counter to address the
EPROM containing the code to be copied.
13
14
Operation is fastest when unused external EPROM addresses contain $00.
15
16
17
18
19
20
BOOTLOADER MODE
Rev. 2
8-1
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1
MC68JC705J2
19
VPP
18
IRQ/VPP
PA0
1
17
OSC1
PA1
4 MHz
16
2
PA2
OSC2
15
PA3
14
PA4
10 M
13
PA5
12
15 pF
15 pF
PA6
11
PA7
2
3
4
2764
D0
D1
D2
D3
D4
D5
D6
D7
CE
VDD
5
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S1
OE
10 k
20
6
VDD 9
1 F
7
8 PB0
VDD
8
7 PB1
PROGRAM
9
VDD
RESET
6
RST
10 k
VSS
PB3
330
11
A12
CLK
VDD
10 k
1
5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
PB2
S2
VERIFY
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
10 k
4
PB4
3
PB5
330
10
MC14040B
10
2
3
CONNECT 2 AND 3 FOR
MC68HC705J2 NATIVE MODE.
CONNECT 1 AND 2 FOR
MC68HC05J1 EMULATION MODE.
Figure 8-1. Bootloader Circuit
12
13
The bootloader function begins when a rising edge occurs on the RESET pin while
the IRQ/VPP pin is at VPP, the PB1 pin is at logical one, and the PB0 pin is
grounded.
14
The PB2 pin selects the bootloader function, as the following table shows.
15
Table 8-1. Bootloader Function Selection
16
PB2
Bootloader Function
1
Program and Verify
17
0
Verify
18
19
20
BOOTLOADER MODE
8-2
Rev. 2
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Complete the following steps to bootload the MCU:
1. Turn off all power to the circuit.
1
2. Install the MCU and the EPROM.
3. Select the MCU mode:
a. Install a jumper between points 2 and 3 to program the MCU as an
MC68HC705J2.
b. Install a jumper between points 1 and 2 to program the MCU as an
MC68HC05J1.
2
3
4
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4. Select the bootloader function:
a. Open switch S2 to select the program and verify function.
b. Close switch S2 to select the verify only function.
5
5. Close switch S1 to reset the MCU.
6
6. Apply VDD to the circuit.
7. Apply the EPROM programming voltage, VPP, to the circuit.
7
8. Open switch S1 to take the MCU out of reset. During programming the
PROGRAM LED turns on. It turns off when the verification routine begins. If
verification is successful, the VERIFY LED turns on. If the bootloader finds an
error during verification, it puts the error address on the external address bus
and stops running.
9
10
9. Close switch S1 to reset the MCU.
10.
8
Remove the VPP voltage.
11
11. Remove the VDD voltage.
12
8.2 Host Downloading
The MC68HC05P8EVS board supports downloading user programs directly from a
personal computer. Refer to MC68HC05P8EVS Customer Specified Integrated
Circuit (CSIC) Evaluation System, Motorola document number BR735/D.
13
14
15
16
17
18
19
20
BOOTLOADER MODE
Rev. 2
8-3
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8.3 Mask Option Register (MOR)
1
The mask option register is an EPROM byte that contains three bits to control the
following options:
2
3
4
•
MC68HC05J1 emulation mode
•
External interrupt trigger sensitivity
•
COP timer (enable/disable)
The mask option register is programmable only when using the bootloader function
to download to the EPROM.
5
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MOR — Mask Option Register
6
7
8
$0F00
MC68HC05J1 Emulation Mode: $0700
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
J1
IRQ
COP
Figure 8-2. Mask Option Register (MOR)
9
J1 — MC68HC05J1 Emulation Mode Select
This bit can be read at any time, but can be programmed only by the bootloader.
1 = Emulation mode selected; MCU functions as MC68HC05J1
0 = (Erased state) MC68HC705J2 native mode selected
10
11
IRQ — Interrupt Request
12
This bit can be read at any time, but can be programmed only by the bootloader.
1 = IRQ trigger is both edge-sensitive and level-sensitive
0 = (Erased state) IRQ trigger is edge-sensitive only
13
COP — COP Timer Enable
14
This bit can be read at any time, but can be programmed only by the bootloader.
1 = COP timer enabled
0 = (Erased state) COP timer disabled
15
16
NOTE
17
To avoid unintentionally enabling any of the options in the MOR, the
user should ensure that location $0F00 of the 8K external EPROM
(2764) is programmed with either the appropriate value for the
options to be enabled or $00. This is necessary because the erased
state of an 8K external EPROM is $FF, whereas the erased state of
the MOR is $00.
18
19
20
BOOTLOADER MODE
8-4
Rev. 2
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1
2
SECTION 9
MC68HC05J1 EMULATION MODE
3
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This section describes how to use the MC68HC05J1 emulation mode to achieve
compatibility with MC68HC05J1 devices.
4
5
6
9.1 Bootloading
Use the bootloader function to put the MCU in MC68HC05J1 emulation mode. To
activate the emulation mode:
1. Connect pin PB5 to VDD in the bootloader circuit.
7
8
2. Program the J1 bit (in the mask option register) high.
9
9.2 MC68HC05J1 Emulation
In MC68HC05J1 emulation mode, the MCU operates as an MC68HC05J1 with the
following exceptions:
•
The emulation mode does not support the RC oscillator mask option of the
MC68HC05J1.
•
The emulation mode does not support the STOP disable mask option of the
MC68HC05J1.
•
The emulation mode has no self-check function.
10
11
12
13
14
15
16
17
18
19
20
MC68HC05J1 EMULATION MODE
Rev. 2
9-1
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9.3 Memory Map
1
Figure 9-1 shows the 2 Kbyte MC68HC05J1 emulation mode memory map.
2
3
$0000
$001F
$0020
4
I/O REGISTERS
32 BYTES
UNUSED
160 BYTES
5
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$00BF
$00C0
6
STACK RAM
64 BYTES
7
$00FF
$0100
8
UNUSED
512 BYTES
9
PORT A DATA REGISTER
PORT B DATA REGISTER
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
UNUSED
UNUSED
TIMER CONTROL & STATUS REGISTER
TIMER COUNTER REGISTER
UNUSED
•
•
•
UNUSED
EPROM PROGRAMMING REGISTER
UNUSED
UNUSED
RESERVED
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
•
•
•
$001B
$001C
$001D
$001E
$001F
$02FF
$0300
10
11
USER EPROM
1024 BYTES
12
13
$06FF
$0700
$0701
14
MASK OPTION REGISTER
BOOTLOADER ROM
239 BYTES
15
$07EF
$07F0
16
USER VECTORS
(EPROM)
16 BYTES
17
$07FF
COP REGISTER *
USER
EPROM
8 BYTES
TIMER INTERRUPT VECTOR (HIGH)
TIMER INTERRUPT VECTOR (LOW)
EXTERNAL INTERRUPT VECTOR (HIGH)
EXTERNAL INTERRUPT VECTOR (LOW)
SOFTWARE INTERRUPT VECTOR (HIGH)
SOFTWARE INTERRUPT VECTOR (LOW)
RESET VECTOR (HIGH)
RESET VECTOR (LOW)
$07F0
•
•
•
$07F7
$07F8
$07F9
$07FA
$07FB
$07FC
$07FD
$07FE
$07FF
*WRITING 0 TO BIT 0 OF $07F0 CLEARS
COP TIMER. READING $07F0 RETURNS
USER EPROM DATA.
18
19
Figure 9-1. MC68HC05J1 Emulation Mode Memory Map
20
MC68HC05J1 EMULATION MODE
9-2
Rev. 2
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1
2
SECTION 10
INSTRUCTION SET
3
4
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This section describes the M68HC705J1A addressing modes and instruction
types.
5
6
10.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
7
8
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
9
10
11
12
13
10.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent
instructions require no memory address and are one byte long.
10.1.2 Immediate
14
15
16
17
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
18
19
20
INSTRUCTION SET
Rev. 2
10-1
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10.1.3 Direct
1
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
2
3
4
10.1.4 Extended
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5
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
6
7
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
8
9
10.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
10
11
12
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
13
14
10.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data with
variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
15
16
17
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
18
19
20
INSTRUCTION SET
10-2
Rev. 2
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10.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the high
byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
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Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing the Motorola assembler determines the
shortest form of indexed addressing.
10.1.8 Relative
1
2
3
4
5
6
7
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch condition
is not true, the CPU goes to the next instruction. The offset is a signed, two’s
complement byte that gives a branching range of –128 to +127 bytes from the
address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
8
9
10
11
12
10.2 Instruction Types
13
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
14
15
16
17
18
19
20
INSTRUCTION SET
Rev. 2
10-3
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10.2.1 Register/Memory Instructions
1
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 10-1 lists the register/memory instructions.
2
3
Table 10-1. Register/Memory Instructions
4
Instruction
Freescale Semiconductor, Inc...
5
6
7
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
8
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
9
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from
Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
10
11
12
13
14
15
16
17
18
19
20
INSTRUCTION SET
10-4
Rev. 2
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10.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 10-2 lists the
read-modify-write instructions.
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Mnemonic
Arithmetic Shift Left
ASL
Arithmetic Shift Right
ASR
Clear Bit in Memory
BCLR
Set Bit in Memory
BSET
Clear
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
2
3
4
Table 10-2. Read-Modify-Write Instructions
Instruction
1
5
6
7
8
9
10
11
12
13
14
10.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is met.
If the test condition is not met, the branch is not performed. All branch instructions
use relative addressing.
Bit test and branch instructions cause a branch based on the state of any readable
bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of the
byte to be tested is in the byte following the opcode. The third byte is the signed
offset byte. The CPU finds the conditional branch destination by adding the third
byte to the program counter if the specified bit tests true. The bit to be tested and
INSTRUCTION SET
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10-5
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15
16
17
18
19
20
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its condition (set or clear) is part of the opcode. The span of branching is from –128
to +127 from the address of the next location after the branch instruction. The CPU
also transfers the tested bit to the carry/borrow bit of the condition code register.
See Table 10-3 lists the jump and branch instructions.
1
2
3
Table 10-3. Jump and Branch Instructions
Instruction
4
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5
6
7
8
9
10
11
12
13
14
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
15
BRCLR
Branch Never
BRN
Branch if Bit Set
16
17
Mnemonic
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
18
19
20
INSTRUCTION SET
10-6
Rev. 2
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10.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 10-4 lists these instructions.
Freescale Semiconductor, Inc...
Clear Bit
2
3
4
Table 10-4. Bit Manipulation Instructions
Instruction
1
Mnemonic
5
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
6
7
BSET
8
10.2.5 Control Instructions
9
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 10-5, use inherent addressing.
10
11
Table 10-5. Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
12
13
14
15
16
17
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
18
19
20
INSTRUCTION SET
Rev. 2
10-7
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10.3 Instruction Set Summary
1
Table 10-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
2
6
7
8
9
10
11
12
13
14
15
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
20
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
2
3
4
5
4
3
↕ — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
38
48
58
68
78
dd
— — ↕ ↕ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
C
0
b7
b0
C
b7
— — ↕ ↕ ↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Description
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
18
19
↕ — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
16
17
Opcode
Freescale Semiconductor, Inc...
5
Operation
Address
Mode
4
Source
Form
Operand
Table 10-6. Instruction Set Summary
3
INSTRUCTION SET
10-8
Rev. 2
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Address
Mode
Opcode
Operand
Cycles
Table 10-6. Instruction Set Summary (Continued)
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry
Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or
Same
Freescale Semiconductor, Inc...
Source
Form
Operation
Description
Effect on
CCR
H I N Z C
1
2
3
4
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
BIH rel
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
10
11
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
REL
INSTRUCTION SET
Rev. 2
10-9
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5
6
7
8
9
12
13
14
15
16
17
18
19
20
Freescale Semiconductor, Inc.
Table 10-6. Instruction Set Summary (Continued)
Operand
Cycles
2
Operation
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Description
Effect on
CCR
H I N Z C
3
Mn ← 1
Address
Mode
Source
Form
Opcode
1
BSET n opr
Set Bit n
6
BSR rel
Branch to
Subroutine
7
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
— — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
— — ↕ ↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — ↕ ↕ 1
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
— — ↕ ↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
4
Freescale Semiconductor, Inc...
5
8
9
10
11
12
13
14
15
16
17
18
19
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
— — 0 1 —
— — ↕ ↕ —
2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
20
INSTRUCTION SET
10-10
Rev. 2
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JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Cycles
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operand
Freescale Semiconductor, Inc...
INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
Opcode
Source
Form
Address
Mode
Table 10-6. Instruction Set Summary (Continued)
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
5
3
3
6
5
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
38
48
58
68
78
dd
— — ↕ ↕ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
0 — — — 0
INH
42
— — ↕ ↕ ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
Effect on
CCR
Description
H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
PC ← Jump Address
Unconditional Jump
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator
with Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shift Right
MUL
Unsigned Multiply
C
0
b7
Negate Byte
(Two’s Complement)
NOP
No Operation
— — — — —
— — — — —
— — ↕ ↕ —
X ← (M)
b0
0
C
b7
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕ ↕ —
— — 0 ↕ ↕
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
— — — — —
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
ii
ff
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
20
10-11
For More Information On This Product,
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2
5
3
3
6
5
INSTRUCTION SET
Rev. 2
1
19
Freescale Semiconductor, Inc.
3
4
Freescale Semiconductor, Inc...
5
6
7
8
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
11
12
13
14
15
16
17
18
19
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
39
49
59
69
79
dd
— — ↕ ↕ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
H I N Z C
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
C
b7
b0
ff
2
3
4
5
4
3
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕
INH
80
6
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
9
10
— — ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
Cycles
2
Operation
Opcode
Source
Form
Address
Mode
1
Operand
Table 10-6. Instruction Set Summary (Continued)
C
b7
— — ↕ ↕ ↕
b0
ff
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory
Byte and Carry Bit
from Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕ ↕ —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— — ↕ ↕ —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
Store Index
Register In Memory
M ← (A)
M ← (X)
20
INSTRUCTION SET
10-12
Rev. 2
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SWI
Subtract Memory
Byte from
Accumulator
Transfer
Accumulator to
Index Register
— — ↕ ↕ ↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
X ← (A)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte
for Negative or Zero
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock
and Enable
Interrupts
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
A ← (A) – (M)
(M) – $00
A ← (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
Cycles
H I N Z C
Software Interrupt
TAX
Description
Opcode
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
Table 10-6. Instruction Set Summary (Continued)
2
3
4
5
4
3
1
2
3
4
5
INH
83
10
6
7
2
8
4
3
3
5
4
9
— — — — —
INH
97
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
11
— ↕ — — —
INH
8F
2
12
dd
ff
10
13
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
14
15
16
17
18
19
20
INSTRUCTION SET
Rev. 2
10-13
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10-14
For More Information On This Product,
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
BCLR7
DIR 2
5
BSET7
DIR 2
5
BCLR6
DIR 2
5
BSET6
DIR 2
5
BCLR5
DIR 2
5
BSET5
DIR 2
5
BCLR4
DIR 2
5
BSET4
DIR 2
5
BCLR3
DIR 2
5
BSET3
3
REL 2
3
BCC
REL 2
3
BLS
REL
3
BHI
REL
3
BRN
REL 2
3
BRA
2
5
DIR 1
5
ASR
DIR 1
5
ROR
5
DIR 1
LSR
DIR 1
5
COM
1
3
INH 1
3
ASRA
INH 1
3
RORA
3
INH 1
LSRA
INH 1
3
COMA
INH
3
MUL
11
INH 1
NEGA
4
INH
3
3
INH 2
3
ASRX
INH 2
3
RORX
3
INH 2
LSRX
INH 2
3
COMX
INH 2
NEGX
5
INH
5
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
3
3
INH 1
CLRA
INH 1
TSTA
INH 1
3
INCA
INH 1
DECA
INH 1
3
ROLA
INH 1
3
INH 2
3
3
3
INH 2
CLRX
INH 2
TSTX
INH 2
3
INCX
INH 2
DECX
INH 2
3
ROLX
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
5
DIR 1
NEG
3
DIR
6
IX1 1
6
6
IX1 1
6
IX1 1
IX1 1
5
CLR
TST
INC
IX1 1
DEC
IX1 1
6
ROL
ASR
ROR
LSR
COM
NEG
7
IX
5
5
IX
5
IX
5
5
IX
IX 1
5
IX
IX
4
5
IX
IX
5
9
10
1
1
1
1
1
1
1
INH 1
WAIT
INH
2
STOP
2
INH
SWI
INH
RTS
INH
6
RTI
8
INH
2
2
2
2
2
2
2
2
INH
TXA
2
2
MSB
0
4
EXT 3
STX
EXT 3
5
LDX
EXT 3
4
JSR
EXT 3
6
JMP
EXT 3
3
ADD
EXT 3
4
ORA
EXT 3
4
ADC
EXT 3
4
EOR
EXT 3
4
STA
EXT 3
5
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
SUB
C
EXT
3
IX2 2
5
IX2 2
6
STX
LDX
JSR
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
IX2 2
5
IX2 2
5
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
BIT
5
IX2 2
5
SUB
D
IX2
IX1 1
4
IX1 1
5
STX
LDX
JSR
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
IX1 1
3
ADD
IX1 1
4
ORA
IX1 1
4
ADC
IX1 1
4
EOR
STA
LDA
IX1 1
4
IX1 1
4
AND
IX1 1
4
CPX
IX1 1
4
SBC
IX1 1
4
CMP
BIT
5 Number of Cycles
DIR Number of Bytes/Addressing Mode
4
IX1 1
4
SUB
E
IX1
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
DIR 3
3
DIR 3
3
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
BIT
3
DIR 3
3
SUB
B
DIR
Register/Memory
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
0
2
REL 2
2
BSR
6
IMM 2
ADD
IMM 2
2
ORA
IMM 2
2
ADC
IMM 2
2
EOR
2
IMM 2
LDA
IMM 2
2
BIT
IMM 2
2
AND
IMM 2
2
CPX
IMM 2
2
SBC
IMM 2
2
CMP
IMM 2
2
SUB
A
IMM
LSB
2
INH 2
NOP
INH
2
RSP
INH 2
2
SEI
INH 2
2
INH 2
2
SEC
INH 2
2
CLC
CLI
2
INH
2
TAX
9
INH
Control
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
IX
5
1
IX 1
5
1
IX 1
ASL/LSL
IX1 1
6
ASR
IX1 1
6
ROR
6
IX1 1
IX1 1
6
COM
LSR
6
IX1 1
NEG
6
IX1
Read-Modify-Write
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET2
DIR 2
5
BCLR1
DIR 2
5
BSET1
DIR 2
5
BCLR0
DIR 2
5
BSET0
1
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
3
BRCLR7
3
BRSET7
3
BRCLR6
3
BRSET6
3
BRCLR5
3
BRSET5
3
BRCLR4
3
BRSET4
3
BRCLR3
3
BRSET3
3
BRCLR2
3
BRSET2
3
BRCLR1
3
BRSET1
3
BRCLR0
DIR 2
5
BRSET0
0
3
0
MSB
LSB
Branc
Bit
h
Manipulation
DIR
DIR
REL
Table 10-7. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
INSTRUCTION SET
Rev. 2
Freescale Semiconductor, Inc.
1
2
SECTION 11
ELECTRICAL SPECIFICATIONS
3
This section contains parametric and timing information.
4
Freescale Semiconductor, Inc...
11.1 Maximum Ratings
5
The MCU contains circuitry that protects the inputs against damage from high static
voltages; however, do not apply voltages higher than those shown in Table 11-1.
Keep Vin and Vout within the range VSS ≤ (Vin or Vout) ≤ VDD. Connect unused inputs
to the appropriate logical voltage level, either VSS or VDD.
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
All Pins in Normal Operation
IRQ/VPP Pin in Bootloader Mode
Vin
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to 2 × VDD + 0.3
V
EPROM Programming Voltage (IRQ/VPP Pin)
VPP
16.75
V
Current Drain Per Pin (ExcludingVDD and VSS)
I
25
mA
0 to +70
–40 to +85
–40 to +105
°C
–65 to +150
°C
Operating Temperature Range
MC68HC705J2P, DW (Standard)
MC68HC705J2CP, CDW (Extended)
MC68HC705J2VP, VDW
Storage Temperature Range
7
8
Table 11-1. Maximum Ratings
Rating
6
TA
TSTG
9
10
11
12
13
14
11.2 Thermal Characteristics
15
Table 11-2. Thermal Resistance
Characteristic
Thermal Resistance
PDIP
SOIC
Symbol
Value
Unit
16
θJA
60
60
°C/W
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 2
11-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
11.3 Power Considerations
1
The average chip-junction temperature, TJ, in °C, can be obtained from:
2
TJ = TA + (PD × θJA)
(1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
3
4
Freescale Semiconductor, Inc...
5
6
For most applications PI/O << PINT and can be neglected.
7
The following is an approximate relationship between PD and TJ (neglecting PI/O):
PD = K ÷ (TJ + 273 °C)
8
(2)
Solving equations (1) and (2) for K gives:
9
K = PD × (TA + 273 °C) + θJA × (PD)2
10
(3)
where K is a constant pertaining to the particular part. K can be determined from
equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of
K, the values of PD and TJ can be obtained by solving equations (1) and (2)
iteratively for any value of TA.
11
12
13
14
15
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
11-2
Rev. 2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
11.4 DC Electrical Characteristics (VDD = 5.0 Vdc)
1
Table 11-3. DC Electrical Characteristics (VDD = 5.0 Vdc)
Characteristic
Freescale Semiconductor, Inc...
Output Voltage
Iload = 10.0 µA
Iload = –10.0 µA
Symbol
Min
Typ
Max
Unit
2
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
3
VDD – 0.8
—
—
Output High Voltage (Iload = –0.8 mA)
PA7–PA0, PB5–PB0
VOH
Output Low Voltage (Iload = 1.6 mA)
PA7–PA0, PB5–PB0
VOL
Input High Voltage
PA7–PA0, PB5–PB0, IRQ/VPP, RESET, OSC1
VIH
Input Low Voltage
PA7–PA0, PB5–PB0, IRQ/VPP, RESET, OSC1
VIL
—
—
0.4
0.7 × VDD
—
VDD
VSS
—
—
—
V
4
V
V
5
0.2 × VDD
V
6
5.0
1.3
7.0
2.5
mA
mA
7
—
—
2.0
—
30
100
µA
µA
8
µA
9
Supply Current (See NOTES.)
Run
Wait
Stop
25 °C
–40 to +85 °C
IDD
I/O Ports High-Z Leakage Current
PA7–PA0, PB5–PB0
IOZ
—
—
10
Input Current
RESET, IRQ/VPP, OSC1
Iin
—
—
±1
Capacitance
Ports (as input or output)
RESET, IRQ/VPP
Cout
Cin
—
—
—
—
12
8
pF
Programming Voltage
VPP
16.25
16.5
16.75
V
IPP
—
5
10
mA
tEPGM
4
—
—
ms
Programming Current
Programming Time/Byte
µA
10
11
NOTES:
1. Typical values at midpoint of voltage range, 25 °C only.
2. Run (operating) IDD and wait IDD measured using external square wave clock source (fosc = 4.2 MHz), all
inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
3. Wait IDD and Stop IDD: all ports configured as inputs; VIL = 0.2 V, VIH = VDD – 0.2 V.
4. Stop IDD measured with OSC1 = VSS.
5. Standard temperature range is 0 °C to 70 °C.
6. OSC2 capacitance linearly affects Wait IDD .
7. Programming voltage measured at IRQ/VPP pin.
12
13
14
15
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 2
11-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
1
11.5 DC Electrical Characteristics (VDD = 3.3 Vdc)
Table 11-4. DC Electrical Characteristics (VDD = 3.3 Vdc)
2
Characteristic
3
4
Freescale Semiconductor, Inc...
5
6
7
8
9
10
11
12
13
14
15
Symbol
Min
Typ
Max
Unit
Output Voltage
Iload = 10.0 µA
Iload = –10.0 µA
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output High Voltage (Iload = –0.2 mA)
PA7–PA0, PB5–PB0
VOH
VDD – 0.3
—
—
Output Low Voltage (Iload = 0.4 mA)
PA7–PA0, PB5–PB0
VOL
—
—
0.3
Input High Voltage
PA7–PA0, PB5–PB0, IRQ/VPP, RESET, OSC1
VIH
0.7 × VDD
—
VDD
Input Low Voltage
PA7–PA0, PB5–PB0, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
1.3
0.7
2.0
1.0
mA
mA
—
—
1.0
—
20
50
µA
µA
Supply Current (See NOTES.)
Run
Wait
Stop
25 °C
–40 to +85 °C
IDD
I/O Ports High-Z Leakage Current
PA7–PA0, PB5–PB0
Ioz
—
—
±10
Input Current
RESET, IRQ/VPP, OSC1
Iin
—
—
±1
Cout
Cin
—
—
—
—
12
8
Capacitance
Ports (as input or output)
RESET, IRQ/VPP
V
V
V
µA
µA
pF
pF
NOTES:
1. Typical values at midpoint of voltage range, 25 °C only.
2. Run (operating) IDD and Wait IDD measured using external square wave clock source (fosc = 2 MHz), all
inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
3. Wait IDD and Stop IDD: all ports configured as inputs; VIL = 0.2 V, VIH = VDD – 0.2 V.
4. Stop IDD measured with OSC1 = VSS.
5. Standard temperature range is 0 °C to 70 °C.
6. OSC2 capacitance linearly affects Wait IDD .
16
VDD
17
R2
18
PINS
TEST POINT
VDD
R1
R2
C
4.5 V
3.26 k
2.38 k
50 pF
3.0 V
10.91 k
6.32 k
50 pF
PA7–PA0, PB5–PB0
C
19
20
R1
Figure 11-1. Equivalent Test Load
ELECTRICAL SPECIFICATIONS
11-4
Rev. 2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
800 mV
SE
OT
C
25
200 mV
EE
C (S
–40
E
OT
1)
N
IN
G
SS
OC
E
2
AL
MI
N
NO
TE
EE
C
0
VDD = 5.0 V
1)
3
NO
(S
–4
4
VDD = 3.3 V
100 mV
0
1
PR
NO
EE
300 mV
200 mV
100 mV
5
0
0
–1.0 mA
–2.0 mA
–3.0 mA
–4.0 mA
–5.0 mA
0
–1.0 mA
–2.0 mA
IOH
–3.0 mA
–4.0 mA
–5.0 mA
IOH
6
NOTES:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V vs I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) 800 mV @ IOL = –0.8 mA.
3. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) 300 mV @ IOL = –0.2 mA.
Figure 11-2. Typical High-Side Driver Characteristics
7
8
9
10
400 mV
EE
C (S
–40
50 mV
N
SS
CE
0
100 mV
VDD = 5.0 V
12
E
EE
25
150 mV
1)
ING
EE
C (S
85
VOL
C
25
100 mV
E
OT
200 mV
CN
SS
CE
LP
NA
NO
MI
C(
85
150 mV
250 mV
RO
EN
SE
200 mV
NOT
G
IN
)
E1
OT
250 mV
SE
300 mV
RO
E2
11
3
LP
OT
300 mV
TE
O
EN
350 mV
INA
EN
350 mV
E 1)
SE
OM
400 mV
VOL
Freescale Semiconductor, Inc...
TE
1
)
NO
400 mV
C
85
300 mV
3
P
500 mV
25
AL
N
MI
C
400 mV
C
RO
C (S
E1
OT
(S
E
EN
500 mV
600 mV
G
IN
S
ES
NOT
E
)
600 mV
VDD – VOH
700 mV
E2
VDD – VOH
700 mV
85
EN
SEE
800 mV
C
T
NO
(S
14
–4
VDD = 3.3 V
50 mV
0
13
1)
15
0
0
2.0 mA
4.0 mA
6.0 mA
IOL
8.0 mA
10.0 mA
0
2.0 mA
4.0 mA
6.0 mA
IOL
8.0 mA
10.0 mA
16
NOTES:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V vs I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL 400 mV @ IOL = 1.6 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL 300 mV @ IOL = 0.4 mA.
17
18
19
Figure 11-3. Typical Low-Side Driver Characteristics
20
ELECTRICAL SPECIFICATIONS
Rev. 2
11-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
5
V
.5
=5
4
4.0 mA
V
DD
SUPPLY CURRENT (IDD)
3
T = 25 C
WAIT MODE
3.0 mA
.5
=4
D
VD
V
V DD
2.0 mA
.6
=3
V DD
6
1.0 mA
7
0
.0 V
=3
.5
V
V
=4
DD
.6 V
V DD
=3
V DD
0.5 mA
.0 V
=3
0
0
8
V
1.0 mA
.5
V
5.0 mA
=5
2
1.5 mA
T = 25 C
RUN MODE
(OPERATING)
V
DD
6.0 mA
SUPPLY CURRENT (IDD)
1
500 kHz
1 MHz
1.5 MHz
INTERNAL CLOCK FREQUENCY
(XTAL 2)
2 MHz
0
500 kHz
1 MHz
1.5 MHz
INTERNAL CLOCK FREQUENCY
(XTAL 2)
2 MHz
Figure 11-4. Typical Supply Current vs Clock Frequency
9
7.0 mA
T = –40 to +85 C
VDD = 5 V 10%
10
6.0 mA
11
15
T = –40 to +85 C
VDD = 3.3 V 10%
4.0 mA
4.0 mA
N
3.0 mA
2.0 mA
IT
WA
16
1.0 mA
17
0
18
2.0 mA
N
RU
IT
WA
0
500 kHz
1 MHz
1.5 MHz
INTERNAL CLOCK FREQUENCY
(XTAL 2)
2 MHz
NOTE: Maximum STOP IDD = 100 A when VDD = 5 V.
20
3.0 mA
1.0 mA
0
19
SUPPLY CURRENT (IDD)
14
5.0 mA
RU
13
SUPPLY CURRENT (IDD)
12
5.0 mA
0
500 kHz
1 MHz
1.5 MHz
INTERNAL CLOCK FREQUENCY
(XTAL 2)
2 MHz
NOTE: Maximum STOP IDD = 50 A when VDD = 3 V.
Figure 11-5. Maximum Supply Current vs Clock Frequency
ELECTRICAL SPECIFICATIONS
11-6
Rev. 2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
11.6 Control Timing (VDD = 5.0 Vdc)
1
Table 11-5. Control Timing (VDD = 5.0 Vdc)
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc; TA = TL to TH)
Symbol
Min
Max
Unit
2
Oscillator Frequency
Crystal Option
External Clock Option
fosc
—
dc
4.2
4.2
MHz
3
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
fop
—
dc
2.1
2.1
MHz
4
Cycle Time
tcyc
480
—
ns
RESET Pulse Width
tRL
1.5
—
tcyc
tRESL
4.0
—
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
(NOTE 2)
—
tcyc
tOH, tOL
90
—
ns
tEPGM
4
—
ms
Freescale Semiconductor, Inc...
Characteristic
Timer Resolution (NOTE 1)
OSC1 Pulse Width
Programming Time per Byte
5
6
7
NOTES:
1. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
2. The minimum period tILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 19 tcyc.
8
9
10
11
IRQ (PIN)
tILIH
12
tILIL
Edge-Sensitive Trigger — The minimum tILIH is either 125 ns (VDD = 5 V) or 250 ns (VDD = 3 V). The period tILIL
should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 19 tcyc cycles.
IRQ 1
13
14
tILIH
15
NORMALLY
USED WITH
WIRED–OR
CONNECTION
IRQ n
IRQ (MCU)
16
Edge and Level-Sensitive Trigger — If IRQ remains low after interrupt is serviced, the next interrupt is recognized.
17
18
Figure 11-6. External Interrupt Timing
19
20
ELECTRICAL SPECIFICATIONS
Rev. 2
11-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
1
11.7 Control Timing (VDD = 3.3 Vdc)
Table 11-6. Control Timing (VDD = 3.3 Vdc)
2
(VDD = 3.3 Vdc 10%, VSS = 0 Vdc; TA = TL to TH)
Characteristic
Symbol
Min
Max
Unit
4
Oscillator Frequency
Crystal Option
External Clock Option
fosc
—
dc
2.0
2.0
MHz
5
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
fop
—
dc
1.0
1.0
MHz
Cycle Time
tcyc
1000
—
ns
RESET Pulse Width
tRL
1.5
—
tcyc
Freescale Semiconductor, Inc...
3
6
Timer Resolution (NOTE 1)
7
Interrupt Pulse Width Low (Edge-Triggered)
8
OSC1 Pulse Width
Interrupt Pulse Period
tRESL
4.0
—
tcyc
tILIH
250
—
ns
tILIL
(NOTE 2)
—
tcyc
tOH, tOL
400
—
ns
NOTES:
1. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
2. The minimum period tILIL should not be less than the number of cycle times it takes to execute
the interrupt service routine plus 19 tcyc.
9
10
11
12
13
14
15
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
11-8
Rev. 2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
OSC1 1
RESET
IRQ 2
IRQ 3
1
tRL
2
tILIH
3
tILCH
4064 tcyc
4
5
Freescale Semiconductor, Inc...
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
FFE 4
FFE 4
FFE 4
6
FFF 4
7
RESET OR INTERRUPT
VECTOR FETCH
NOTES:
1. Represents internal gating of OSC1 pin.
2. IRQ pin edge-sensitive mask option.
3. IRQ pin level and edge-sensitive mask option.
4. Reset vector address of MC68HC705J2 native mode shown as timing example.
8
9
Figure 11-7. STOP Recovery Timing
10
11
12
13
14
15
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 2
11-9
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1
tVDDR
VDD
2
3
POR THRESHOLD (TYPICALLY 1–2 V)
OSC1 PIN
4
Freescale Semiconductor, Inc...
5
6
7
8
9
4064 tcyc
INTERNAL
CLOCK 1
INTERNAL
ADDRESS
BUS 1
0FFE2
0FFE2
0FFE2
0FFE2
0FFE2
INTERNAL
DATA
BUS 1
0FFE2
NEW
PCH
0FFF 3
NEW
PCL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
3. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
10
Figure 11-8. Power-On Reset Timing
11
12
13
14
15
16
17
18
INTERNAL
CLOCK 1
INTERNAL
ADDRESS
BUS 1
0FFE3
INTERNAL
DATA
BUS 1
0FFE3
0FFE3
0FFE3
NEW
PCH
0FFF 4
NEW PC
NEW
PCL
DUMMY
NEW PC
OP
CODE
tRL
RESET 2
NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
3. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
4. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
19
Figure 11-9. External Reset Timing
20
ELECTRICAL SPECIFICATIONS
11-10
Rev. 2
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1
2
SECTION 12
MECHANICAL SPECIFICATIONS
3
Freescale Semiconductor, Inc...
The MC68HC705J2 is available in the following packages:
•
738-03 — plastic dual in-line package (PDIP)
•
751D-04 — small outline integrated circuit (SOIC)
•
732-03 — ceramic DIP (Cerdip) (windowed)
4
5
6
The following figures show the latest packages at the time of this publication. To make sure
that you have the latest package specifications, contact one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
7
8
9
10
Worldwide Web (wwweb) at http://design-net.com
11
Follow Mfax or Worldwide Web on-line instructions to retrieve the current mechanical
specifications.
12
13
14
15
16
17
18
19
20
MECHANICAL SPECIFICATIONS
Rev. 2
12-1
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12.1 Plastic Dual In-Line Package (DIP)
1
2
-A-
3
20
11
1
10
B
4
Freescale Semiconductor, Inc...
5
! ! $
! ! ! #
! " C
-T-
K
M
E
6
L
G
N
F
J 20 PL
D 20 PL
7
8
! ! °
°
°
°
Figure 12-1. MC68HC705J2P (Case 738-03)
9
10
11
12
13
14
15
16
17
18
19
20
MECHANICAL SPECIFICATIONS
12-2
Rev. 2
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Freescale Semiconductor, Inc.
12.2 Small Outline Integrated Circuit (SOIC)
-A20
! ! %
! !
! "
!" $" !" ! "
!" #
!" !! $ ! $" ! !
11
-B-
P 10 PL
1
10
D
20 PL
! J
F
Freescale Semiconductor, Inc...
R X 45°
C
-TG
18 PL
K
M
°
°
°
°
1
2
3
4
5
6
7
8
Figure 12-2. MC68HC705J2DW (Case 751D-04)
9
10
11
12
13
14
15
16
17
18
19
20
MECHANICAL SPECIFICATIONS
Rev. 2
12-3
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Freescale Semiconductor, Inc.
12.3 Ceramic DIP (Cerdip)
1
2
3
4
20
11
1
10
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
5
Freescale Semiconductor, Inc...
A
6
L
C
F
7
N
H
8
D
G
K
J
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040
SEATING
PLANE
9
Figure 12-3. MC68HC705J2S (Case 732-03)
10
11
12
13
14
15
16
17
18
19
20
MECHANICAL SPECIFICATIONS
12-4
Rev. 2
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MC68HC705J2/D