Freescale Semiconductor Technical Data Document Number: MC33884 Rev. 4.0, 11/2006 Switch Monitor Interface 33884 The 33884 Switch Monitor Interface is a monolithic silicon integrated circuit (IC) to perform switch monitoring functions. The device provides efficient interface between electrical switches and low voltage microprocessors. The 33884 supplies switch contact pull-up and pull down current while monitoring the input voltage level. All inputs are protected for transients when implemented with an appropriate static discharge capacitor used on the inputs. There are four modes of operation: Sleep, Normal, Polling, and Polling + INT Timer. SWITCH MONITOR INTERFACE The Polling and Timer modes are similar, except the Timer mode has the addition of an interrupt that is sent to the microprocessor if a switch is sensed closed, or upon the internal interrupt timer times out. An interrupt is ultimately sent to the microprocessor. All modes of operation are easily programmed via the Serial Peripheral Interface (SPI) control. DW SUFFIX EG (PB-FREE) SUFFIX 98ASB42344B 24-PIN SOICW Features • Full Operation with 7.0 V < VPWR < 26 V, Limited Operation with ORDERING INFORMATION 5.5 V < VPWR < 7.0 V Temperature • Input Voltage Range: -14 V to 40 V Device Package Range (TA) • Interface Directly to Microprocessors Using SPI Protocol • Wake Up on Change of Monitored Switch Status MC33884DW/R2 -40°C to 105°C 24 SOICW • Programmable Wetting Current MCZ33884EG/R2 • Four Switch-to-Ground Switches • Six (Fixed Function) Inputs Monitoring Six Switch-to-Ground Switches • Two (Fixed Function) Inputs Monitoring Two Switch-to-Battery Switches • Quiescent Current in Sleep Mode < 10 µA • Reset Input Defaults the Device to Sleep Mode • Pb-Free Packaging Designated by Suffix Code EG VPWR 33884 2 VPWR Sense Inputs 4 GND / VPWR Sense Inputs 6 GND Sense Inputs SB1 SB2 SP1 SP2 SP3 SP4 SG1 SG2 SG3 SG4 SG5 SG6 VDD VPWR VDD MCU VDD CS SI SO SCLK INT RESET GND VBG CS MOSI MISO CLK INT RESET GND SYNC MASL Figure 1. 33884 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM SP1 SP2 SP3 SP4 Switch-to-Ground and Switch-to-Battery Sense Inputs (x4) SG1 SG2 SG3 SG4 SG5 SG6 Switch-to-Ground Sense Inputs (x6) SB1 SB2 Switch-to-Battery Sense Inputs (x2) Programmable Input Blocks (1-4) Metallic or Non-metallic Enable or Disable Input Block (Tri-State) Fixed Input Blocks GND (1-6) SPI Decode Switch-Ground, Metallic or Nonmetallic, Enable or Disable FIB (Tri-State) PIB Configure, FIB/PIB Tri-State FIB/PIB Metallic Fixed Input Blocks Battery (1-2) Switch-Batt, Metallic or Non-Metallic, Enable or Disable FIB (Tri-State) SPI Interface CS SI SO SCLK SPI Encode Mode Switch Status VDD VPWR VSS VDD, V+ Distribution (To all input blocks) Quiescent Current Control Mode Control Normal, Polling, Sleep INT Polling Mode VBG Oscillator RST Wake Up Slave Sync SYNC Master/Slave Select MASL Figure 2. 33884 Simplified Block Diagram 33884 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VDD SO SI SP1 SG1 SG2 SG3 SB1 SP2 MASL VPWR VSS 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 SCLK CS VBG SP4 SG6 SG5 SG4 SB2 SP3 INT SYNC RST Figure 3. 33884 Pin Connections Table 1. 33884 Pin Definitions Pin Number Pin Name Formal Name Definitions 1 VDD Voltage Power 2 SO Serial Output This pin is the SPI data out. 3 SI Serial Input This pin provides data input. 4 SP1 Switch Input One 5 SG1 Switch-to-Ground Inputs One This pin is one of six and are switch-to-ground inputs only. 6 SG2 Switch-to-Ground Inputs Two This pin is one of six and are switch-to-ground inputs only. 7 SG3 Switch-to-Ground Inputs Three This pin is one of six and are switch-to-ground inputs only. 8 SB1 Switch-to Battery One 9 SP2 Switch Input Two 10 MASL Master/Slave 11 VPWR Voltage Power 12 VSS Voltage SS 13 RST Reset 14 SYNC Synchronization 15 INT Interrupt 16 SP3 Switch Input Three 17 SB2 Switch-to-Battery Two 18 SG4 Switch-to-Ground Inputs Four This pin is one of six and are switch-to-ground inputs only. 19 SG5 Switch-to-Ground Inputs Five This pin is one of six and are switch-to-ground inputs only. 20 SG6 Switch-to-Ground Inputs Four This pin is one of six and are switch-to-ground inputs only. 21 SP4 Switch Input One This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. 22 VBG Bandgap Voltage This pin.... This pin is 5.0 V logic supply. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin is one of two, and senses inputs only. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin identifies which device will be master and which will be slave. This pin is the power source. This pin is a ground. This pin is active low reset input to the device. This pin is used by the slave IC during the Polling mode. This pin is an interrupt output from the device. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin is one of two, and senses inputs only. 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33884 Pin Definitions Pin Number Pin Name Formal Name Definitions 23 CS Chip Select This pin is transmits communication to the device. 24 SCLK Serial Clock This pin clocks the internal 16-bit Shift register of the device. 33884 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit VDD -0.3 to 7.0 VDC VPWR -16 to 50 VDC Switch Input Voltage Range VSI -14 to 40 VDC Recommended Frequency of SPI Operation fSPI 3.0 MHz Human Body Model (3) (4) VESD1 4000 Machine Model (3) (5) VESD2 200 TSTG -55 to 150 °C TC -40 to 105 °C TJ -40 to 150 °C TPPRT Note 7. °C PθJ-A 107 °C/W Power Supply Voltage CS, SI, SO, SCLK, RST, MASL, SYNC, INT (1) VPWR Supply Voltage (1) ESD Voltage (2) V Storage Temperature Operating Case Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow (6) (7) , Thermal Resistance (Junction-to-Ambient) Notes 1 Exceeding these limits may cause malfunction or permanent damage to the device. 2 ESD data available upon request. 3 ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω) and ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 4 5 All pins are tested individually. 1 kV on VPWR and VDD when connected together. See page three. 6 Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 7. 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 105°C, unless otherwise noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.) Characteristic Symbol Min Typ Max Unit Quasi-Functional (8) VPWR(QF) 5.5 — 7.0 Fully Operational VPWR(FO) 7.0 IPWR(ON) — 100 300 µA I(SS) — 2.0 10 µA — 26 — µA POWER INPUT Supply Voltage Range Supply Current Normal Mode (IDD + IPWR) (All switches open) Supply Current Sleep State (IDD(SS) + IPWR(ON)) V Supply Current Periodic Mode (Polling at 30-50 ms period) (All switches open) 26 Logic Supply Voltage VDD 4.75 — 5.25 V Bandgap Voltage Output Pin (Tested with 130 kΩ ± 0.1% resistor) VBG 1.18 1.26 1.4 V Switch Input Pulse Wetting Current Switch to Battery IW(BAT) 7.5 14 25 mA Switch Input Pulse Wetting Current Switch to Ground IW(GND) -7.5 -14 -25 mA Switch Input Sustain Current Switch to Battery IS(BAT) 0.4 0.75 1.25 mA Switch Input Sustain Current Switch to Ground IS(GND) -0.4 -0.75 -1.25 mA Switch Input Tri-State Input Current IT(SWT) -10 — 10 µA Switch Input Switch Detection Threshold ITH 3.25 3.75 4.75 V Switch Input Switch Input Voltage Range VIN -14 — 40 V Notes 8 SPI inputs and outputs are operational. Fault reporting may not be fully operational within this voltage range. See page five. 33884 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 105°C, unless otherwise noted. Typical values, where applicable, reflect the approximate parameter mean with VPWR = 13 V, TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit tPULSE 3.0 34 43 ms tINT(DELAY) 2.5 — 13 ms fSCLK 3.2 3.5 4.0 — — — — — — MHz VIN(LOGIC) 0.2 x VDD — 0.7 x VDD V SO High State Output Voltage (IOH = 1 mA) VOH(SO) 3.5 — — V SO Low State Output Voltage (IOL = 1 mA) VOL(SO) — — 0.4 V IT(SO) -40 — 40 µA SI Pull Down Current (SI = VDD) ISI 5.0 — 35 µA SCLK Input Current (0 V = VDD) ISCLK -10 — 10 µA CS Pull-Up Current (CS = 0 V) ICS -25 — -5.0 µA RST Pull Down Current (RST = 0 V) IRST 5.0 — 35 µA VOL(INT) — — 0.4 V CIN — — 20 pF tLEAD — 100 140 ns Falling Edge of SCLK to Rising Edge of CS (Required set-up time) tLAG — — 50 ns SI to Rising Edge of SCLK (Required set-up time) tSU2 — 25 45 ns Rising Edge of SCLK to SI (Required hold time) tH2 — 25 45 ns SO to Rising Edge of SCLK tSU1 90 125 — ns Rising Edge of SCLK to Falling Edge of SO (Hold time) tH1 90 125 — ns tR(SO) — 30 50 ns POWER INPUT TIMING Pulse Wetting Current Duration Interrupt Delay Time SCLK Frequency vs. SO Load Capacitance 200 pF 160 pF 120 pF DIGITAL INTERFACE TIMING Input Logic Voltage Thresholds (13) SO Tri-State Leakage Current (CS = 0.7 VDD, VSO = 0 to VDD) INT Low State Output Voltage (IOL = 0.5 mA) Input Capacitance on SCLK, SI, Tri-State, SO, CS Falling Edge of CS to Rising Edge of SCLK (13) (13) (Required set-up time) SO Rise Time, SO Fall Time (CL = 200 pF) tF(SO) SI, CS, SCLK Incoming Signal Rise Time (13) tR(SI) — — 50 ns SI, CS, SCLK Incoming Signal Fall Time (13) tF(SI) — — 50 ns tSO(EN) — 80 110 ns Time from Falling Edge of CS to SO Low Impedance (13) Notes 9 10 11 12 Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, SYNC, MASL. See page five. This parameter is guaranteed by design, however, it has not been production tested. Rise and fall time for incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output states data to be available at SO pin. 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 105°C, unless otherwise noted. Typical values, where applicable, reflect the approximate parameter mean with VPWR = 13 V, TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Time from Rising Edge of CS to SO High Impedance (13) Time from Falling Edge of SCLK to SO Data Valid (14) Recovery Time for Sequential Transfers Symbol Min Typ Max Unit tSO(DIS) — 80 110 ns tVALID — 65 105 ns tREC — 100 120 ns Notes 13 Time required for output states data to be terminated at SO pin. 14 Time required to obtain valid data out from SO following the falling edge of SCLK. 33884 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33884 is a monolithic integrated circuit designed to interface between external electrical system switches and low voltage microprocessors via a Serial Peripheral Interface (SPI). The 33884 monitors the OPEN/CLOSED status of multiple external switches used in a system. The 33884 features four programmable Switch-to-Ground or Battery sense inputs, 6 Switch-to-Ground sense inputs, 2 Switch-toBattery sense inputs, programmable Wake up Timer, programmable Interrupt Timer, and programmable wetting current settings. All inputs are protected for ESD transients when implemented with the appropriate ESD capacitor. There are numerous applications for this device in aircraft, aerospace, robotic, process & control, automotive, and security systems. Potential applications exist where switch status verification for safety, fault tolerant operation, or process control function purposes are critical. The 33884 has four modes of operation: Sleep, Normal, Polling, and Polling + INT Timer. The 33884 is designed to provide a robust interface between system switch contacts and a microprocessor. Each 33884 input provides the switch contact with high levels of wetting current during switch closure. After the input switch has been closed for 20 ms, the wetting current is reduced, hence reducing power dissipation in the IC. The response to a SPI command will always return Switch Status, Master/ Slave, INT Flag, and Mode settings. The following section describes the programming modes and features of the 33884. MICROPROCESSOR INTERFACE The M33884 directly interfaces to 3.3 or 5.0 V MCU. SPI serial clock frequencies in excess of 5.0 MHz may be used for programming and reading switch input status. Figure 4 shows the configuration between an MCU and one 33884. 33884 MC68HCXX Microcontroller MOSI SI MISO SO 16 Bit Shift Register 16 Bit Shift Register SCLK Receive Buffer Parallel Ports To Logic RST CS INT INT Figure 4. SPI Interface with Microprocessor The 33884, though originally designed for automotive use, is very useful in a variety of other applications, i.e., computer, telecommunications, and industrial fields. It is parametrically specified over an input battery/supply voltage of 9.0 to 16.0 V but is designed to operate over a considerably wider range of 5.5 to 26.5 V. Two or more 33884 devices may be used in a module system when implemented in a parallel or serial configuration. Figure 5 and Figure 6 show the parallel and serial configurations respectively. When using the Serial configuration, 32 clock cycles are required for a complete transfer of data to the 33884. 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION MC68HCXX Microcontroller MC68HCXX Microcontroller MOSI 33884 MISO SCLK Parallel Ports MOSI SI 16 Bit Shift Register INT MISO SO SCLK CS SCLK Parallel Ports RST INT SI 16 Bit Shift Register INT SI SO SCLK CS RST INT SI 33884 33884 33884 SO SO SCLK SCLK CS CS RST INT RST INT Figure 5. SPI Parallel Interface with Microprocessor Figure 6. SPI Serial Interface with Microprocessor FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS) SERIAL INPUT (SI) The MCU system selects the 33884 to receive its communication through the Chip Select (CS) pin. With the CS in a logic low state, command words may be sent to the 33884 via the Serial Input (SI) pin. Switch status is received by the MCU via Serial Output (SO) pin. The falling edge of CS enables the SO output, latches the state of the Interrupt (INT) pin, Operating mode and the state of the external switch inputs. The rising edge of CS disables the SO driver, resets the INT pin to logic [1], activates the received command word, and allows the 33884 to act upon new data obtained from switch inputs. To avoid any spurious data, it is essential the high-to-low and low-to-high transition of the CS signal occur only when System Clock (SCLK) is in a logic low state. Internal to the 33884 is an active pull-up on CS pin. This Serial Input (SI) pin is used for serial instruction data input. SI information is latched into the Input register on the rising edge of SCLK. A logic high state present at SI when SCLK rises, programs a logic [1] into the command word on rising edge of the CS signal. To program a complete word, 16 bits of information must be entered into the 33884. Internal to the IC is an active pull down on the SI pin. SYSTEM CLOCK (SCLK) The System Clock (SCLK) pin clocks the internal 16-bit Shift register. The Serial Input (SI) data is latched into the Input Shift register on the rising edge of SCLK signal. The Serial Output (SO) pin shifts the switch status bits out on the falling edge of SCLK. False clocking of the Shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever CS makes any transition. For this reason it is recommended, though not necessary, the SCLK pin be commanded to a low logic state as long as the device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal on the SCLK and SI pin will be ignored and the SO pin is Tri-Stated (high impedance). SERIAL OUTPUT (SO) The Serial Output (SO) pin is the output from the Shift register. The SO pin remains Tri-Stated until the CS pin transitions to a logic low state. All open switches are reported as logic [0], all closed switches are reported as logic [1]. The negative transition of CS will make status bit 15 available on SO. Each successive negative clock makes the next status bit available. The SI/SO shifting of the data follows a first-infirst-out protocol with both input and output words transferring the most significant bit (MSB) first. MASTER/SLAVE (MASL) The Master/Slave (MASL) pin is required when multiple 33884 devices are used in one module. The MASL identifies which device will be the master or slave. MASL identification is used during the Polling mode. In the Polling mode, the master device has it’s internal oscillator running while the Slave device oscillator is shutdown. While polling, the master device wakes the slave via the Synchronization (SYNC) pin. This feature provides minimal quiescent from the voltage power (VPWR) and voltage digital drain (VDD) pins. 33884 10 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION SYNCHRONIZATION (SYNC) The Synchronization (SYNC) input is used by the slave IC during the Polling mode. The SYNC allows multiple 33884 ICs to poll the multiple inputs concurrently. The master controls the polling period. The slave is allowed to shut down it’s oscillator, thereby conserving current. When the slave receives the SYNC signal from the master, the slave starts the internal oscillator and reads the switch inputs. INTERRUPT (INT) The Interrupt (INT) pin is an interrupt output from the 33884. The INT pin is an open drain output with an internal pull-up. In the Normal mode, a switch state change triggers the INT pin. The INT pin and INT bit (flag) are latched on the falling edge of CS. This procedure determines the interrupt origin. The flag INT bit in the SPI word is the inverse of the INT pin. The INT pin is cleared on the rising edge of CS. The INT pin is active only during the ON time (when sink and source currents are active) in the Polling mode. voltage on VPWR is 40 V. All wetting currents and sustain currents are derived from VPWR. SWITCH PINS (SP1 : SP4) The 33884 has four programmable switch sense inputs (SP1- P4) to read switch-to-ground or switch-to-battery/ supply contacts. Transient battery/supply voltages greater than 40 V must be clamped by an external device. Surface mount 0805 MOVs and transient voltage suppressors (TVS) are available in SOT-23 packages. The sensed input is compared with an internal 4.0 V reference. When programmed to sense switch-to-battery, sensed voltages greater than 4.0 V are interpreted as a CLOSED switch, while sensed voltages less than 4.0 V are interpreted as an OPEN switch. The opposite holds true when inputs are programmed to sense switch-to-ground. Further programming can set the wetting currents or make the inputs Tri-State. Programming methods are provided in the following section. SWITCH-TO-BATTERY (SB1 AND SB2) RESET (RST) The Reset (RST) pin is active low reset input to the 33884. When asserted, the 33884 will reset all internal registers, timers, and enters a Sleep mode (with all switch inputs in a Tri-State condition). Only an MCU SPI command word will wake the 33884 from a Sleep state. The RST pin may be controlled directly from a general purpose input/output (GPIO) pin or from a system/MCU reset. BANDGAP VOLTAGE (VBG) The Bandgap Voltage (VBG) pin requires a 130 kΩ to ground for standard wetting and sustain currents. The device is tested with a 0.1 percent value, but a standard 1.0 percent could be used to function properly. VOLTAGE POWER (VPWR) The Voltage Power (VPWR) pin is battery/supply source pin for the 33884. The VPWR pin requires external reverse battery/supply and transient protection. Maximum input The two Switch-to-Battery (SB) pins sense inputs only. Transient battery/supply voltages greater than 40 V must be clamped by an external device. Surface mount 0805 MOVs and transient voltage suppressors (TVS) are available in SOT-23 packages. The sensed input is compared with an internal 4.0 V reference. Voltages greater than 4.0 V are interpreted as a CLOSED switch, while sensed voltages less than 4.0 V are interpreted as an OPEN switch. Programming can set wetting currents or Tri-State the input. Programming methods are provided in the following section. SWITCH-TO-GROUND (SG1 : SG6) The six Switch-to-Ground (SG) pins are inputs only. The input is compared with the internal 4.0 V reference. Voltages greater than 4.0 volts are interpreted as an OPEN switch. Voltages less than 4.0 V are interpreted as a CLOSED switch. Programming can set the wetting currents or Tri-State the input. Programming methods are provided in the following section. 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER-UP On initial power-up all 33884 registers are cleared and the device enters the Sleep mode. To exit the Sleep mode, a valid command word is required to be received from the microprocessor. SLEEP COMMAND Sleep mode can be entered by a SPI Sleep command or asserting the RST pin. In Sleep mode all inputs are Tri–State and all internal active pull up and pull down currents are disabled. Sleep mode reduces the current drain to a quiescent current level of 10 µA and disables the IC. Sleep mode provides lowest quiescent current for the IC. Exit from sleep mode requires a valid SPI RUN, TRI–STATE, or METALLIC command. RUN COMMAND The Run command places the IC in one of three operating modes: 1. This is the normal operating mode of the 33884. In Normal mode the status of the input switches are latched on falling edge of CS and data is returned to the MCU via SPI. All programmed combinations of source and sink currents, used for sensing purposes, are always active in this mode. While in the Normal mode, an interrupt is generated and sent to the microprocessor whenever an external switch changes its OPEN or CLOSED state. Prior to a switch closing, the 33884 sources 0.75 mA of sustain current. When the voltage at the input crosses the comparator threshold, 14 mA of current is allowed to flow. The 14 mA wetting current shuts off after a 20 ms timer expires. 2. The Polling mode reads a switch status periodically, interrupting the microprocessor only when an external switch is sensed as being CLOSED. When the 33884 senses all external switches to be OPEN, the Polling mode of operation continues. When a switch is sensed CLOSED, an interrupt is sent to the microprocessor, transferring it’s operational mode to the Normal mode. The Polling mode provides a reduction in quiescent current by turning OFF all source and sink currents during sensed switch OFF periods. The Polling mode allows reduction of quiescent current by disabling sink and source currents during switch OFF periods. 3. The Polling + INT Timer mode of operation is similar to the Polling mode above, except with the addition of an interrupt being sent to the microprocessor if a switch is sensed CLOSED, or upon the internal interrupt timer timing out. An interrupt is always ultimately sent to the microprocessor in this mode. The microprocessor can be programmed to read, or ignore the reported switch status while receiving the interrupt. If a switch is sensed CLOSED, operation automatically reverts to the Normal mode. If all switches are sensed OPEN, and the wake up timer (INT Timer) times out, the 33884 continues to operate in the Polling + INT Timer mode. The wake up timer duration may be set much longer than the polling time. The command also programs the SP1 to SP4 sense inputs (switch-to-battery logic [1] or switch-to-ground logic[0]). Please refer to Table 17. TRI-STATE COMMAND A Tri-State command places all switch inputs into Tri-State position. All comparators on input are disabled in this mode. The device will return logic [0] for the switch status. SPI PROGRAMMING The 33884 uses the SPI in full duplex synchronous slave mode for communication with the microprocessor. The 33884 is programmed via a 16-bit word command from the MCU. The word is sent to the device with the MSB first. The command word sent to the 33884 sets the mode of operation in the device. Returning data received from the 33884 is the status of the sensed input switch on the falling edge of CS. Sixteen clock periods are required for each transmission to be valid. After the 16 clocks, CS is returned to the inactive state (logic [1]), command words are no longer accepted into SI, and the SO pin is Tri-Stated. The response to a SPI command returns status based on previous command word. This previous command could be a hardware reset as well as any of the other commands discussed in this section. 33884 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS PROGRAMMING AND CONFIGURATION DESCRIPTION SPI Commands from Microcontroller / Command Protocol (Data into SI) Table 5. SPI Command Protocol MSB LSB Command 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Sleep (Default) 0 0 0 0 x x x x x x x x x x x x Run 0 0 0 1 ST3 ST2 ST1 — WT2 WT1 CP4 CP3 CP2 CP1 Tri-State 0 0 1 1 TG6 TG5 TG4 TG3 TG2 TG1 TP4 TP3 TP2 TP1 TB2 TB1 Metallic 0 1 0 1 MG6 MG5 MG4 MG3 MG2 MG1 MP4 MP3 MP2 MP1 MB2 MB1 IC Test Mode 1 x x x x x x x x x x x x x x x Run Register — — — — U U U U U U U U U U U U Tri-State Register — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Metallic Register — — — — U U U U U U U U U U U U MOD2 MOD1 Reset Values: U =Unknown value coming out of Sleep mode. It be must configured with Run and Metallic commands. Note: the remaining combinations of bits [16;13] are non-functional (0010. 0100. 0110. 0111). MOD[2:1] = Operating mode TP[4:1] = Tri-State programmable switch ST[3:1] = Sample OFF time WT[3:1] = Wake up time MG[6:1] = Metallic switch-to-ground CP[4:1] = Configure programmable switch MB[2:1] = Metallic switch-to-battery TG[6:1] = Tri-State switch-to-ground MP[4:1] = Metallic programmable switch TB[2:1] = Tri-State switch-to-battery SLEEP COMMAND disabling all input blocks and all internal pull-ups/pull downs. Only a SPI command can take the IC out of Sleep mode. Exiting this mode requires a valid Run, Tri-State, or Metallic command. The Sleep command places the IC in Sleep mode and essentially turns the part OFF. By definition, a hardware reset sends/keeps the IC in Sleep mode. All inputs are Tri-Stated, Table 6. Sleep Command MSB LSB Command 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Sleep (Default) 0 0 0 0 x x x x x x x x x x x x 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RUN COMMAND of tWAIT and tWAKE, and configures the programmable input blocks. Bit 7 is currently unused. Note that the Run register values are unknown after exiting the Sleep mode. The Run command gives access to all operating modes: Normal, Polling, and Polling + INT Timer. It allows selection Table 7. Run Command MSB LSB Command 16 15 14 13 Run 0 0 0 1 — — — — 12 11 MOD2 MOD1 10 9 8 7 6 5 4 3 2 1 ST3 ST2 ST1 — WT2 WT1 CP4 CP3 CP2 CP1 U U U U U U U U U U Reset Values: Run Register U U U = Unknown value coming out of Sleep mode. It must be configured with Run command. Table 9. Sample OFF Time Prescales MOD[2:1] OPERATING MODE Multiplier Selected OFF Time, tWAIT (ms) [tDETECT (4.8ms typ) x Multiplier] ON Time (ms) 000 5 15 - 25 5.1 - 6.3 001 9 30 - 55 5.1 - 6.3 010 17 60 - 90 5.1 - 6.3 011 25 100 - 140 5.1 - 6.3 100 33 145 - 185 5.1 - 6.3 101 41 195 - 215 5.1 - 6.3 110 49 220 - 245 5.1 - 6.3 111 57 250 - 320 5.1 - 6.3 In the Run command, the two MOD bits place the device in one of three operating modes: Normal, Polling, and Polling + INT Timer. ST[3:1] Table 8. Bit Definition for Run Command Command: Run (0001) with bits [12:1] Mode MOD2 MOD1 ST[3:1] WT[2:1] CP[4:1] Undefined 0 0 xxx xx CP[4:1] Normal 0 1 xxx xx CP[4:1] Polling 1 0 ST[3:1] xx CP[4:1] Polling + INT Timer 1 1 ST[3:1] WT[2:1] CP[4:1] ST[3:1] – OFF TIME BETWEEN SAMPLES (TWAIT) WT[2:1] – WAKE UP TIME During both Polling modes (with and without INT Timer wake up, MOD2=[1]), these bits select the interval of time (tWAIT) the Input Blocks are turned OFF; switch transitions are not detected during the OFF interval. These bits allow the device to assert an external interrupt (INT) at the following intervals during Polling mode (MOD2 = MOD1 = 1). Table 10. Wake Up Delay Prescales Multiplier Selected Wake Up Interrupt, tWAIT (ms) [tDETECT (2.8ms typ) x Multiplier] 00 512 + 1 2400 - 3200 01 256 + 1 1200 - 1600 10 128 + 1 600 - 750 11 64 + 1 290 - 360 WT[2:1] 33884 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS TRI-STATE COMMAND Note: This configuration may be entered in any of the three valid Operating Modes (see MOD[2:1]) within the Run command. This command places an external switch into a Tri-State condition, essentially disconnecting the wetting current (if the switch is metallic) and the sustain current. The internal inputthreshold comparator is still internally connected to its external pin. This command does not change the mode of operation Table 11. Programmable Switch Bit Definition CPx CP[4:1] – CONFIGURE PROGRAMMABLE SWITCH Configure the programmable inputs SP[4:1] to detect either an external switch-to-ground (internal current source) or an external switch-to-battery (internal current sink). External Switch to: 0 Ground 1 Battery (e.g., a Tri-State command received while in the Polling mode leaves the part in that mode). Note: The Tri-State register clears all bits to logic [0] (all inputs in Tri-State) in response to a hardware reset; all inputs also remain in Tri-State after existing the Sleep mode. Table 12. Tri-State Command MSB LSB Command 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Tri-State 0 0 1 1 TG6 TG5 TG4 TG3 TG2 TG1 TP4 TP3 TP2 TP1 TB2 TB1 — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Reset Values: Run Register TG[6:1] = Tri-state switch-to-ground TB[2:1] = Tri-state switch-to-battery TP[4:1] = Tri-state programmable switch METALLIC COMMAND Table 13. Programmable Switch Bit Definition TGx, TBx, TPx This command enables the pulsed wetting current for an external metallic switch and disables it for an external nonmetallic switch. This command does not change the mode of operation (e.g., a Metallic command received while in Polling mode leaves the part in that mode). Note that the Run register values are unknown after exiting the Sleep mode. Input Configured to: 0 Input Disabled (Default) 1 Input Enabled Table 14. Metallic Command MSB LSB Command 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Metallic 0 1 0 1 MG6 MG5 MG4 MG3 MG2 MG1 MP4 MP3 MP2 MP1 MB2 MB1 — — — — U U U U U U U U U U U U Reset Values: Run Register U = Unknown value coming out of Sleep mode. It must be configured with Run command. MG[6:1] = Metallic switch-to-ground MB[2:1] = Metallic switch-to-battery MP[4:1] = Metallic programmable switch Table 15. Metallic Switch Bit Definition MGx, MBx, MPx Accept Switch Type: 0 Non-Metallic 1 Metallic (Enable Wetting Current Pulse) 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS TEST MODE Bit 16 is reserved for placing the device into a special IC Test mode. It is used to confirm various internal functions. Table 16. Test Mode MSB LSB Command 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 IC Test Mode 1 x x x x x x x x x x x x x x x SPI RESPONSES Response Protocol (Data out of SO). Table 17. SPI Responses MSB LSB Mode 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reset/Sleep 0 0 x x x x x x x x x x x x x x Normal 0 1 MASL INT SG6 SG5 SG4 SG3 SG2 SG1 SP4 SP3 SP2 SP1 SB2 SB1 Polling 1 0 MASL x SG6 SG5 SG4 SG3 SG2 SG1 SP4 SP3 SP2 SP1 SB2 SB1 Polling + INT Timer 1 1 MASL INT SG6 SG5 SG4 SG3 SG2 SG1 SP4 SP3 SP2 SP1 SB2 SB1 SG[6:1] = Switch-to-ground flag MASL = Master/Slave identification flag SB[2:1] = Switch-to-battery flag INT = External Interrupt flag SP[4:1] = Programmable switch flag RESET/SLEEP (logic [1]) the MC33884 remains in Sleep mode. A SPI command, received from the microprocessor, is necessary to command the device out of Sleep mode. When the Reset (RST) input is active (logic [0]), all internal registers are cleared, thereby placing the device in Sleep mode and upon the RST input returning to the inactive state Table 18. Reset/Sleep MSB LSB Mode 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reset/Sleep 0 0 x x x x x x x x x x x x x x Note: The SPI response given while sending the command to exit Sleep mode should be ignored due to unknown power-up state. 33884 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS NORMAL AND PERIODIC Bits [16:15] identify one of the three operating modes: Normal, Polling, and Polling + INT Timer. The remaining bits identify the device as the Master or a Slave, whether the device has an interrupt that has not been cleared, and the state of all the inputs. Table 19. Normal and Periodic MSB LSB Mode 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Normal 0 1 MASL INT SG6 SG5 SG4 SG3 SG2 SG2 SG1 SP3 SP2 SP1 SB2 SB1 Polling 1 0 x — — Polling + INT Timer 1 1 INT — — Note: The SPI response given while sending the command to exit Sleep mode should be ignored due to unknown power-up state. MASL– MASTER/SLAVE IDENTIFICATION FLAG This flag is the same as the state of the MASL pin. It provides software identification of the configuration of each IC. Table 20. MASL Bit Definition MASL Device is a: 0 Slave 1 Master These twelve flags indicate the state of all switch inputs: Table 22. Switch State Bit Definition External Switch is: Mode Input States Latched: 0 Open Normal 1 At the moment CS transitions to logic 0 Closed Polling SGx, SBx, SPx TRI-STATE INT – EXTERNAL INTERRUPT FLAG This flag identifies this particular IC as the initiator of an external interrupt. It is the inverse of INT. All Tri-State inputs have their wetting and sustain currents disabled. By definition, all disabled inputs return the following value for the switch state whenever SPI data is exchanged: Table 21. MASL Bit Definition Table 23. Tri-State Bit Definition MASL 16 15 14 13 Type of Interrupt Normal 0 1 x 0 Nothing Happened — — — 1 Switch Interrupt 1 0 x x — 1 1 x 0 Nothing Happened — — — 1 Wake up Interrupt Polling Polling + INT Timer SGx, SBx, SPx 0 External Switch is: Tri-State SG[6:1] = Switch-to-ground flag SB[2:1] = Switch-to-battery flag SP[4:1] = Programmable switch flag 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 17 TYPICAL APPLICATIONS TYPICAL APPLICATIONS External Switches VPWR VBAT T VDD VPWR SB1 VBAT T 10 nF 0805 100 V VBAT T 10 nF 0805 100 V 10 nF 0805 100 V SP1 VBAT T SP2 10 nF 0805 100 V 10k 0805 SI MOSI SO MISO 16 Bit Shift Register M S B L S B SCLK SP3 VBAT T 10 nF 0805 100 V 33884 10 nF 0805 100 V VBAT T MC68HCXX Microcontroller VDD SB2 INT 10 nF 0805 100 V Parallel Ports CS SP4 10 nF 0805 100 V 10 nF 0805 100 V 10 nF 0805 100 V 10 nF 0805 100 V VBG RESET SG1 130k 0805 SG2 SG3 10k 0805 RST SG4 WDOG LVI RESET Control 10 nF 0805 100 V SG5 10 nF 0805 100 V VBAT T SG6 Master Node SYNC 10 nF 0805 100 V SYNC SB1 VBAT T MASL Slave Node 10 nF 0805 100 V VPWR 10 nF 0805 100 V SB2 VBAT T 10 nF 0805 100 V SP1 10 nF 0805 100 V SP2 10 nF 0805 100 V 10 nF 0805 100 V SO SCLK INT CS SP3 VBAT T VDD SI VBAT T VBAT T MC33884 10 nF 0805 100 V RST MASL VBG SP4 10 nF 0805 100 V 130k 0805 Figure 7. Typical Master/Slave Application 33884 18 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX EG (Pb-FREE) SUFFIX PLASTIC PACKAGE 98ASB42344B ISSUE F 33884 Analog Integrated Circuit Device Data Freescale Semiconductor 19 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 3.0 6/2006 • • • • Implemented Revision History page Converted to Freescale format Corrected content to the prevailing form and style Removed MC33884EG/R2, and replaced with MCZ33884EG/R2 in the Ordering Information block 4.0 11/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum ratings on page 5. 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