FREESCALE MPC7410_1

Freescale Semiconductor
MPC7410EC
Rev. 6.1, 11/2007
Technical Data
MPC7410 RISC Microprocessor
Hardware Specifications
The MPC7410 is a PowerPC™ reduced instruction set computing
(RISC) microprocessor. This document describes pertinent
electrical and physical characteristics of the MPC7410. For
functional characteristics of the processor, refer to the MPC7410
RISC Microprocessor User’s Manual.
To locate any published errata or updates for this document, refer
to the web site at http://www.freescale.com.
1
Overview
The MPC7410 is the second implementation of the fourth
generation (G4) microprocessors from Freescale. The MPC7410
implements the full PowerPC 32-bit architecture and is targeted at
both computing and embedded systems applications.
Some comments on the MPC7410 with respect to the MPC750:
•
•
•
The MPC7410 adds an implementation of the new
AltiVec™ technology instruction set.
The MPC7410 includes significant improvements in
memory subsystem (MSS) bandwidth and offers an
optional, high-bandwidth MPX bus interface.
The MPC7410 adds full hardware-based multiprocessing
capability, including a five-state cache coherency protocol
(four MESI states plus a fifth state for shared
intervention).
© Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical and Thermal Characteristics . . . . . . . . . . . . 7
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 29
System Design Information . . . . . . . . . . . . . . . . . . . 34
Document Revision History . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 53
Features
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•
•
•
The MPC7410 is implemented in a next generation process technology for core frequency improvement.
The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision
operations involving multiplication.
The completion queue has been extended to eight slots.
There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the
branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute,
complete/writeback).
Some comments on the MPC7410 with respect to the MPC7400:
•
•
•
The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface.
The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements a 19th L2
address pin (L2ASPARE on the MPC7400) in order to support additional address range.
The MPC7410 removes support for 3.3-V I/O on the L2 cache interface.
Figure 1 shows a block diagram of the MPC7410.
2
Features
This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major features of
the MPC7410 are as follows:
•
•
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving two speculations)
— Up to one speculative stream in execution, one additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay
slots
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1,
fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)
— Serialization control (predispatch, postdispatch, execution serialization)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Completion Queue
(8-Entry)
Completion Unit
VSCR
Vector ALU
Vector
Permute
Unit
19-Bit L2 Address Bus
64- or 32-Bit L2 Data Bus
Ability to Complete Up
to Two Instructions Per Clock
Integer
Unit 2
Reservation
Station
+
CTR
LR
32-Bit Address Bus
64-Bit Data Bus
L2PMCR
L2 Castout
IBAT
Array
DBAT
Array
Reservation
Station (2-Entry)
128-Entry
DTLB
SRs
(Original)
Data MMU
128-Entry
ITLB
SRs
(Shadow)
Instruction MMU
32-Kbyte
I Cache
Instruction
Instruction
Reload Buffer Reload Table
Memory Subsystem
Data Reload Data Reload
Buffer
Table
64-Bit
6 Rename
Buffers
FPSCR
FPSCR
+ x ÷
FloatingPoint Unit
Reservation
Station
32-Kbyte
Tags D Cache
Tags
128-Bit
(4 Instructions)
FPR File
Completed
L1
Stores Operations 64-Bit
Load/Store Unit
+ (EA Calculation)
Load Fold
32-Bit Finished Queue
Stores
Vector
Touch
Queue
6 Rename
Buffers
GPR File
PA
EA
Bus Interface Unit
Data
L2 Miss
Transaction
Queue
32-Bit
System
Register Unit
Reservation
Station
64-Bit (2 Instructions)
Dispatch Unit
BHT
(512-Entry)
Branch Processing
Unit
BTIC
(64-Entry)
L2 Controller
L2 Data
L2 Tags
Transaction
Queue
L2CR
32-Bit
+ x ÷
Integer
Unit 1
Reservation
Station
Instruction Queue
(6-Word)
128-Bit
6 Rename
Buffers
VR File
128-Bit
VSIU VCIU VFPU
Reservation
Station
2 Instructions
Reservation
Station
•
•
•
•
•
•
Additional Features
Time Base
Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
Fetcher
Instruction Unit
Features
Figure 1. MPC7410 Block Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Features
•
•
•
•
•
•
•
Decode
— Register file access
— Forwarding control
— Partial instruction decode
Completion
— Eight-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction execution,
completion serialization, and all instruction flow changes
Fixed point units (FXUs) that share 32 GPRs for integer operands
— Fixed point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Three-stage floating-point unit and a 32-entry FPR file
— Support for IEEE Std 754™ single- and double-precision floating-point arithmetic
— Three-cycle latency, one-cycle throughput (single- or double-precision)
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
AltiVec unit
— Full 128-bit data paths
— Two dispatchable units: vector permute unit and vector ALU unit.
— Contains its own 32-entry, 128-bit vector register file (VRF) with 6 renames
— The vector ALU unit is further subdivided into the vector simple integer unit (VSIU), the vector
complex integer unit (VCIU), and the vector floating-point unit (VFPU).
— Fully pipelined
Load/store unit
— One-cycle load or store cache access (byte, half word, word, double word)
— Two-cycle load latency with 1-cycle throughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double-word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
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Features
•
•
•
•
— Store gathering
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all four architecture AltiVec DST streams
Level 1 (L1) cache structure
— 32 Kbyte, 32-byte line, eight-way set-associative instruction cache (iL1)
— 32 Kbyte, 32-byte line, eight-way set-associative data cache (dL1)
— Single-cycle cache access
— Pseudo least-recently-used (LRU) replacement
— Data cache supports AltiVec LRU and transient instructions algorithm
— Copy-back or write-through data cache (on a page-per-page basis)
— Supports all PowerPC memory coherency modes
— Nonblocking instruction and data cache
— Separate copy of data cache tags for efficient snooping
— No snooping of instruction cache except for ICBI instruction
Level 2 (L2) cache interface
— Internal L2 cache controller and tags; external data SRAMs
— 512-Kbyte, 1-Mbyte, and 2-Mbyte two-way set-associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— 32-byte (512-Kbyte), 64-byte (1-Mbyte), or 128-byte (2-Mbyte) sectored line size
— Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register) late
write synchronous BurstRAMs
— Supports direct-mapped mode for 256 Kbytes, 512 Kbytes, 1 Mbyte, or 2 Mbytes of SRAM (either all,
half, or none of L2 SRAM must be configured as direct-mapped)
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64-bit data bus which also supports 32-bit bus mode
— Selectable interface voltages of 1.8 and 2.5 V
Memory management unit
— 128-entry, two-way set-associative instruction TLB
— 128-entry, two-way set-associative data TLB
— Hardware reload for TLBs
— Four instruction BATs and four data BATs
— Virtual memory support for up to 4 hexabytes (252) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
— Snooped and invalidated for TLBI instructions
Efficient data flow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide
— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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5
Features
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—
—
—
—
•
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•
•
L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s.
Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus
Up to seven outstanding, out-of-order transactions on the bus
Load folding to fold new dL1 misses into older, outstanding load and store misses to the same line
Store miss merging for multiple store misses to the same line. Only coherency action taken (that is,
address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).
— Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1
— Separate additional queues for efficient buffering of outbound data (castouts, write throughs, and so on)
from dL1 and L2
Bus interface
— MPX bus extension to 60x processor interface
— Mode-compatible with 60x processor interface
— 32-bit address bus
— 64-bit data bus
— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x
supported
— Selectable interface voltages of 1.8, 2.5, and 3.3 V
Power management
— Low-power design with thermal requirements very similar to MPC740 and MPC750
— Low-voltage processor core
— Selectable interface voltages can reduce power in output buffers
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management
Testability
— LSSD scan design
— IEEE Std 1149.1™ JTAG interface
— Array built-in self test (ABIST)—factory test only
— Redundancy on L1 data arrays and L2 tag arrays
Reliability and serviceability
— Parity checking on 60x and L2 cache buses
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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General Parameters
3
General Parameters
The following list provides a summary of the general parameters of the MPC7410:
Technology
Die size
Transistor count
Logic design
Packages
0.18 µm CMOS, six-layer metal
6.32 mm × 8.26 mm (52 mm2)
10.5 million
Fully static
Surface mount 360 ceramic ball grid array (CBGA)
Surface mount 360 high coefficient of thermal expansion ceramic ball grid array
(HCTE_CBGA)
Surface mount 360 high coefficient of thermal expansion ceramic ball grid array with
lead free C5 spheres (HCTE_CBGA Lead Free C5 Spheres)
Surface mount 360 high coefficient of thermal expansion ceramic land grid array
(HCTE_LGA)
Core power supply 1.8 V ± 100 mV DC (nominal; see Table 3 for recommended operating conditions)
I/O power supply 1.8 V ± 100 mV DC or
2.5 V ± 100 mV
3.3 V ± 165 mV (system bus only)
(input thresholds are configuration pin selectable)
4
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7410.
4.1 DC Electrical Characteristics
The tables in this section describe the MPC7410 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 2.1
V
4
PLL supply voltage
AVDD
–0.3 to 2.1
V
4
L2AVDD
–0.3 to 2.1
V
4
OVDD
–0.3 to 3.6
V
3, 6
L2OVDD
–0.3 to 2.8
V
3
Processor bus
Vin
–0.3 to OVDD + 0.2 V
V
2, 5
L2 bus
Vin
–0.3 to L2OVDD + 0.2 V
V
2, 5
JTAG signals
Vin
–0.3 to OVDD + 0.2 V
V
—
Tstg
–55 to 150
°C
—
L2 DLL supply voltage
Processor bus supply voltage
L2 bus supply voltage
Input voltage
Storage temperature range
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
7
Electrical and Thermal Characteristics
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic
Rework temperature
Symbol
Maximum Value
Unit
Notes
Trwk
260
°C
—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: V in must not exceed OVDD or L2OVDD by more than 0.2 V at any time including during power-on reset.
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0 V at any time including during
power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V at any time including during
power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a maximum
value OVDD of –0.3 to 2.8 V.
Figure 2 shows the allowable undershoot and overshoot voltage for the MPC7410.
(L2)OV DD + 20%
(L2)OVDD + 5%
(L2)OVDD
VIH
VIL
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
of tSYSCLK (OVDD)
or tL2CLK (L2OV DD)
Figure 2. Overshoot/Undershoot Voltage
The MPC7410 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7410 core voltage must always be provided at nominal voltage (see Table 3 for actual
recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in Table 2. Voltage must be provided to the L2OVDD
power pins even if the interface is not used. The input voltage threshold for each bus is selected by sampling the
state of the voltage select pins BVSEL and L2VSEL at the negation of the signal HRESET. These signals must
remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum
voltage applied to the OVDD or L2OVDD power pins.
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Electrical and Thermal Characteristics
Table 2. Input Threshold Voltage Setting
BVSEL Signal 3
Processor Bus Input
Threshold is Relative to:
L2VSEL Signal 3
L2 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
1
HRESET
2.5 V
HRESET
2.5 V
1, 2
1
3.3 V
1
2.5 V
1, 4, 5
¬HRESET
3.3 V
¬HRESET
Not Supported
6
Notes:
1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.
2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals
change state together. This is the preferred method for selecting this mode of operation.
3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used.
4. Default voltage setting if left unconnected (internal pulled-up). MPC7410RXnnnLE (Rev 1.4) and later only.
Previous revisions do not support 3.3 V OVDD; the default voltage setting if left unconnected is 2.5 V.
5. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD; having BVSEL = 1 selects
the 2.5-V threshold.
6. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET. (¬HRESET is
the inverse of HRESET.)
Table 3 provides the recommended operating conditions for the MPC7410.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Electrical and Thermal Characteristics
Table 3. Recommended Operating Conditions 1
Symbol
Recommended
Value
Unit
Notes
Core supply voltage
VDD
1.8 V ± 100 mV
V
—
PLL supply voltage
AVDD
1.8 V ± 100 mV
V
—
L2AVDD
1.8 V ± 100 mV
V
—
BVSEL = 0
OVDD
1.8 V ± 100 mV
V
—
BVSEL = HRESET
OVDD
2.5 V ± 100 mV
V
—
BVSEL = ¬HRESET or
BVSEL = 1
OVDD
3.3 V ± 165 mV
V
2, 3
L2VSEL = 0
L2OVDD
1.8 V ± 100 mV
V
—
L2VSEL = HRESET or
L2VSEL = 1
L2OVDD
2.5 V ± 100 mV
V
—
Processor bus and
JTAG signals
Vin
GND to OVDD
V
—
L2 bus
Vin
GND to L2OVDD
V
—
Tj
0 to 105
°C
—
Characteristic
L2 DLL supply voltage
Processor bus supply
voltage
L2 bus supply voltage
Input voltage
Die-junction temperature
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a
recommended OVDD value of 2.5 V ± 100 mV for BVSEL = 1.
3. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET.
Table 4 provides the package thermal characteristics for the MPC7410.
Table 4. Package Thermal Characteristics
Value
Characteristic
Symbol
Unit
Notes
Junction-to-ambient thermal resistance, natural convection,
four-layer (2s2p) board
20
°C/W
1, 2
14
16
°C/W
1, 2
RθJMA
13
15
°C/W
1, 2
RθJB
9
11
°C/W
3
MPC7410
CBGA
MPC7410
HCTE
RθJMA
18
Junction-to-ambient thermal resistance, 1m/sec airflow,
four-layer (2s2p) board
RθJMA
Junction-to-ambient thermal resistance, 2m/sec airflow,
four-layer (2s2p) board
Junction-to-board thermal resistance
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Electrical and Thermal Characteristics
Table 4. Package Thermal Characteristics (continued)
Value
Characteristic
Symbol
Junction-to-case thermal resistance
RθJC
MPC7410
CBGA
MPC7410
HCTE
< 0.1
< 0.1
Unit
Notes
°C/W
4
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
4. Thermal resistance between the active portion of the die and the calculated case temperature at the top of the die.
The actual value of R JC is less than 0.1 °C/W.
Note: Refer to Section 8.8, “Thermal Management Information,” for details on thermal management.
Table 5 provides the DC electrical characteristics for the MPC7410.
Table 5. DC Electrical Specifications
At recommended operating conditions (see Table 3)
Characteristic
Input high voltage (all inputs except
SYSCLK)
Input low voltage (all inputs except
SYSCLK)
SYSCLK input high voltage
SYSCLK input low voltage
Input leakage current,
Vin = L2OVDD/OVDD
Nominal
Bus
Voltage1
Symbol
Min
Max
Unit
Notes
1.8
VIH
0.65 × (L2)OVDD
(L2)OVDD + 0.2
V
2, 3, 8
2.5
VIH
1.7
(L2)OVDD + 0.2
3.3
VIH
2.0
OVDD + 0.3
1.8
VIL
–0.3
0.35 × (L2)OVDD
V
8
2.5
VIL
–0.3
0.2 × (L2)OVDD
3.3
VIL
–0.3
0.8
1.8
CVIH
1.5
OVDD + 0.2
V
2, 8
2.5
CVIH
2.0
OVDD + 0.2
3.3
CVIH
2.4
OVDD + 0.3
1.8
CV IL
–0.3
0.2
V
8
2.5
CV IL
–0.3
0.4
3.3
CV IL
–0.3
0.4
1.8
Iin
—
20
µA
2.5
Iin
—
35
2, 3,
6, 7
3.3
Iin
—
70
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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11
Electrical and Thermal Characteristics
Table 5. DC Electrical Specifications (continued)
At recommended operating conditions (see Table 3)
Characteristic
High-Z (off-state) leakage current,
Vin = L2OVDD/OVDD
Output high voltage, IOH = –5 mA
Output low voltage, IOL = 5 mA
Capacitance, Vin = 0 V, f = 1 MHz
Nominal
Bus
Voltage1
Symbol
Min
Max
Unit
Notes
1.8
ITSI
—
20
µA
2.5
ITSI
—
35
2, 3,
5, 7
3.3
ITSI
—
70
1.8
VOH
(L2)OVDD – 0.45
—
V
8
2.5
VOH
1.7
—
3.3
VOH
2.4
—
1.8
VOL
—
0.45
V
8
2.5
VOL
—
0.4
3.3
VOL
—
0.4
Cin
—
6.0
pF
3, 4, 7
Notes:
1. Nominal voltages; see Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.
3. Excludes factory test signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same
direction (for example, both OVDD and L2OVDD vary by either +5% or –5%).
6. Measured at max OVDD/L2OVDD.
7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.
8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of
1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by
the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR
or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed,
there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a
SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET.
Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST
or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Electrical and Thermal Characteristics
Table 6 provides the power consumption for the MPC7410.
Table 6. Power Consumption for MPC7410
Processor (CPU) Frequency
400 MHz
450 MHz
Unit
Notes
500 MHz
Full-On Mode
Typical
4.2
4.7
5.3
W
1, 3
Maximum
9.5
10.7
11.9
W
1, 2
4.8
5.3
W
1
1.5
1.65
W
1
1.45
1.6
W
1
Doze Mode
Maximum
4.3
Nap Mode
Maximum
1.35
Sleep Mode
Maximum
1.3
Sleep Mode—PLL and DLL Disabled
Typical
600
600
600
mW
1
Maximum
1.1
1.1
1.1
W
1
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD
and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but
is typically <5% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW.
2. Maximum power is measured at 105°C and VDD = 1.8 V while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, including AltiVec, maximally busy.
3. Typical power is an average value measured at 65°C and VDD = 1.8 V in a system while running typical benchmarks.
4.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7410. After fabrication, functional parts are
sorted by maximum processor core frequency, see Section 4.2.1, “Clock AC Specifications,” and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core
frequency; see Section 10, “Ordering Information.”
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
13
Electrical and Thermal Characteristics
4.2.1
Clock AC Specifications
Table 7 provides the clock AC timing specifications as defined in Figure 3.
Table 7. Clock AC Timing Specifications
At recommended operating conditions (see Table 3)
Maximum Processor Core Frequency
Characteristic
Symbol
400 MHz
450 MHz
500 MHz
Min
Max
Min
Max
Min
Max
Unit
Notes
Processor frequency
fcore
350
400
350
450
350
500
MHz
1
VCO frequency
fVCO
700
800
700
900
700
1000
MHz
1
SYSCLK frequency
fSYSCLK
33
133
33
133
33
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
30
7.5
30
7.5
30
ns
—
tKR and tKF
—
0.5
—
0.5
—
0.5
ns/V
2
tKHKL/tSYSCLK
40
60
40
60
40
60
%
3
SYSCLK jitter
—
—
±150
—
±150
—
±150
ps
4
Internal PLL-relock time
—
—
100
—
100
—
100
μs
5
SYSCLK rise and fall time
SYSCLK duty cycle
measured at OVDD/2
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in Section 8.1, “PLL Configuration,” for valid PLL_CFG[0:3]
settings.
2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a result, the
0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the 3.3-V bus interface.
Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from 0.2 to 1.2 V) in 0.5 ns for the
1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change (from 0.4 to 2.4 V) in 1 ns.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Figure 3 provides the SYSCLK input timing diagram.
SYSCLK
VM
VM
tKHKL
VM
CVIH
CVIL
tKR
tKF
tSYSCLK
VM = Midpoint Voltage (OVDD/2)
Figure 3. SYSCLK Input Timing Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
14
Freescale Semiconductor
Electrical and Thermal Characteristics
4.2.2
Processor Bus AC Specifications
Table 8 provides the processor bus AC timing specifications for the MPC7410 as defined in Figure 4 and Figure 5.
Timing specifications for the L2 bus are provided in Section 4.2.3, “L2 Clock AC Specifications.”
Table 8. Processor Bus AC Timing Specifications 1
At recommended operating conditions (see Table 3)
400, 450, 500 MHz
Symbol 2
Parameter
Min
Max
Unit
Notes
Input setup
tIVKH
1.0
—
ns
4
Input hold
tIXKH
0
—
ns
4
ns
5, 6
TS
ARTRY, SHD0, SHD1
All other outputs
tKHTSV
tKHARV
tKHOV
—
—
—
3.0
2.3
3.0
ns
5
TS
ARTRY, SHD0, SHD1
All other outputs
tKHTSX
tKHARX
tKHOX
0.5
0.5
0.5
—
—
—
SYSCLK to output enable
tKHOE
0.5
—
ns
9
SYSCLK to output high impedance (all except ABB/AMON(0),
ARTRY/SHD, DBB/DMON(0), SHD0, SHD1)
tKHOZ
—
3.5
ns
SYSCLK to ABB/AMON(0), DBB/DMON(0) high impedance after
precharge
tKHABPZ
—
1
tSYSCLK
3, 7, 9
Maximum delay to ARTRY, SHD0, SHD1 precharge
tKHARP
—
1
tSYSCLK
3, 8, 9
Output valid times:
Output hold times:
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
15
Electrical and Thermal Characteristics
Table 8. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions (see Table 3)
400, 450, 500 MHz
Symbol 2
Parameter
SYSCLK to ARTRY, SHD0, SHD1 high impedance after precharge
tKHARPZ
Min
Max
—
2
Unit
Notes
tSYSCLK
3, 8, 9
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V)
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that
the input signal (I) went invalid (X) with respect to the rising clock edge (KH)— note the position of the reference and its state
for inputs—and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
3. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period
of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. Includes mode select signals: BVSEL, EMODE, L2VSEL. See Figure 5 for mode select timing with respect to HRESET.
5. All other output signals are composed of the following— A[0:31], AP[0:3], TT[0:4], TS, TBST, TSIZ[0:2], GBL, WT, CI,
DH[0:31], DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.
6. Output valid time is measured from 2.4 to 0.8 V which may be longer than the time required to discharge from VDD to 0.8 V.
7. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low
then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for ABB or DBB is 0.5
× tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting ABB, or DBB on the
following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted.
Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.
8. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting
it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle
after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high-Z as shown in
Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for
the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.
9. Guaranteed by design and not tested.
Figure 4 provides the AC test load for the MPC7410.
Output
Z0 = 50 Ω
OVDD /2
RL = 50 Ω
Figure 4. AC Test Load
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7410. The mode select inputs are sampled
twice, once before and once after HRESET negation.
SYSCLK
VM
VM
HRESET
Mode Signals
First sample
VM = Midpoint Voltage (OVDD/2)
Second sample
Figure 5. Mode Input Timing Diagram
Figure 6 provides the input/output timing diagram for the MPC7410.
SYSCLK
VM
VM
VM
tIVKH
tIXKH
All Inputs
tKHOV
All Outputs
(Except TS, ABB,
ARTRY, DBB)
tKHOX
tkhoe
tKHOZ
All Outputs
(Except TS, ABB,
ARTRY, DBB)
tKHABPZ
tKHTSV
tKHTSX
TS,
ABB/AMON(0),
DBB/DMON(0)
tKHTSV
tKHARPZ
tKHARV
ARTRY,
SHD0,
SHD1
tKHARP
tKHARV
tKHARX
VM = Midpoint Voltage (OVDD/2)
Figure 6. Input/Output Timing Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
17
Electrical and Thermal Characteristics
4.2.3
L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2 divisor ratio. See
Table 14 for example core and L2 frequencies at various divisors. Table 9 provides the potential range of L2CLK
output AC timing specifications as defined in Figure 7.
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN
input of the MPC7410 to synchronize L2CLK_OUT at the SRAM with the processor’s internal clock. L2CLK_OUT
at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2SYNC_OUT
to L2SYNC_IN. See Freescale Application Note AN1794, Backside L2 Timing Analysis for the PCB Design
Engineer.
The minimum L2CLK frequency in Table 9 is specified by the maximum delay of the internal DLL. The variable-tap
DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT signals
so that the returning L2SYNC_IN signal is phase-aligned with the next core clock (divided by the L2 divisor ratio).
Do not choose a core-to-L2 divisor that results in an L2 frequency below this minimum, or the L2CLK_OUT signals
provided for SRAM clocking will not be phase-aligned with the MPC7410 core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 9 is the core frequency divided by one. Very few L2 SRAM
designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer
L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of
the MPC7410 will be a function of the AC timings of the MPC7410, the AC timings for the SRAM, bus loading,
and printed-circuit board trace length.
Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part
on a functional tester at the maximum frequencies in Table 9. Therefore, functional operation and AC timing
information are tested at core-to-L2 divisors of two or greater.
L2 input and output signals are latched or enabled, respectively, by the internal L2CLK (which is SYSCLK
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings in
Table 10 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through
the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLK_OUTA and
L2CLK_OUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system
L2SYNC_IN is held in phase-alignment with the internal L2CLK, the signals in Table 10 are referenced to this
signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually
measured relative to SYSCLK.
Table 9. L2CLK Output AC Timing Specifications
At recommended operating conditions (see Table 3)
400 MHz
Parameter
450 MHz
500 MHz
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
L2CLK frequency
fL2CLK
133
400
133
400
133
400
MHz
1, 4
L2CLK cycle time
tL2CLK
2.5
7.5
2.5
7.5
2.5
7.5
ns
—
L2CLK duty cycle
tCHCL/tL2CLK
%
2
50
50
50
Internal DLL-relock time
—
640
—
640
—
640
—
L2CLK
3
DLL capture window
—
0
10
0
10
0
10
ns
5
L2CLK_OUT
output-to-output skew
tL2CSKW
—
50
—
50
—
50
ps
6
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
18
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 9. L2CLK Output AC Timing Specifications (continued)
At recommended operating conditions (see Table 3)
400 MHz
Parameter
450 MHz
500 MHz
Symbol
L2CLK_OUT output jitter
—
Min
Max
Min
Max
Min
Max
—
±150
—
±150
—
±150
Unit
Notes
ps
6
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core
frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their
respective maximum or minimum operating frequencies. The maximum L2CLK frequency will be system
dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL-relock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of
L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. This adds more delay to each tap of
the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward
or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between
L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter
on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already
comprehended in the AC timing and does not have to be considered in the L2 timing analysis.
The L2CLK_OUT timing diagram is shown in Figure 7.
L2 Single-Ended Clock Mode
tL2CF
tL2CR
tL2CLK
tCHCL
L2CLK_OUTA
L2CLK_OUTB
VM
VM
VM
VM
VM
VM
VM
tL2CSKW
VM
L2SYNC_OUT
VM
VM
VM
L2 Differential Clock Mode
tL2CLK
L2CLK_OUTB
tCHCL
L2CLK_OUTA
VM
VM
VM
L2SYNC_OUT
VM
VM
VM
VM = Midpoint Voltage (L2OVDD/2)
Figure 7. L2CLK_OUT Output Timing Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
19
Electrical and Thermal Characteristics
4.2.4
L2 Bus AC Specifications
Table 10 provides the L2 bus interface AC timing specifications for the MPC7410 as defined in Figure 8 and
Figure 9 for the loading conditions described in Figure 10.
Table 10. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (see Table 3)
400, 450, 500 MHz
Parameter
Symbol
Min
Max
Unit
Notes
L2SYNC_IN rise and fall time
tL2CR and tL2CF
—
1.0
ns
1
Setup times: Data and parity
tDVL2CH
1.5
—
ns
2
Input hold times: Data and parity
tDXL2CH
—
0.0
ns
2
ns
3, 4
—
—
—
—
2.5
2.5
2.9
3.5
ns
3
0.4
0.8
1.2
1.6
—
—
—
—
ns
—
—
—
—
—
2.0
2.5
3.0
3.5
tL2CHOV
Valid times:
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
00
01
10
11
Output hold times
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
00
01
10
11
L2SYNC_IN to high impedance:
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
All outputs when L2CR[14–15] =
00
01
10
11
tL2CHOX
tL2CHOZ
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-Ω load (see Figure 10).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous
BurstRAMs, L2CR[14–15] = 00 is recommended. For pipelined late write synchronous BurstRAMs,
L2CR[14–15] = 10 is recommended.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
20
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC7410.
tL2CR
L2SYNC_IN
tL2CF
VM
tDVL2CH
tDXL2CH
L2 Data and
Data Parity
Inputs
VM = Midpoint Voltage (L2OVDD/2)
Figure 8. L2 Bus Input Timing Diagrams
Figure 9 shows the L2 bus output timing diagrams for the MPC7410.
L2SYNC_IN
VM
VM
tL2CHOV
tL2CHOX
All Outputs
tL2CHOZ
L2DATA Bus
VM = Midpoint Voltage (L2OVDD/2)
Figure 9. L2 Bus Output Timing Diagrams
Figure 10 provides the AC test load for L2 interface of the MPC7410.
Output
Z0 = 50 Ω
R L = 50 Ω
L2OVDD/2
Figure 10. AC Test Load for the L2 Interface
4.2.5
IEEE 1149.1 AC Timing Specifications
Table 11 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12 through Figure 15.
Table 11. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
0
33.3
MHz
—
TCK cycle time
t TCLK
30
—
ns
—
TCK clock pulse width measured at OVDD/2
tJHJL
15
—
ns
—
tJR and tJF
0
2
ns
—
TCK rise and fall times
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
21
Electrical and Thermal Characteristics
Table 11. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions (see Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
tTRST
25
—
ns
2
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
—
—
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
—
—
Boundary-scan data
TDO
tJLDV
tJLOV
4
4
20
25
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
3
19
9
TRST assert time
Input setup times:
ns
3
ns
Input hold times:
3
Valid times:
ns
4
ns
4, 5
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC7410.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 11. Alternate AC Test Load for the JTAG Interface
Figure 12 provides the JTAG clock input timing diagram.
TCLK
VM
VM
tJHJL
VM
tJR
tJF
tTCLK
VM = Midpoint Voltage (OVDD/2)
Figure 12. JTAG Clock Input Timing Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
22
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 13 provides the TRST timing diagram.
VM
TRST
VM
tTRST
VM = Midpoint Voltage (OV DD/2)
Figure 13. TRST Timing Diagram
Figure 14 provides the boundary-scan timing diagram.
TCK
VM
VM
tDVJH
Boundary
Data Inputs
tDXJH
Input
Data Valid
tJLDV
tJLDX
Boundary
Data Outputs
Output Data Valid
tJLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 14. Boundary-Scan Timing Diagram
Figure 15 provides the test access port timing diagram.
TCK
VM
VM
tIVJH
tIXJH
Input
Data Valid
TDI, TMS
tJLOV
tJLOX
Output Data Valid
TDO
tJLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 15. Test Access Port Timing Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
23
Pin Assignments
5
Pin Assignments
Figure 16, part A shows the pinout for the MPC7410, 360 CBGA, 360 HCTE, and 360 HCTE Lead Free C5 Spheres
packages as viewed from the top surface. Figure 16, part B shows the side profile of the CBGA and HCTE_CBGA
packages to indicate the direction of the top surface view. Figure 16, part C shows the side profile of the
HCTE_LGA package to indicate the direction of the top surface view.
Part A
1
2
3
4
5
6
7
8
9
10
11 12 13
14 15 16
17 18 19
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Not to Scale
Part B
Substrate Assembly
Encapsulant
View
BGA Package
Die
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
24
Freescale Semiconductor
Pinout Listings
Part C
Substrate Assembly
View
LGA Package
Encapsulant
Die
Figure 16. Pinout of the MPC7410, 360 CBGA and 360 HCTE Packages
as Viewed from the Top Surface
6
Pinout Listings
Table 12 provides the pinout listing for the MPC7410 360 CBGA, 360 HCTE packages.
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages
Pin Number
Active
I/O
I/F Select 1
A[0:31]
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3,
G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3,
J2, J6, K3, K2, L2
High
I/O
BVSEL
AACK
N3
Low
Input
BVSEL
—
ABB
L7
Low
Output
BVSEL
12, 16
AP[0:3]
C4, C5, C6, C7
High
I/O
BVSEL
—
ARTRY
L6
Low
I/O
BVSEL
—
AVDD
A8
—
Input
VDD
—
BG
H1
Low
Input
BVSEL
—
BR
E7
Low
Output
BVSEL
—
BVSEL
W1
High
Input
N/A
1, 3, 8,
9, 14
CHK
K11
Low
Input
BVSEL
2, 8, 9
CI
C2
Low
I/O
BVSEL
—
CKSTP_IN
B8
Low
Input
BVSEL
—
CKSTP_OUT
D7
Low
Output
BVSEL
—
CLK_OUT
E3
High
Output
BVSEL
—
DBB
K5
Low
Output
BVSEL
12, 16
DBG
K1
Low
Input
BVSEL
—
DH[0:31]
W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9,
W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4,
P7, V5, V4, W3, U4, R5
High
I/O
BVSEL
—
Signal Name
Notes
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
25
Pinout Listings
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Pin Number
Active
I/O
I/F Select 1
Notes
DL[0:31]
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12,
P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1,
V1, U1, N1, R2, V3, U3, W2
High
I/O
BVSEL
—
DP[0:7]
L1, P2, M2, V2, M1, N2, T3, R1
High
I/O
BVSEL
—
DRDY
K9
Low
Output
BVSEL
6, 8, 13
DBWO
DTI[0]
D1
Low
Input
BVSEL
—
DTI[1:2]
H6, G1
High
Input
BVSEL
5, 10, 13
EMODE
A3
Low
Input
BVSEL
7, 10
GBL
B1
Low
I/O
BVSEL
—
GND
D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16,
G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10,
K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11,
P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16
—
—
N/A
—
HIT
B5
Low
Output
BVSEL
6, 8
HRESET
B6
Low
Input
BVSEL
—
INT
C11
Low
Input
BVSEL
—
L1_TSTCLK
F8
High
Input
BVSEL
2
L2ADDR[0:16]
L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16,
H18, H17, J14, J13, H19, G18
High
Output
L2VSEL
—
L2ADDR[17:18]
K19,W19
High
Output
L2VSEL
8
L2AVDD
L13
—
Input
VDD
—
L2CE
P17
Low
Output
L2VSEL
—
L2CLK_OUTA
N15
High
Output
L2VSEL
—
L2CLK_OUTB
L16
High
Output
L2VSEL
—
L2DATA[0:63]
U14, R13, W14, W15, V15, U15, W16, V16, W17, V17,
U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17,
R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18,
H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18,
E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18,
A17, A16, B16, C16, A14, A15, C15, B14, C14, E13
High
I/O
L2VSEL
—
L2DP[0:7]
V14, U16, T19, N18, H14, F17, C19, B15
High
I/O
L2VSEL
—
L2OVDD
D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16,
T15, F15
—
—
N/A
11
L2SYNC_IN
L14
High
Input
L2VSEL
—
L2SYNC_OUT
M14
High
Output
L2VSEL
—
L2_TSTCLK
F7
High
Input
BVSEL
2
Signal Name
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
26
Freescale Semiconductor
Pinout Listings
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
L2VSEL
A19
High
Input
N/A
1, 3, 8,
9, 14
L2WE
N16
Low
Output
L2VSEL
—
L2ZZ
G17
High
Output
L2VSEL
—
LSSD_MODE
F9
Low
Input
BVSEL
2
MCP
B11
Low
Input
BVSEL
15
OVDD
D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4,
R6, R9, R11, T5, T8, T12
—
—
N/A
—
PLL_CFG[0:3]
A4, A5, A6, A7
High
Input
BVSEL
4
QACK
B2
Low
Input
BVSEL
—
QREQ
J3
Low
Output
BVSEL
—
RSRV
D3
Low
Output
BVSEL
—
SHD0
B3
Low
I/O
BVSEL
8
SHD1
B4
Low
I/O
BVSEL
5, 8
SMI
A12
Low
Input
BVSEL
—
SRESET
E10
Low
Input
BVSEL
—
SYSCLK
H9
—
Input
BVSEL
—
TA
F1
Low
Input
BVSEL
—
TBEN
A2
High
Input
BVSEL
—
TBST
A11
Low
Output
BVSEL
—
TCK
B10
High
Input
BVSEL
—
TDI
B7
High
Input
BVSEL
9
TDO
D9
High
Output
BVSEL
—
TEA
J1
Low
Input
BVSEL
—
TMS
C8
High
Input
BVSEL
9
TRST
A10
Low
Input
BVSEL
9
TS
K7
Low
I/O
BVSEL
—
TSIZ[0:2]
A9, B9, C9
High
Output
BVSEL
—
TT[0:4]
C10, D11, B12, C12, F11
High
I/O
BVSEL
—
WT
C3
Low
I/O
BVSEL
—
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
27
Pinout Listings
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Signal Name
VDD
Pin Number
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
Active
I/O
I/F Select 1
Notes
—
—
N/A
—
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and
L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT)
and the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become
AVDD and L2AV DD, respectively). These columns serve as a reference for the nominal voltage supported on a given signal
as selected by the BVSEL/L2VSEL pin configurations of Table 2 and the voltage supplied. For actual recommended value
of Vin or supply voltages, see Table 3.
2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD,
GND, HRESET, or ¬HRESET. For the MPC7410 the L2 bus only supports 2.5- and 1.8-V options. The default selection, if
L2VSEL is left unconnected, is 2.5-V operation. For the MPC7410 the processor bus supports 3.3-, 2.5-, and 1.8-V options.
The default selection, if BVSEL is left unconnected, is 3.3-V operation. Refer to Table 2 for supported BVSEL and L2VSEL
settings.
4. PLL_CFG[0:3] must remain stable during operation; should only be changed during the assertion of HRESET or during sleep
mode and must adhere to the internal PLL-relock time requirement.
5. Ignored input in 60x bus mode.
6. Unused output in 60x bus mode. Signal is three-stated in 60x mode.
7. Deasserted (pulled high) at HRESET negation for 60x bus mode. Asserted (pulled low) at HRESET negation for MPX bus
mode.
8. Uses one of nine existing no connects in the MPC750 360 BGA package.
9. Internal pull up on die. Pulled-up signals are VDD based.
10.Reuses MPC750 DRTRY, DBDIS, and TLBISYNC pins (DTI1, DTI2, and EMODE, respectively).
11.The VOLTDET pin position on the MPC750 360 BGA package is now an L2OVDD pin on the MPC7410 360 package.
12.Output only for MPC7410, was I/O for MPC750.
13.MPX bus mode only.
14.If necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down
resistance less than 250 Ω should be used.
15.MCP minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles to
guarantee that it is latched by the processor.
16.In MPX bus mode the ABB signal is called AMON and the DBB signal is called DMON. These signals are not a requirement
of the MPX bus protocol and may not be available on future products.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
28
Freescale Semiconductor
Package Description
7
Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC7410, 360 CBGA
and 360 HCTE packages.
7.1 Package Parameters for the MPC7410, 360 CBGA and
360 HCTE_CBGA
The package parameters are as provided in the following list. The package types are the 25 × 25 mm, 360-lead
ceramic ball grid array package (CBGA) or the 25 × 25 mm, 360-lead high coefficient of thermal expansion CBGA
package (HCTE_CBGA).
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Ball diameter
Coefficient of thermal expansion
25 × 25 mm
360 (19 × 19 ball array – 1)
1.27 mm (50 mil)
2.72 mm
3.20 mm
0.89 mm (35 mil)
6.8 ppm/°C (CBGA)
12.3ppm/°C (HCTE_CBGA)
7.2 Package Parameters for the MPC7410, 360 HCTE_CBGA (Lead
Free C5 Spheres)
The package parameters are as listed here. The package types are the 25 × 25 mm, 360-lead high coefficient of
thermal expansion CBGA package with lead-free C5 spheres (HCTE_CBGA lead-free spheres).
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Ball diameter
Coefficient of thermal expansion
25 × 25 mm
360 (19 × 19 ball array – 1)
1.27 mm (50 mil)
2.32 mm
2.80 mm
0.76 mm (30 mil)
12.3ppm/°C
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
29
Package Description
7.3 Mechanical Dimensions for the MPC7410, 360 CBGA and
360 HCTE_CBGA
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410, 360 CBGA and
360 HCTE_CBGA packages.
2X
0.2
D
D2
D4
A1 CORNER
Capacitor Region
A
C
0.15 C
// 0.25 C
E
E2
// 0.35 C
E4
K3
L3
L4
K2
K1
0.2
K4
B
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
MIN
MAX
A
2.72
3.20
A1
0.80
1.00
A2
1.10
1.30
A3
—
0.60
A4
0.82
0.90
b
0.82
0.93
25.00 BSC
D2
—
12.50
D4
6.00
9.00
e
1.27 BSC
E
25.00 BSC
E2
—
14.30
E4
8.00
11.00
F
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819
F
DIM
D
L2 L1
2X
Millimeters
22.86 BSC
K1
—
K2
6.46
9.75
—
K3
8.20
8.60
K4
2.75
—
L1
—
9.50
A3
A2
L2
6.94
—
L3
3.10
3.30
A4
A1
A
L4
3.00
—
F
360X
b
0.3 C A B
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH
VARIOUS SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED WITH A
BALL MISSING FROM THE ARRAY.
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,
360 CBGA and 360 HCTE_CBGA Packages
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
30
Freescale Semiconductor
Package Description
7.4 Mechanical Dimensions for the MPC7410, 360 HCTE_CBGA
(Lead Free C5 Spheres)
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410,
360 HCTE_CBGA (lead-free C5 spheres) package.
2X
0.2
D
D2
D4
A1 CORNER
Capacitor Region
A
C
0.15 C
// 0.25 C
E
E2
// 0.35 C
E4
K3
L3
L4
K2
K1
0.2
K4
B
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
MIN
MAX
A
2.32
2.80
A1
0.40
0.60
A2
1.10
1.30
A3
—
0.60
A4
0.82
0.90
b
0.60
0.90
25.00 BSC
D2
—
12.50
D4
6.00
9.00
e
1.27 BSC
E
25.00 BSC
E2
—
14.30
E4
8.00
11.00
F
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819
F
DIM
D
L2 L1
2X
Millimeters
22.86 BSC
K1
—
K2
6.46
9.75
—
K3
8.20
8.60
K4
2.75
—
L1
—
9.50
A3
A2
L2
6.94
—
L3
3.10
3.30
A4
A1
A
L4
3.00
—
F
360X
b
0.3 C A B
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH
VARIOUS SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED WITH A
BALL MISSING FROM THE ARRAY.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410
360 HCTE_CBGA (Lead-Free C5 Spheres) Package
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
31
Package Description
7.5 Package Parameters for the MPC7410, 360 HCTE_LGA
The package parameters are as listed here. The package type is the 25 × 25 mm, 360 high coefficient of thermal
expansion LGA package (HCTE_LGA).
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Coefficient of thermal expansion
25 × 25 mm
360 (19 × 19 land array – 1)
1.27 mm (50 mil)
1.92 mm
2.20 mm
12.3ppm/°C
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
32
Freescale Semiconductor
Package Description
7.5.1
Mechanical Dimensions for the MPC7410, 360 HCTE_LGA
Figure 19 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410, 360 HCTE_LGA
package.
2X
0.2
D
D2
D4
A1 CORNER
Capacitor Region
A
DIM
C
// 0.25 C
E
E2
// 0.35 C
E4
Millimeters
0.1
L2 L1
K3
A
1.92
2.20
1.10
1.30
A3
—
0.60
A4
0.82
0.90
b
0.79
0.99
D
K2
K1
0.2
K4
B
—
12.50
D4
6.00
9.00
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
F
e
A3
A2
A4
A
1.27 BSC
25.00 BSC
E2
—
14.30
E4
8.00
11.00
F
1 2 3 4 5 6 7 8 9 10 111213141516 171819
25.00 BSC
D2
E
L4
L3
MAX
A2
e
2X
MIN
22.86 BSC
K1
—
9.75
K2
6.46
—
K3
8.20
8.60
K4
2.75
—
L1
—
9.50
L2
6.94
—
L3
3.10
3.30
L4
3.00
—
F
360X
b
0.3 C A B
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH
VARIOUS SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED WITH A
PAD MISSING FROM THE ARRAY.
Figure 19. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,
360 HCTE_LGA Package
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
33
System Design Information
7.6 Substrate Capacitors for the MPC7410
Figure 20 shows the connectivity of the substrate capacitor pads for the MPC7410, 360 CBGA and 360 HCTE
packages.
Package
Caps
A1 CORNER
C6-2
C6-1
C5-1
C5-2
Value
µF
C1-1
C1-1
C1-2
C1-2
L2OVDD
0.01
C2-1
C2-2
C4-1
C4-2
L2 L1
0.01
C5-2
C3-1
C3-2
GND
OVDD
0.01
C6-1
C6-2
GND
OVDD
0.01
C5-1
C2-2
C2-1
GND
VDD
0.01
C4-1
C4-2
GND
L2OVDD
C3-1
C3-2
Voltage
Reference
GND
VDD
0.01
GND
Figure 20. Substrate Bypass Capacitors for the MPC7410
8
System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC7410.
8.1 PLL Configuration
The MPC7410 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
MPC7410 is shown in Table 13 for example frequencies. In this example, shaded cells represent settings that, for a
given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the minimum and
maximum core frequencies listed in Table 8.
Table 13. MPC7410 Microprocessor PLL Configuration
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
PLL_CFG
[0:3]
Bus-toCore
Multiplier
Core-to
Bus
VCO
33.3 MHz
Multiplier
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
Bus
83.3 MHz 100 MHz
Bus
133 MHz
0100
2x
2x
—
—
—
—
—
—
—
0110
2.5x
2x
—
—
—
—
—
—
—
1000
3x
2x
—
—
—
—
—
—
400
(800)
1110
3.5x
2x
—
—
—
—
—
350
(700)
465
(930)
1010
4x
2x
—
—
—
—
—
400
(800)
—
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
34
Freescale Semiconductor
System Design Information
Table 13. MPC7410 Microprocessor PLL Configuration (continued)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
PLL_CFG
[0:3]
Bus-toCore
Multiplier
Core-to
Bus
VCO
33.3 MHz
Multiplier
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
Bus
83.3 MHz 100 MHz
Bus
133 MHz
0111
4.5x
2x
—
—
—
—
375
(750)
450
(900)
—
1011
5x
2x
—
—
—
375
(750)
416
(833)
500
(1000)
—
1001
5.5x
2x
—
—
366
(733)
412
(825)
458
(916)
—
—
1101
6x
2x
—
—
400
(800)
450
(900)
500
(1000)
—
—
0101
6.5x
2x
—
—
433
(866)
488
(967)
—
—
—
0010
7x
2x
—
350
(700)
466
(933)
—
—
—
—
0001
7.5x
2x
—
375
(750)
500
(1000)
—
—
—
—
1100
8x
2x
—
400
(800)
—
—
—
—
—
0000
9x
2x
—
450
(900)
—
—
—
—
—
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7410; see Section 4.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use and third-party emulator tool
development only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7410 regardless of the SYSCLK input.
5. PLL-off mode should not be used during chip power-up sequencing.
The MPC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL)
circuit and should be routed from the MPC7410 to the external RAMs. A separate clock output, L2SYNC_OUT is
sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the
rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2
bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally,
the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
35
System Design Information
MPC7410 core, and the phase adjustment range that the L2 DLL supports. Table 14 shows various example L2 clock
frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 133 MHz.
Sample core-to-L2 frequencies for the MPC7410 is shown in Table 14. In this example, shaded cells represent
settings that, for a given core frequency, result in L2 frequencies that do not comply with the minimum and
maximum L2 frequencies listed in Table 10.
Table 14. Sample Core-to-L2 Frequencies
Core Frequency
(MHz)
÷1
÷1.5
÷2
÷2.5
÷3
÷3.5
÷4
350
350
233
175
140
—
—
—
366
366
244
183
147
—
—
—
400
400
266
200
160
133
—
—
433
—
288
216
173
144
—
—
450
—
300
225
180
150
—
—
466
—
311
233
186
155
133
—
500
—
333
250
200
166
143
—
Note: The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not tested
for by the MPC7410; see Section 4.2.3, “L2 Clock AC Specifications,” for valid
L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less
than 150 MHz.
8.2 PLL and DLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC7410 to supply power to the PLL and DLL,
respectively. Both AVDD and L2AVDD can be supplied power from the VDD power plane. High frequency noise in
the 500 kHz to 10 MHz resonant frequency range of the PLL on the V DD power plane could affect the stability of
the internal clocks.
On systems that use the MPC7410 HCTE device, the AVDD and L2AVDD input signals should both implement the
circuit shown in Figure 21.
On systems that use the MPC7410 CBGA device, the L2AVDD input should implement the circuit shown in
Figure 21.
When selecting which filter to use on the AVDD input of the MPC7410 CBGA device specifically, system designers
should refer to Erratum No. 18 in the MPC7410 RISC Microprocessor Chip Errata (MPC7410CE). The AVDD input
of the MPC7410 CBGA device is sensitive to system noise on both the VDD power plane, as described above, and
the OVDD power plane as described in the Erratum No. 18. With these AVDD sensitivities to OVDD and VDD noise,
care must be taken when selecting the filter circuit for the AVDD input of the MPC7410 CBGA device. Erratum
No. 18 does not apply to the AVDD input of the MPC7401 HCTE device, nor does it affect the L2AVDD input of
either the HCTE or the CBGA device.
As described in Erratum No. 18, when there is a high amount of noise on the OVDD power plane due to I/O switching
rates, it is possible for the OVDD noise to couple into the PLL supply voltage (AVDD) internal to the MPC7410
CBGA package. It is the recommendation of Freescale, that new designs using the MPC7410 CBGA package
provide the ability to implement either filter shown in Figure 21 and Figure 22 at the AVDD input. Existing designs
that implemented Figure 21 on AVDD may never experience the error described in Erratum No. 18. Both new and
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
existing designs should qualify both AVDD filter solutions, and the filter providing the most robust margin should
be implemented.
10 Ω
AVDD (or L2AV DD)
VDD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 21. PLL Power Supply Filter Circuit No.1
51 Ω
AVDD
VDD
Capacitor
Pad Sites
GND
Figure 22. PLL Power Supply Filter Circuit No. 2
The filter circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. A separate circuit should be placed as close as possible to the L2AVDD pin. It is often possible to route
directly from the capacitors to the AVDD pin, which is on the periphery of the 360 BGA footprint, without the
inductance of vias. The L2AV DD pin may be more difficult to route, but is proportionately less critical.
It is the recommendation of Freescale, that systems that implement the AVDD filter shown in Figure 22 design in the
pads for the removed capacitors (shown in Figure 21), to provide for the possible reintroduction of the filter in
Figure 21. This would be necessary in case there is a planned transition from the CBGA package to the HCTE
package of the MPC7410.
8.3 Decoupling Recommendations
Due to the MPC7410 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7410 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC7410 system, and the MPC7410 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD
pin of the MPC7410. It is also recommended that these decoupling capacitors receive their power from separate
VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0508 or 0603 orientations, where connections are made
along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
VDD, L2OV DD, and OV DD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON).
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
8.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level
through a resistor. Unused active low inputs should be tied to OV DD. Unused active high inputs should be connected
to GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the MPC7410.
Note that power must be supplied to L2OVDD even if the L2 interface of the MPC7410 will not be used; the
remainder of the L2 interface may be left unterminated.
8.5 Output Buffer DC Impedance
The MPC7410 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure Z 0, an
external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until
the pad voltage is OVDD/2 (see Figure 23).
The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals (L2)OVDD/2.
RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and
RP is trimmed until the voltage at the pad equals (L2)OV DD/2. RP then becomes the resistance of the pull-up devices.
RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
Figure 23 describes the driver impedance measurement circuit described above.
OVDD
RN
SW2
Data
Pad
SW1
RP
OGND
Figure 23. Driver Impedance Measurement Circuit
Alternately, the following is another method to determine the output impedance of the MPC7410. A voltage source,
Vforce, is connected to the output of the MPC7410, as in Figure 24. Data is held low, the voltage source is set to a
value that is equal to (L2)OVDD/2, and the current sourced by Vforce is measured. The voltage drop across the
pull-down device, which is equal to (L2)OVDD/2, is divided by the measured current to determine the output
impedance of the pull-down device, RN. Similarly, the impedance of the pull-up device is determined by dividing
the voltage drop of the pull-up, (L2)OVDD/2, by the current sank by the pull-up when the data is high and Vforce is
equal to (L2)OVDD/2. This method can be employed with either empirical data from a test setup or with data from
simulation models, such as IBIS.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 24 describes the alternate
driver impedance measurement circuit.
(L2)OVDD
BGA
Pin
Vforce
Data
OGND
Figure 24. Alternate Driver Impedance Measurement Circuit
Table 15 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and
105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.
Table 15. Impedance Characteristics
VDD = 1.8 V, OVDD = 2.5 V, Tj = 0° – 105°C
Impedance
Processor Bus
L2 Bus
Symbol
Unit
RN
41.5–54.3
42.7–54.1
Z0
Ω
RP
37.3–55.3
39.3–50.0
Z0
Ω
8.6 Pull-Up Resistor Requirements
The MPC7410 requires pull-up resistors (1 kΩ–5 kΩ) on several control pins of the bus interface to maintain the
control signals in the negated state after they have been actively negated and released by the MPC7410 or other bus
masters. These pins are: TS, ARTRY, SHDO, SHD1.
Four test pins also require pull-up resistors (100 Ω−1 kΩ). These pins are CHK, L1_TSTCLK, L2_TSTCLK, and
LSSD_MODE. These signals are for factory use only and must be pulled up to OV DD for normal machine
operation.
If pull-down resistors are used to configure BVSEL or L2VSEL, the resistors should be less than 250 Ω (see Table
12). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and pull-down resistors
(1 kΩ or less) are recommended to configure these signals in order to protect against erroneous switching due to
ground bounce, power supply noise or noise coupling.
In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 kΩ–5 kΩ) if it is used by
the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (1 kΩ–5 kΩ) to prevent
erroneous assertions of this signal.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may,
therefore, float in the high-impedance state for relatively long periods of time. Since the MPC7410 must continually
monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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39
System Design Information
the MPC7410 or by other receivers in the system. These signals can be pulled up through weak (10-kΩ) pull-up
resistors by the system, address bus driven mode can be enabled (see the MPC7410 RISC Microprocessor Family
Users’ Manual for more information on this mode), or these signals may be otherwise driven by the system during
inactive periods of the bus to avoid this additional power draw. The snooped address and transfer attribute inputs
are: A[0:31], AP[0:3], TT[0:4], CI, WT, and GBL.
In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction while not
driving GBL to the processor, we recommend that a strong (1 kΩ) pull-up resistor be used on GBL. Note that the
MPC7410 will only snoop transactions when GBL is asserted.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not
require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that
those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are:
DH[0:31], DL[0:31], and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the
input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left
unconnected by the system. If parity checking is disabled through HID0, and parity generation is not required by the
MPC7410 (note that the MPC7410 always generates parity), then all parity pins may be left unconnected by the
system.
The L2 interface does not normally require pull-up resistors.
8.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE
1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible
to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is
also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 25 allows the COP port to independently assert HRESET or TRST, while ensuring
that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be
tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the
COP header be designed into the system as shown in Figure 25, if this is not possible, the isolation resistor will allow
future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 25 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Freescale Semiconductor
System Design Information
From Target
Board Sources
(if any)
SRESET
SRESET
HRESET
HRESET 6
QACK
13
11
HRESET
10 kΩ
SRESET
10 kΩ
OVDD
OVDD
10 kΩ
OVDD
10 kΩ
OVDD
0Ω5
1
2
3
4
5
6
7
8
9
10
11
12
VDD_SENSE
6
5
CHKSTP_OUT
10 kΩ
Key
14 2
10 kΩ
OVDD
OVDD
CHKSTP_IN
COP Header
COP Connector
Physical Pin Out
OVDD
OVDD
CHKSTP_OUT
KEY
16
10 kΩ
2 kΩ
1
15
13 No Pin
15
TRST 6
TRST
4
CHKSTP_IN
8
TMS
9
1
3
TMS
TDO
TDO
TDI
TDI
TCK
7
TCK
QACK
2
10
NC
12
NC
16
QACK
2 kΩ 3
OV DD
10 kΩ
10 kΩ 4
OV DD
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7410. Connect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.
6. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above.
Figure 25. COP Connector Diagram
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
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System Design Information
The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100"
centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector
key.
There is no standardized way to number the COP header shown in Figure 25; consequently, many different pin
numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while
others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with
an IC). Regardless of the numbering, the signal placement recommended in Figure 25 is common to all known
emulators.
The QACK signal shown in Figure 25 is usually connected to the PCI bridge chip in a system and is an input to the
MPC7410 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power
mode selection. In order for COP to work, the MPC7410 must see this signal asserted (pulled down). While shown
on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be
populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can
only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated
when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation,
QACK should be merged via logic so that it also can be driven by the PCI bridge.
8.8 Thermal Management Information
This section provides thermal management information for the MPC7410 for air-cooled applications. Proper
thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal
interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several
methods such as spring clip to holes in the printed circuit board or with screws and springs to the printed circuit
board; see Figure 26 for the BGA package and Figure 27 for the LGA package. This spring force should not exceed
5.5 pounds of force. Note that care should be taken to avoid focused forces being applied to die corners and/or edges
when mounting heat sinks.
Heat Sink
BGA Package
Heat Sink
Clip
Thermal Interface Material
Printed-Circuit Board
Figure 26. BGA Package Exploded Cross-Sectional View with Heat Sink Clip to PCB Option
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
Heat Sink
LGA Package
Heat Sink
Clip
Thermal
Interface Material
Printed-Circuit Board
Figure 27. LGA Package Exploded Cross-Sectional View with Heat Sink Clip to PCB Option
The board designer can choose between several types of heat sinks to place on the MPC7410. There are several
commercially-available heat sinks for the MPC7410 from the following vendors:
Aavid Thermalloy
70 Commercial Street, Suite 200
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
Alpha Novatech
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
408-567-8082
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
800-347-4572
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
818-842-7277
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-635-2800
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at
a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
8.8.1 Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance paths are
as follows:
•
•
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
The die junction-to-ball thermal resistance
Figure 28 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit
board.
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach
material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection.
Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may
be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the
dominant terms.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
External Resistance
Radiation
Convection
Note the internal versus external package resistance.
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
8.8.2 Adhesives and Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 29 shows
the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare
joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal
interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the
interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater
than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 26).
This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal
performance, considering the low interface pressure. Of course, the selection of any thermal interface material
depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric
properties, cost, and so on.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
Figure 29 describes the thermal performance of selected thermal interface materials.
Silicone Sheet (0.006")
Bare Joint
Floroether Oil Sheet (0.007")
Graphite/Oil Sheet (0.005")
Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
Contact Pressure (psi)
Figure 29. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be
selected based on high conductivity, yet adequate mechanical strength to meet equipment shock/vibration
requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the
following vendors:
Chomerics, Inc.
77 Dragon Court
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dow.com
800-248-2481
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
888-642-7674
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
Thermagon Inc.
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
888-246-9050
8.8.3 Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = Ta + Tr + (θjc + θint + θsa) × Pd
where:
Tj is the die-junction temperature
Ta is the inlet cabinet ambient temperature
Tr is the air temperature rise within the computer cabinet
θjc is the junction-to-case thermal resistance
θint is the adhesive or interface material thermal resistance
θsa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device
During operation the die-junction temperatures (T j) should be maintained less than the value specified in Table 3.
The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air
temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30°
to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of
the thermal interface material (θint) is typically about 1°C/W. Assuming a Ta of 30°C, a Tr of 5°C, a CBGA package
θjc = 0.03, and a power consumption (Pd) of 5.0 W, the following expression for Tj is obtained:
Die-junction temperature:
Tj = 30°C + 5°C + (0.03°C/W + 1.0°C/W + θsa) × 5.0 W
For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) versus airflow velocity is
shown in Figure 30.
Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7°C/W, thus
Tj = 30°C + 5°C + (0.03°C/W + 1.0°C/W + 7°C/W) × 5.0 W,
resulting in a die-junction temperature of approximately 75°C which is well within the maximum operating
temperature of the component.
Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, The Bergquist Company, IERC, and Wakefield
Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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System Design Information
8
Thermalloy #2328B Pin-Fin Heat Sink
(25 × 28 × 15 mm)
Heat Sink Thermal Resistance (ºC/W)
7
6
5
4
3
2
1
0
0.5
1
1.5
2
2.5
Approach Air Velocity (m/s)
3
3.5
Figure 30. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit
used for comparing the thermal performance of various microelectronic packaging technologies, one should
exercise caution when only using this metric in determining thermal management because no single parameter can
adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function
of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to
the component's power consumption, a number of factors affect the final operating die-junction
temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink
attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on.
Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic
equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary
widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as,
system-level designs.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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47
Document Revision History
9
Document Revision History
Table 16 provides a revision history for this hardware specification.
Table 16. Document Revision History
Revision
6.1
6
Date
Substantive Change(s)
11/16/2007 Updated Table 17 and Table 19 to show the VU package is available as an MC prefix device compared
to an MPC prefix for the other package types; this was done to match the specification documents
with the device ordering and part marking information.
Updated title of Table 19 to reflect correct name of referenced document and updated respective
document order information below table.
Updated notes in Table 1–Table 3 replacing references to MPC7410RX nnnLE with Mxx7410xxnnnLE
since notes to apply to all the available packages types.
8/14/2007
Updated Table 4 thermal information:
• Deleted rows on single-layer (1s) boards.
• CBGA package R θJMA for natural convection for four layer boards changed from 17 to 18 °C/W.
• HCTE package RθJMA for natural convection for four layer boards changed from 22 to 20 °C/W.
• HCTE package RθJMA for 200 ft./min airflow for four layer boards changed from 19 to 16 °C/W with
airflow rate specification changed from 200 ft./min to 1 m/sec.
• HCTE package RθJMA for 400 ft./min airflow for four layer boards changed from 18 to 15 °C/W with
airflow rate specification changed from 400 ft./min to 2 m/sec.
• CBGA package R θJB changed from 8 to 9°C/W.
• HCTE package RθJB changed from 14 to 11°C/W.
• Table 4 Notes 2 - 4 have been revised and updated; Note 5 is no longer used. Notes on table rows
have been renumbered.
Updated Figure 26 removing optional heat sink clip to package.
Removed references in document to adhesive attached thermal solutions.
Updated thermal solution vendor information in Section 8.8.
Added HCTE_CBGA Lead Free C5 Spheres (VU) packaging information to document:
• Added Section 7.2, “Package Parameters for the MPC7410, 360 HCTE_CBGA (Lead Free C5
Spheres).
• Added Figure 18 for HCTE_CBGA Lead Free C5 Spheres package, similar to Figure 17 but with
differences in dimensions A, A1, and b in the figure’s dimension table.
• Added HCTE_CBGA Lead Free C5 Spheres (VU) packaging information in Table 17 and Table 19.
• Changed part marking example in Figure 31 to an HCTE_CBGA device.
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Document Revision History
Table 16. Document Revision History (continued)
Revision
Date
5
4/13/2005
Substantive Change(s)
Section numbering revised. In all previous versions, section numbering began with ‘1.’ These extra
‘1’s’ were deleted. For example, previously numbered section 1.8.2 changed to 8.2.
Section 7.1—added CTE value for HCTE package. Corrected minimum module height from 2.65 mm
to 2.72 mm per Figure 17.
Section 3—added HCTE_LGA (VS package descriptor) package description which is the
HCTE_CBGA (HX package descriptor) with the spheres removed.
Table 4—generalized ‘HCTE CBGA’ column to ‘HCTE’ to include both HCTE_CBGA and HCTE_LGA
package thermal characteristics.
Section 5—added HCTE_LGA package. The HCTE_LGA has the same pin assignments as the
CBGA and HCTE_CBGA packages. Added side view Part C for HCTE_LGA.
Section 6—added HCTE_LGA package (VS package descriptor). The HCTE_LGA has the same
pinout listing as the CBGA and HCTE packages.
Section 7.3—added HCTE_LGA package parameters.
Section 7.4—added HCTE_LGA package mechanical dimensions.
Table 17—added HCTE_LGA package (VS package descriptor) to part numbering nomenclature.
4
—
Table 5—Changed measurement test condition IOH from -6mA to –5 mA for VOH and IOL from 6 mA
to 5 mA for VOL per Product Bulletin.
Section 1.8.2—revised text regarding AVDD filter selection for the CBGA package.
3
—
Table 6—Changed note 1 to specify that OVDD and L2OVDD power is typically <5% of VDD power.
Figure 17—revised diagram and dimensions to specify ‘cap regions’ versus individual cap
measurements. Moved individual capacitor placement to separate figure.
Figure 18—Added this figure to show each individual capacitor placement and value.
Figure 22—updated COP Connector Diagram to recommend a weak pull-up resistor on TCK.
2
—
Public release, includes Rev 1.1 changes.
Section 1.7.2—added package capacitor values.
Section 1.8.6—added recommendation that strong pull-up/down resistors be used on the
PLL_CFG[0:3] signals.
Table 8—removed mode input setup and hold times. These inputs adhere to the general input setup
and hold specifications.
Figure 5—revised mode input diagram to show sample points around HRESET negation.
Section 1.3—added HCTE package description.
Figure 22—added note 6 to emphasize that COP emulator and target board need to be able to drive
HRESET and TRST independently to the CPU.
Section 1.8.2—revised section for HCTE package. Added text and figure for AVDD filter for the CBGA
package.
Section 1.8.6—removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST
from snooped transfer attribute list. TBST is an output and is not snooped.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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49
Document Revision History
Table 16. Document Revision History (continued)
Revision
Date
1.1
—
Substantive Change(s)
Internal release.
Table 12—added note 16 for ABB/AMON and DBB/DMON signal clarification.
Table 12—changed CHK note 4 reference to note 2, signal is for factory test only. Changed previous
note 4 (CHK related) to now provide additional PLL info.
Table 1—modified maximum value for OVDD from –0.3 to 3.465 to now be –0.3 to 3.6 and L2OVDD
from –0.3 to 2.6 to now be –0.3 to 2.8. Modified note 6, OVDD for revisions prior to Rev. 1.4 have
maximum value for OVDD of –0.3 to 2.8.
Table 8—removed note 12. L2_TSTCLK is for factory use only (see Table 12, note 2).
Section 1.10.2—revised section to include nomenclature tables for part markings not covered by this
spec.
Figure 2—added that under/overshoot for L2OVDD references tL2CLK while OVDD references tSYSCLK.
Table 4—added HCTE package (HX package descriptor) thermal characteristics.
Section 1.5—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages
have the same pin assignments.
Section 1.6—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages
have the same pinout listings.
Section 1.7—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages
have the same package parameters and dimensions.
Table 17—added HCTE package (HX package descriptor) to part numbering nomenclature.
Table 21—added MPC7410THXnnnLE extended temperature HCTE package part numbers and part
number specification document reference.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Document Revision History
Table 16. Document Revision History (continued)
Revision
Date
1.0
—
Substantive Change(s)
Section 1.3 and Table 3—revised OVDD from 3.3 V ± 100 mV to 3.3 V ± 165 mV.
Table 13—removed unsupported PLL configurations.
Table 12—added note 15 for minimum MCP pulse width, correct note 3 for 3.3-V processor bus
support.
Table 13—revised note 3 to include emulator tool development.
Table 14—removed unsupported Core-to-L2 example frequencies.
Section 1.8.8—updated heat sink vendors list.
Section 1.8.8.2—updated interface vendors list.
Table 1—updated voltage sequencing requirements notes 3 and 4.
Table 4—Updated/added thermal characteristics.
Table 5—removed table and TAU related information, TAU is no longer supported.
Table 6—updated Iin and ITSI leakage current specs.
Section 1.8.3—removed section.
Section 1.10—reformatted section.
Section 1.8.6—changed recommended pull-up resistor value to 1 kW–5 kW. Added AACK, TEA, and
TS to control signals needing pull-ups. Added pull-up resistor value recommendation for
L1_TSTCLK, L2_TSTCLK, and LSSD_MODE factory test signals.
Section 1.8.7—revised text regarding connection of TRST. Combined Figure 22, Figure 23, and Table
17, into Figure 21.
Table 7—corrected min VCO frequencies from 450 to 700 MHz to match min processor frequency of
350 MHz.
Table 2—added note 3 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V OVDD.
Table 3—added notes 5 and 6 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V
OVDD.
Table 5—added note 8 regarding DC voltage limits for JTAG signals.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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51
Document Revision History
Table 16. Document Revision History (continued)
Revision
Date
0.3
—
Substantive Change(s)
Added 3.3 V support on the processor bus (BVSEL).
Table 7—update typical and maximum power numbers for full-on mode in. Removed note 4.
Reworded notes 2 and 3.
Table 9, Note 2—removed reference to application note.
Figure 17—corrected side view datum A to be datum C.
Section 1.8.7—added CI and WT to transfer attribute signals requiring pull-ups.
Section 1.8.7—added 1-kΩ pull-up recommendation to GBL when GBL is not connected.
Table 2— added pull-down resistance necessary for internally pulled-up voltage select pins. Added
3.3-V support for BVSEL.
Table 13—added note 14 for BVSEL, L2VSEL, and TRST pins to address pull-down resistance
necessary for these internally pulled-up pins to recognize a low signal.
Table 6—lowered 2.5 V CVIH from 2.2 to 2.0 V to be compatible with VOH of the MPC107. Added
support for 3.3-V processor bus.
Table 15—modified note 1, use L2CR[L2SL] for L2CLK frequency less than 150 MHz.
Table 8—revised note 2 discussing for 3.3-V bus voltage support.
Table 14—added note 5, do not use PL off during power-up sequence.
Table 1—update output hold times (tL2CHOX).
0.2
—
Corrected Section 1.3—technology from 0.13 µm to 0.18 µm.
Updated Table 7—adds power consumption numbers; adds note on estimated decrease w/o AltiVec.
Updated Table 8—adds minimum values for processor frequency and VCO frequency.
Updated Table 9—input setup, output valid times, output hold times, SYSCLK to output high
impedance.
Updated Table 11—L2SYNC_IN to high impedance.
Updated Figure 17—mechanical dimensions, adds capacitor pad dimensions.
0.1
—
Minor updates.
0
—
Initial release.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Ordering Information
10 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 10.1, “Part
Numbers Addressed by This Specification.” Section 10.2, “Part Numbers Not Fully Addressed by This Document,”
lists the part numbers which do not fully conform to the specifications of this document. These special part numbers
require an additional document called a part number specification.
10.1 Part Numbers Addressed by This Specification
Table 17 provides the Freescale part numbering nomenclature for the MPC7410 Note that the individual part
numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale
sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier
which may specify special application conditions. Each part number also contains a revision code which refers to
the die mask revision number.
Table 17. Part Numbering Nomenclature
Mxx
7410
Product
Part
Code Identifier
MPC
7410
xx
nnn
x
x
Package 1
Processor
Frequency 2
Application
Modifier
Revision Level
RX = CBGA
400
450
500
HX = HCTE_CBGA
L: 1.8 V ± 100 mV C: 1.2; PVR = 800C 1102
0° to 105°C
D: 1.3; PVR = 800C 1103
E: 1.4; PVR = 800C 1104
E: 1.4; PVR = 800C 1104
VS = HCTE_LGA
MC
VU = HCTE_CBGA
(Lead Free C5
Solder Spheres)
400
500
Notes:
1. See Section 7, “Package Description,” for more information on available package types and Table 4 for more
information on thermal characteristics.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may
support other maximum core frequencies.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
53
Ordering Information
10.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are described
in separate part number specifications which supplement and supersede this document, as described in the following
tables.
Table 18. Part Numbers Addressed by MPC7410RXnnnPx Series Part Number Specifications
MPC
7410
RX
nnn
P
x
Product
Code
Part
Identifier
Package
Processor
Frequency 1
Application
Modifier
Revision Level
MPC
7410
RX = CBGA
C: 1.2; PVR = 800C 1102 1
D: 1.3; PVR = 800C 1103 2
E: 1.4; PVR = 800C 1104 3
P: 2.0 V ± 50 mV
0° to 65°C
450
500
550
Notes: Document order numbers:
1. MPC7410PCPNS.
2. MPC7410PDPNS.
3. MPC7410PEPNS.
Table 19. Part Numbers Addressed by MPC7410 RISC Microprocessor HardwareSpecifications Addendum
for the MPC7410xxnnnNE Series
Mxx
7410
xx
nnn
N
E
Product
Code
Part
Identifier
Package
Processor
Frequency 1
Application
Modifier
Revision Level
MPC
7410
MC
RX = CBGA
400
450
500
HX = HCTE_CBGA
VS = HCTE_LGA
400
450
N: 1.5 V ± 50 mV
E: 1.4; PVR = 800C 1104
VU = HCTE_CBGA
(Lead Free C5 Solder
Spheres)
Note: Document order number: MPC7410ECS02AD
Table 20. Part Numbers Addressed by MPC7410TRXnnnNE Part Number Specification
MPC
7410
T
RX
nnn
N
E
Product
Code
Part
Identifier
Process
Descriptor
Package
Processor
Frequency 1
Application
Modifier
Revision Level
MPC
7410
T: –40° to 105°C RX = CBGA
400
450
N: 1.5 V ±50 mV
E: 1.4; PVR = 800C 1104
Note: Document order number: MPC7410TRXNEPNS.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
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Ordering Information
10.3 Part Marking
Parts are marked as the example shown in Figure 31.
MPC7410
HXnnnLE
MMMMMM
AWLYYWWA
7410
Notes:
HCTE_CBGA
MMMMMM is the 6-digit mask number.
AWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 31. Part Marking for HCTE_CBGA Device
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
55
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Rev. 6.1
11/2007
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