FUJITSU MB90330A

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13734-3Ea
16-bit Microcontroller
CMOS
F2MC-16LX MB90330A Series
MB90333A/F334A/MB90V330A
■ DESCRIPTION
The MB90330A series are 16-bit microcontrollers designed for applications, such as personal computer peripheral
devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but
also Mini-HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices
such as displays and audio devices, and control of mobile devices that support USB communications. While
inheriting the AT architecture of the F2MC family, the instruction set supports the C language and extended
addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial
collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in oscillation circuit and PLL clock frequency multiplication circuit
• Oscillation clock
• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)
• Clock for USB is 48 MHz
• Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable
• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock
24 MHz and at operating VCC = 3.3 V.
• The maximum memory space : 16 Mbytes
• 24-bit addressing
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://edevice.fujitsu.com/micom/en-support/
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2007.11
MB90330A Series
(Continued)
• Bank addressing
• Instruction system
• Data types : Bit, Byte, Word and Long word
• Addressing mode (23 types)
• Enhanced high-precision computing with 32-bit accumulator
• Enhanced Multiply/Divide instructions with sign and the RETI instruction
• Instruction system compatible with high-level language (C language) and multi-task
• Employing system stack pointer
• Instruction set symmetry and barrel shift instructions
• Program Patch Function (2 address pointer)
• 4-byte instruction queue
• Interrupt function
• Priority levels are programmable
• 32 interrupts function
• Data transfer function
• Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels
• µDMAC : Maximum 16 channels
• Low Power Consumption Mode
• Sleep mode (with the CPU operating clock stopped)
• Time-base timer mode (with the oscillator clock and time-base timer operating)
• Stop mode (with the oscillator clock stopped)
• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)
• Watch mode (with 32 kHz oscillator clock and watch timer operating)
• Package
• LQFP-120P (FPT-120P-M05 : 0.40 mm pin pitch)
• LQFP-120P (FPT-120P-M21 : 0.50 mm pin pitch)
• Process : CMOS technology
• Operation guaranteed temperature : − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)
2
MB90330A Series
■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)
• I/O port : Max 94 ports
• Time-base timer : 1 channel
• Watchdog timer : 1 channel
• Watch timer : 1 channel
• 16-bit reload timer : 3 channels
• Multi-functional timer
• 16-bit free run timer : 1 channel
• Output compare : 4 channels
An interrupt request can be output when the 16-bit free-run timer value matches the compare register value.
• Input capture : 4 channels
Upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the
input capture data register to the 16-bit free-run timer value to output an interrupt request.
• 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) the period and duty of the output pulse can be
set by the program.
• 16-bit PWC timer : 1 channel
Timer function and pulse width measurement function
• UART : 4 channels
• Full-duplex double buffer (8-bit length)
• Asynchronous transfer or clock-synchronous serial (Extended I/O serial) transfer can be set.
• Extended I/O serial interface : 1 channel
• DTP/External interrupt circuit (8 channels)
• Activate the extended intelligent I/O service by external interrupt input
• Interrupt output by external interrupt input
• Delay interrupt output module
• Output an interrupt request for task switching
• 8/10-bit A/D converter : 16 channels
• 8-bit resolution or 10-bit resolution can be set.
• USB : 1 channel
• USB function (correspond to USB Full Speed)
• Full Speed is supported/Endpoint are specifiable up to six.
• Dual port RAM (The FIFO mode is supported).
• Transfer type : Control, Interrupt, Bulk, or Isochronous transfer possible
• USB Mini-HOST function
• I2C* Interface : 3 channels
• Supports Intel SM bus standard and Phillips I2C bus standards
• Two-wire data transfer protocol specification
• Master and slave transmission/reception
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
3
MB90330A Series
■ PRODUCT LINEUP
Part number
MB90V330A
MB90F334A
MB90333A
For evaluation
Built-in Flash memory
Built-in MASK ROM
ROM capacity
No
384 Kbytes
256 Kbytes
RAM capacity
28 Kbytes
24 Kbytes
16 Kbytes
Type
Emulator-specific power supply *
Yes
⎯
CPU functions
Number of basic instructions
: 351 instructions
Minimum instruction execution time : 41.6 ns/at oscillation of 6 MHz
(When 4 times are used : Machine clock
of 24 MHz)
Addressing type
: 23 types
Program Patch Function
: For 2 address pointers
Maximum memory space
: 16 Mbytes
Ports
I/O Ports (CMOS) 94 ports
UART
Equipped with full-duplex double buffer
Clock synchronous or asynchronous operation selectable
It can also be used for I/O serial
Built-in special baud-rate generator
Built-in 4 channels
16-bit reload timer
16-bit reload timer operation
Built-in 3 channels
Multi-functional timer
16-bit free run timer × 1 channel
Output compare × 4 channels
Input capture × 4 channels
8/16-bit PPG timer (8-bit mode × 6 channels, 16-bit mode × 3 channels)
16-bit PWC timer × 1 channel
8/10-bit A/D converter
16 channels (input multiplex)
8-bit resolution or 10-bit resolution can be set.
Conversion time : 7.16 µs at minimum (24 MHz machine clock at maximum)
DTP/External interrupt
8 channels
Interrupt factor : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable
I2C
3 channels
Extended I/O serial interface
1 channel
USB
1 channel
USB function (correspond to USB Full Speed)
USB Mini-HOST function
External bus interface
For multi-bus/non-multi-bus
Withstand voltage of 5 V
16 ports (excluding UTEST and I/O for I2C)
Low Power Consumption Mode
Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/
Watch mode
Process
CMOS
Operating voltage
3.3 V ± 0.3 V (at maximum machine clock 24 MHz)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the
MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
4
MB90330A Series
■ PACKAGES AND PRODUCT MODELS
Package
MB90333A
MB90F334A
MB90V330A
FPT-120P-M05 (LQFP-0.40 mm)
×
FPT-120P-M21 (LQFP-0.50 mm)
×
PGA-299C-A01 (PGA)
×
×
: Yes × : No
Note : For detailed information on each package, refer to “■ PACKAGE DIMENSIONS”.
5
P92/SCK2
P93/SIN3
P94/SOT3
P95/SCK3
P96/ADTG/FRCK
AVCC
AVRH
AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
VSS
P80/AN8
P81/AN9
P82/AN10
P83/AN11
P84/AN12
P85/AN13
P86/AN14
P87/AN15
PA0/IN0
PA1/IN1
PA2/IN2
PA3/IN3
PA4/OUT0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/A23/PPG3
P26/A22/PPG2
P25/A21/PPG1
P24/A20/PPG0
P23/A19
P22/A18
P21/A17
P20/A16
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
X0
X1
VSS
VCC
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
P02/AD02/D02
P01/AD01/D01
P00/AD00/D00
P57/CLK
P56/RDY
MB90330A Series
■ PIN ASSIGNMENT
(TOP VIEW)
P30/A00/TIN1
P31/A01/TOT1
P32/A02/TIN2
P33/A03/TOT2
P34/A04
P35/A05
P36/A06
P37/A07
P40/A08/TIN0
P41/A09/TOT0
P42/A10/SIN0
P43/A11/SOT0
X0A
X1A
VCC
VSS
P44/A12/SCK0
P45/A13/SIN1
P46/A14/SOT1
P47/A15/SCK1
P60/INT0
P61/INT1
P62/INT2/SIN
P63/INT3/SOT
P64/INT4/SCK
P65/INT5/PWC
P66/INT6/SCL0
P67/INT7/SDA0
P90/SIN2
P91/SOT2
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(FPT-120P-M05 / FPT-120P-M21)
RST
MD0
MD1
MD2
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
HCON
VCC
HVP
HVM
VSS
VCC
DVP
DVM
VSS
UTEST
PB6/PPG5
PB5/PPG4
PB4
PB3/SDA2
PB2/SCL2
PB1/SDA1
PB0/SCL1
PA7/OUT3
PA6/OUT2
PA5/OUT1
MB90330A Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type*
108, 107
X0, X1
A
Terminals to connect the oscillator.
When connecting an external clock, leave the X1 pin side unconnected.
13, 14
X0A, X1A
A
32 kHz oscillation terminals.
90
RST
F
External reset input pin.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1)
by the pull-up resistor setting register (RDR0). (When the power output is
set, it is invalid.)
P00 to P07
93 to 100
H
AD00 to AD07
Function as an I/O pin for the low-order external address and data bus in
multiplex mode.
D00 to D07
Function as an output pin for the low-order external data bus in nonmultiplex mode.
P10 to P13
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
101 to 104
H
AD08 to AD11
Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
D08 to D11
Function as an output pin for the high-order external data bus in nonmultiplex mode.
P14 to P17
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
109 to 112
H
AD12 to D15
113 to 116
Function
Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
D12 to D15
Function as an output pin for the high-order external data bus in nonmultiplex mode.
P20 to P23
This is a general purpose I/O port. When the bits of external address output
control register (HACR) are set to “1” in external bus mode, these pins
function as general purpose I/O ports.
A16 to A19
A16 to A19
D
When the bits of external address output control register (HACR) are set to
“0” in multiplex mode, these pins function as address high output pins.
When the bits of external address output control register (HACR) are set to
“0” in non-multiplex mode, these pins function as address high output pins.
(Continued)
7
MB90330A Series
Pin no.
Pin name
I/O
Circuit
type*
This is a general purpose I/O port. When the bits of external address
output control register (HACR) are set to “1” in external bus mode, these
pins function as general purpose I/O ports.
P24 to P27
117 to 120
A20 to A23
D
PPG0 to PPG3
Function as ch.0 to ch.3 output pins for the 8-bit PPG timer.
P30
2
A00
General purpose input/output port.
D
Function as an event input pin for 16-bit reload timer ch.1.
P31
General purpose input/output port.
A01
D
A02
General purpose input/output port.
D
Function as an event input pin for 16-bit reload timer ch.2.
P33
General purpose input/output port.
A03
D
P34 to P37
A04 to A07
A08
D
G
12
General purpose input/output port.
G
Function as the external address pin in non-multi-bus mode.
SIN0
Function as a data input pin for UART ch.0.
P43
General purpose input/output port.
A11
G
SOT0
A12
SCK0
Function as the external address pin in non-multi-bus mode.
Function as a data output pin for UART ch.0.
P44
17
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.0.
P42
A10
Function as the external address pin in non-multi-bus mode.
General purpose input/output port.
G
TOT0
11
Function as the external address pin in non-multi-bus mode.
Function as an event input pin for 16-bit reload timer ch.0.
P41
A09
General purpose input/output port.
General purpose input/output port.
TIN0
10
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.2.
P40
9
Function as the external address pin in non-multi-bus mode.
TIN2
TOT2
5 to 8
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.1.
P32
4
Function as the external address pin in non-multi-bus mode.
TIN1
TOT1
3
When the bits of external address output control register (HACR) are set
to “0” in multiplex mode, these pins function as address high output pins.
When the bits of external address output control register (HACR) are set
to “0” in non-multiplex mode, these pins function as address high output
pins.
A20 to A23
1
Function
General purpose input/output port.
G
Function as the external address pin in non-multi-bus mode.
Function as a clock I/O pin for UART ch.0.
(Continued)
8
MB90330A Series
Pin no.
Pin name
I/O
Circuit
type*
P45
18
19
A13
General purpose input/output port.
G
Function as a data input pin for UART ch.1.
P46
General purpose input/output port.
A14
G
A15
General purpose input/output port.
G
SCK1
82
P50
ALE
P51
RD
WRL
L
L
WRH
L
HRQ
L
HAK
L
RDY
L
21, 22
CLK
P60, P61
INT0, INT1
Function as the data write strobe output pin on the lower side in external
bus mode. This pin functions as a general-purpose I/O port when the WRE
bit in the EPCR register is “0”.
Function as the data write strobe output pin on the higher side in bus width
16-bit external bus mode. This pin functions as a general-purpose I/O port
when the WRE bit in the EPCR register is “0”.
Function as the hold request input pin in external bus mode. This pin
functions as a general-purpose I/O port when the HDE bit in the EPCR
register is “0”.
Function as the hold acknowledge output pin in external bus mode. This pin
functions as a general-purpose I/O port when the HDE bit in the EPCR
register is “0”.
General purpose input/output port.
L
P57
92
Function as the read strobe output pin in external bus mode.
General purpose input/output port.
P56
91
General purpose input/output port.
General purpose input/output port.
P55
86
Function as the address latch enable signal pin in external bus mode.
General purpose input/output port.
P54
85
General purpose input/output port.
General purpose input/output port.
P53
84
Function as the external address pin in non-multi-bus mode.
Function as a clock I/O pin for UART ch.1.
P52
83
Function as the external address pin in non-multi-bus mode.
Function as a data output pin for UART ch.1.
P47
81
Function as the external address pin in non-multi-bus mode.
SIN1
SOT1
20
Function
Function as the external ready input pin in external bus mode. This pin
functions as a general-purpose I/O port when the RYE bit in the EPCR
register is “0”.
General purpose input/output port.
L
C
Function as the machine cycle clock output pin in external bus mode. This
pin functions as a general-purpose I/O port when the CKE bit in the EPCR
register is “0”.
General purpose input/output port. (With stand voltage of 5 V)
Function as external interrupt ch.0 and ch.1 input pins.
(Continued)
9
MB90330A Series
Pin no.
Pin name
I/O
Circuit
type*
P62
23
24
25
26
27
INT2
General purpose input/output ports. (Withstand voltage of 5 V)
C
SIN
Extended I/O serial interface data input pin.
General purpose input/output port. (Withstand voltage of 5 V)
INT3
C
Extended I/O serial interface data output pin.
P64
General purpose input/output port. (Withstand voltage of 5 V)
INT4
C
29
30
31
32
33
34
Extended I/O serial interface clock input/output pin.
P65
General purpose input/output port. (Withstand voltage of 5 V)
INT5
C
Function as an external interrupt ch.5 input pin.
PWC
Function as the PWC input pin.
P66
General purpose input/output port. (Withstand voltage of 5 V)
INT6
C
INT7
P70 to P77
AN0 to AN7
P80 to P87
AN8 to AN15
P90
SIN2
P91
SOT2
P92
SCK2
P93
SIN3
P94
SOT3
P95
SCK3
ADTG
FRCK
Function as an external interrupt ch.6 input pin.
Function as the ch.0 clock I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
C
I
I
D
D
D
D
D
D
P96
35
Function as an external interrupt ch.4 input pin.
SCK
SDA0
48 to 55
Function as an external interrupt ch.3 input pin.
SOT
P67
39 to 46
Function as an external interrupt ch.2 input pin.
P63
SCL0
28
Function
Function as an external interrupt ch.7 input pin.
Function as the ch.0 data I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port.
Function as input pins for analog ch.0 to ch.7.
General purpose input/output port.
Function as input pins for analog ch.8 to ch.15.
General purpose input/output port.
Function as a data input pin for UART ch.2.
General purpose input/output port.
Function as a data output pin for UART ch.2.
General purpose input/output port.
Function as a clock I/O pin for UART ch.2.
General purpose input/output port.
Function as a data input pin for UART ch.3.
General purpose input/output port.
Function as a data output pin for UART ch.3.
General purpose input/output port.
Function as a clock I/O pin for UART ch.3.
General purpose input/output port. (Withstand voltage of 5 V)
C
Function as the external trigger input pin when the A/D converter is being used.
Function as the external clock input pin when the free-run timer is being used.
(Continued)
10
MB90330A Series
(Continued)
Pin no.
56 to 59
60 to 63
Pin name
PA0 to PA3
IN0 to IN3
PA4 to PA7
OUT0 to OUT3
I/O
Circuit
type*
C
C
PB0
64
SCL1
SDA1
SCL2
C
68
69, 70
SDA2
PB4
PB5, PB6
PPG4, PPG5
General purpose input/output port. (Withstand voltage of 5 V)
Function as the output compare ch.0 to ch.3 event output pins.
Function as the ch.1 clock I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
Function as the ch.1 data I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
C
PB3
67
Function as the input capture ch.0 to ch.3 trigger inputs.
General purpose input/output port. (Withstand voltage of 5 V)
PB2
66
General purpose input/output port. (Withstand voltage of 5 V)
General purpose input/output port. (Withstand voltage of 5 V)
C
PB1
65
Function
Function as the ch.2 clock I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
C
C
D
Function as the ch.2 data I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
General purpose input/output port.
Function as ch.4 and ch.5 output pins for the 8-bit PPG timer.
71
UTEST
C
USB test pin. Connect this to a pull-down resistor during normal usage.
73
DVM
K
USB function D− pin.
74
DVP
K
USB function D+ pin.
77
HVM
K
USB Mini-HOST D− pin.
78
HVP
K
USB Mini-HOST D+ pin.
80
HCON
E
External pull-up resistor connect pin.
36
AVcc
⎯
A/D converter power supply pin.
37
AVRH
J
A/D converter external reference power supply pin.
38
AVss
⎯
A/D converter power supply pin.
87 to 89
MD2 to MD0
B
Operation mode select input pin.
15
Vcc
⎯
Power supply pin.
75
Vcc
⎯
Power supply pin.
79
Vcc
⎯
Power supply pin.
105
Vcc
⎯
Power supply pin.
16
Vss
⎯
Power supply pin (GND).
47
Vss
⎯
Power supply pin (GND).
72
Vss
⎯
Power supply pin (GND).
76
Vss
⎯
Power supply pin (GND).
106
Vss
⎯
Power supply pin (GND).
* : For circuit information, refer to “■ I/O CIRCUIT TYPE”.
11
MB90330A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
X1A
X0
X0A
Standby control signal
B
• High-rate oscillation feedback resistor,
approx.1 MΩ
• Low-rate oscillation feedback resistor,
approx.10 MΩ
• With standby control
CMOS hysteresis input
CMOS hysteresis
input
C
• CMOS hysteresis input
• N-ch open drain output
N-ch
Nout
CMOS hysteresis input
Standby control signal
D
P-ch
Pout
N-ch
Nout
CMOS hysteresis input
Standby control signal
E
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
Notes : • Share one output buffer because
both output of I/O port and
internal resource are used.
• Share one input buffer because
both input of I/O port and internal
resource are used.
CMOS output
P-ch
Pout
N-ch
Nout
F
CMOS hysteresis input with pull-up resistor
R
CMOS hysteresis
input
(Continued)
12
MB90330A Series
Type
Circuit
Remarks
G
P-ch
Pout
N-ch
Nout
Open drain control
signal
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
With open drain control signal
CMOS hysteresis
input
Standby control
signal
H
• CMOS output
• CMOS input
(With input interception function at
standby)
• With input pull-up register control
CTL
R
P-ch
Pout
N-ch
Nout
CMOS input
Standby control signal
I
P-ch
Pout
N-ch
Nout
CMOS hysteresis
input
Standby control signal
A/D converter analog
input
J
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• Analog input
(The A/D converter analog input is enabled
when the corresponding bit in the analog
input enable register (ADER) is 1.)
Notes: • Because the output of the I/O port and
the output of internal resources are
used combinedly, one output buffer
is shared.
• Because the input of the I/O port
and the input of internal resources
are used combinedly, one input
buffer is shared.
A/D converter (AVRH) voltage input pin
P-ch
P-ch
N-ch
N-ch
AVRH input
A/D converter
analog input
enable signal
(Continued)
13
MB90330A Series
(Continued)
Type
Circuit
Remarks
K
USB I/O pin
D + input
D - input
D+
Differential input
D−
Full D + output
Full D - output
Low D + output
Low D - output
Direction
Speed
L
P-ch
Pout
N-ch
Nout
CMOS input
Standby control signal
14
• CMOS output
• CMOS input
• With standby control
MB90330A Series
■ HANDLING DEVICES
1. Preventing latch-up and turning on power supply
Latch-up may occur on CMOS IC under the following conditions:
• If a voltage higher than VCC or lower than VSS is applied to input and output pins.
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• If the AVCC power supply is turned on before the VCC voltage.
Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the
digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as
VCC and the digital power supply).
If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device.
Use meticulous care not to let any voltage exceed the maximum rating.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it to open.
3. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC,
and AVSS = VSS.
4. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub clock or stop mode. When suing an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
• Using external clock
X0
OPEN
X1
5. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the
current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC pin and VSS pin
near this device.
15
MB90330A Series
6. About Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass
capacitor to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded
by ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
7. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu Microelectronics will not guarantee results of operations if such failure
occurs.
8. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage
operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations
(peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage
and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching.
9. When the dual-supply is used as a single-supply device
If you are using only a single-system of the MB90330A series that come in the dual-system product, use it with
X0A = VSS : X1A = OPEN.
10. Writing to flash memory
For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.
For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
16
MB90330A Series
■ BLOCK DIAGRAM
X0, X1
X0A,X1A
RST
MD0 to MD2
Clock control
circuit
F2MC-16LX
CPU
Interrupt
controller
8/16-bit
PPG timer
ch.0 to ch.5*
PPG0 to PPG5
Input capture
ch.0 to ch.3
IN0 to IN3
16-bit free-run
timer
FRCK
RAM
SIN0 to SIN3
SOT0 to SOT3
SCK0 to SCK3
UART/SIO
ch.0 to ch.3
SCL0 to SCL2
SDA0 to SDA2
I2C
ch.0 to ch.2
AVCC
AVRH
AVSS
AN0 to AN15
ADTG
8/10-bit A/D
converter
TOT0 to TOT2
TIN0 to TIN2
16-bit reload
timer
ch.0 to ch.2
DVP
DVM
HVP
HVM
HCON
UTEST
USB
(Function)
(Mini-HOST)
Internal data bus
ROM
Output compare
ch.0 to ch.3
OUT0 to OUT3
16-bit PWC
PWC
SIO
SIN
SOT
SCK
µDMAC
External
interrupt
INT0 to INT7
I/O port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
P00
P10
P20
P30
P40
P50
P60
P70
P80
P90
PA0 PB0
P07
P17
P27
P37
P47
P57
P67
P77
P87
P96
PA7 PB6
* : Channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode.
Note : I/O ports share pins with peripheral function (resources) .
For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.
Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
17
MB90330A Series
■ MEMORY MAP
Single chip mode (with ROM mirror function)
MB90V330A
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
MB90F334A
FFFFFFH
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
ROM (FD bank)
FE0000H
FDFFFFH
ROM (FC bank)
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
F80000H
00FFFFH
008000H
007FFFH
00FFFFH
ROM
(image of FF bank)
008000H
007FFFH
Peripheral area
007900H
ROM (FF bank)
MB90333A
FFFFFFH
ROM (FE bank)
FF0000H
FEFFFFH
ROM (FD bank)
FE0000H
FDFFFFH
FD0000H
FCFFFFH
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM
(image of FF bank)
Peripheral area
007900H
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
008000H
007FFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
ROM
(image of FF bank)
Peripheral area
007900H
007100H
006100H
004100H
RAM area
(28 Kbytes)
000100H
RAM area
(24 Kbytes)
Register
0000FBH
000100H
0000FBH
Peripheral area
000000H
Register
RAM area
(16 Kbytes)
000100H
0000FBH
Peripheral area
000000H
Peripheral area
000000H
Memory map of MB90330A series (1/3)
18
Register
MB90330A Series
Internal ROM external bus mode (with ROM mirror function)
MB90V330A
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
F80000H
MB90F334A
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
External area
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
007900H
MB90333A
FFFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
ROM (FE bank)
FE0000H
FDFFFFH
ROM (FD bank)
*1
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
*1
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
External area
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
007900H
External area
ROM (FE bank)
ROM (FD bank)
*2
ROM (FB bank)
*2
External area
External area
External area
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
007900H
External area
007100H
ROM (FF bank)
External area
006100H
004100H
RAM area
(28 Kbytes)
000100H
Register
0000FBH
RAM area
(24 Kbytes)
000100H
0000FBH
000100H
000000H
Register
0000FBH
Peripheral area
Peripheral area
000000H
Register
RAM area
(16 Kbytes)
Peripheral area
000000H
*1 : In the area of F80000H to F8FFFFH and FC0000H to FCFFFFH at MB90F334A, a value of “1” is read at
read operating.
*2 : In the area of FA0000H to FAFFFFH and FC0000H to FCFFFFH at MB90333A, a value of “1” is read at
read operating.
Memory map of MB90330A series (2/3)
19
MB90330A Series
External ROM external bus mode
MB90V330A
MB90F334A
FFFFFFH
FFFFFFH
External area
008000H
007FFFH
MB90333A
FFFFFFH
External area
008000H
007FFFH
Peripheral area
007900H
Peripheral area
007900H
External area
008000H
007FFFH
External area
External area
Peripheral area
007900H
External area
007100H
006100H
004100H
RAM area
(28 Kbytes)
000100H
RAM area
(24 Kbytes)
Register
0000FBH
000100H
0000FBH
Peripheral area
000000H
Register
RAM area
(16 Kbytes)
000100H
0000FBH
Peripheral area
000000H
Register
Peripheral area
000000H
Memory map of MB90330A series (3/3)
Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses
(“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of
bank 00.
• The ROM mirror function is effective for using the C compiler small model.
• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in
bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be
reproduced in bank 00.
• When the C compiler small model is used, the data table mirror image can be shown at “008000H to
00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM
area can be referred without declaring the far addressing with the pointer.
20
MB90330A Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated register
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8-bit
16-bit
32-bit
• General purpose register
MSB
LSB
16-bit
000180H + RP × 10H
RW0
RL0
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
• Processor status
Bit 15
PS
13 12
ILM
8 7
RP
0
CCR
21
MB90330A Series
■ I/O MAP
Address
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
00000DH
00000EH
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
000019H
00001AH
Register
abbreviation
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
Port 7 Data Register
Port 8 Data Register
Port 9 Data Register
Port A Data Register
Resource name
Initial Value
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
- XXXXXXXB
XXXXXXXXB
R/W
R/W
Port B
Port B
- XXXXXXXB
- 0 0 0 0 0 0 0B
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 4
(open drain control)
Port 0 (PULL-UP)
Port 1 (PULL-UP)
Port 7, 8, A/D
Port 7, 8, A/D
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Prohibited
PDRB
DDRB
Port B Data Register
Port B Direction Register
Prohibited
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
Port 7 Direction Register
Port 8 Direction Register
Port 9 Direction Register
Port A Direction Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00001BH
ODR4
Port 4 Output Pin Register
R/W
00001CH
00001DH
00001EH
00001FH
000020H
000021H
RDR0
RDR1
ADER0
ADER1
SMR0
SCR0
SIDR0
SODR0
SSR0
UTRLR0
UTCR0
Port 0 Pull-up Resistance Register
Port 1 Pull-up Resistance Register
Analog Input Enable Register 0
Analog Input Enable Register 1
Serial Mode Register 0
Serial Control Register 0
Serial Input Data Register 0
Serial Output Data Register 0
Serial Status Register 0
UART Prescaler Reload Register 0
UART Prescaler Control Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
000022H
000023H
000024H
000025H
UART0
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
XXXXXXXXB
0 0 0 0 1 0 0 0B
Communication 0 0 0 0 0 0 0 0B
Prescaler (UART0) 0 0 0 0 - 0 0 0B
(Continued)
22
MB90330A Series
Address
Register
abbreviation
000026H
SMR1
Serial Mode Register 1
R/W
0 0 1 0 0 0 0 0B
000027H
SCR1
Serial Control Register 1
R/W
0 0 0 0 0 1 0 0B
000028H
Read/
Write
Register
SIDR1
Serial Input Data Register 1
R
SODR1
Serial Output Data Register 1
W
000029H
SSR1
00002AH
Resource name
UART1
Initial Value
XXXXXXXXB
Serial Status Register 1
R/W
0 0 0 0 1 0 0 0B
UTRLR1
UART Prescaler Reload Register 1
R/W
00002BH
UTCR1
UART Prescaler Control Register 1
R/W
Communication 0 0 0 0 0 0 0 0B
Prescaler (UART1) 0 0 0 0 - 0 0 0B
00002CH
SMR2
Serial Mode Register 2
R/W
0 0 1 0 0 0 0 0B
00002DH
SCR2
Serial Control Register 2
R/W
0 0 0 0 0 1 0 0B
SIDR2
Serial Input Data Register 2
R
SODR2
Serial Output Data Register 2
W
00002EH
00002FH
SSR2
000030H
UART2
XXXXXXXXB
Serial Status Register 2
R/W
0 0 0 0 1 0 0 0B
UTRLR2
UART Prescaler Reload Register 2
R/W
000031H
UTCR2
UART Prescaler Control Register 2
R/W
Communication 0 0 0 0 0 0 0 0B
Prescaler (UART2) 0 0 0 0 - 0 0 0B
000032H
SMR3
Serial Mode Register 3
R/W
0 0 1 0 0 0 0 0B
000033H
SCR3
Serial Control Register 3
R/W
0 0 0 0 0 1 0 0B
SIDR3
Serial Input Data Register 3
R
SODR3
Serial Output Data Register 3
W
000034H
UART3
XXXXXXXXB
000035H
SSR3
Serial Status Register 3
R/W
0 0 0 0 1 0 0 0B
000036H
UTRLR3
UART Prescaler Reload Register 3
R/W
0 0 0 0 0 0 0 0B
000037H
UTCR3
UART Prescaler Control Register 3
R/W
Communication
Prescaler (UART3) 0 0 0 0 - 0 0 0B
0 0 0 0 0 0 0 0B
000038H
to
00003BH
Prohibited
00003CH
ENIR
DTP/Interrupt Enable Register
R/W
00003DH
EIRR
DTP/Interrupt Source Register
R/W
Request Level Setting Register Lower
R/W
Request Level Setting Register Upper
R/W
00003EH
00003FH
ELVR
DTP/External
Interrupt
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
000040H
ADCS0
A/D Control Status Register Lower
R/W
0 0 - - - - - 0B
000041H
ADCS1
A/D Control Status Register Upper
R/W
0 0 0 0 0 0 0 0B
000042H
ADCR0
A/D Data Register Lower
R/W
000043H
ADCR1
A/D Data Register Upper
R/W
000045H
ADMR
A/D Conversion Channel Selection
Register
R/W
8/10-bit
A/D Converter
0 0 0 0 0 0 0 0B
000046H
PPGC0
PPG0 Operation Mode Control
Register
R/W
PPG ch.0
0X0 0 0XX1B
000047H
PPGC1
PPG1 Operation Mode Control
Register
R/W
PPG ch.1
0X0 0 0 0 0 1B
000048H
PPGC2
PPG2 Operation Mode Control
Register
R/W
PPG ch.2
0X0 0 0XX1B
000044H
8/10-bit
A/D Converter
XXXXXXXXB
0 0 1 0 1 XXXB
Prohibited
(Continued)
23
MB90330A Series
Address
Register
abbreviation
Register
Read/
Write
Resource name
Initial Value
000049H
PPGC3
PPG3 Operation Mode Control Register
R/W
PPG ch.3
0X0 0 0 0 0 1B
00004AH
PPGC4
PPG4 Operation Mode Control Register
R/W
PPG ch.4
0X0 0 0XX1B
00004BH
PPGC5
PPG5 Operation Mode Control Register
R/W
PPG ch.5
0X0 0 0 0 0 1B
00004CH
PPG01
PPG0 and PPG1 Output Control
Register
R/W
PPG ch.0/ch.1
0 0 0 0 0 0XXB
R/W
PPG ch.2/ch.3
0 0 0 0 0 0 XXB
R/W
PPG ch.4/ch.5
0 0 0 0 0 0 XXB
Input Capture
ch.0/ch.1
0 0 0 0 0 0 0 0B
00004DH
00004EH
Prohibited
PPG23
PPG2 and PPG3 Output Control
Register
00004FH
000050H
Prohibited
PPG45
PPG4 and PPG5 Output Control
Register
000051H
Prohibited
000052H
ICS01
Input Capture Control Status Register 01
R/W
000053H
ICS23
Input Capture Control Status Register 23
R/W
000054H
OCS0
Output Compare Control Register ch.0
Lower
R/W
000055H
OCS1
Output Compare Control Register ch.1
Upper
R/W
000056H
OCS2
Output Compare Control Register ch.2
Lower
R/W
000057H
OCS3
Output Compare Control Register ch.3
Upper
R/W
SMCS
Serial Mode Control Status Register
R/W
Serial Data Register
R/W
Communication Prescaler Control
Register
R/W
PWC Control Status Register
R/W
PWC Data Buffer Register
R/W
000058H
000059H
00005AH
SDR
00005BH
SDCR
00005CH
00005DH
00005EH
00005FH
000060H
PWCSR
PWCR
DIVR
000061H
000062H
000063H
000064H
000065H
PWC Dividing Ratio Control Register
Input
0 0 0 0 0 0 0 0B
Capture ch.2/ch.3
Output
Compare
ch.0/ch.1
0 0 0 0 - - 0 0B
Output
Compare
ch.2/ch.3
0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
- - - 0 0 0 0 0B
XXXX0 0 0 0B
Extended Serial
I/O
0 0 0 0 0 0 1 0B
Communication
Prescaler
0XXX0 0 0 0B
XXXXXXXXB
0 0 0 0 0 0 0 0B
16-bit
PWC Timer
R/W
0 0 0 0 0 0 0 XB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - - - 0 0B
Prohibited
TMCSR0
TMR0
TMRLR0
TMR0
TMRLR0
Timer Control Status Register 0
0 0 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
16-bit
Reload Timer
ch.0
16-bit Timer Register 0 Lower
R
16-bit Reload Register 0 Lower
W
XXXXXXXXB
16-bit Timer Register 0 Upper
R
XXXXXXXXB
16-bit Reload Register 0 Upper
W
XXXXXXXXB
XXXXXXXXB
(Continued)
24
MB90330A Series
Address
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
Register
abbreviation
TMCSR1
TMR1
Read/
Write
Register
Timer Control Status Register 1
Initial Value
0 0 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
16-bit Timer Register 1 Lower
R
16-bit Reload Register 1 Lower
W
16-bit Timer Register 1 Upper
R
XXXXXXXXB
TMRLR1
16-bit Reload Register 1 Upper
W
XXXXXXXXB
TMCSR2
Timer Control Status Register 2
R/W
TMRLR1
TMR1
TMR2
TMRLR2
TMR2
TMRLR2
16-bit Reload
Timer ch.1
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
XXXX 0 0 0 0B
16-bit Timer Register 2 Lower
R
16-bit Reload Register 2 Lower
W
16-bit Timer Register 2 Upper
R
XXXXXXXXB
16-bit Reload Register 2 Upper
W
XXXXXXXXB
00006EH
16-bit Reload
Timer ch.2
XXXXXXXXB
XXXXXXXXB
Prohibited
00006FH
ROMM
ROM Mirror Function Selection
Register
W
000070H
IBSR0
I2C Bus Status Register 0
R
000071H
Resource name
IBCR0
2
I C Bus Control Register 0
ROM Mirror
Function
Selection Module
0 0 0 0 0 0 0 0B
R/W
2
- - - - - - 1 1B
0 0 0 0 0 0 0 0B
I2C Bus Interface
ch.0
000072H
ICCR0
I C Bus Clock Control Register 0
R/W
000073H
IADR0
I2C Bus Address Register 0
R/W
XXXXXXXXB
000074H
IDAR0
I2C Bus Data Register 0
R/W
XXXXXXXXB
2
R
0 0 0 0 0 0 0 0B
2
R/W
000075H
000076H
000077H
000078H
000079H
00007AH
Prohibited
IBSR1
IBCR1
ICCR1
IADR1
IDAR1
I C Bus Status Register 1
I C Bus Control Register 1
00007DH
00007EH
00007FH
000080H
000081H
to
000085H
0 0 0 0 0 0 0 0B
I2C Bus Interface
ch.1
2
R/W
2
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R
0 0 0 0 0 0 0 0B
I C Bus Clock Control Register 1
I C Bus Address Register 1
2
I C Bus Data Register 1
00007BH
00007CH
XX 0 XXXXXB
XX 0 XXXXXB
Prohibited
IBSR2
IBCR2
ICCR2
IADR2
IDAR2
I2C Bus Status Register 2
2
I C Bus Control Register 2
R/W
0 0 0 0 0 0 0 0B
I2C Bus Interface
ch.2
2
R/W
2
R/W
XXXXXXXXB
2
R/W
XXXXXXXXB
I C Bus Clock Control Register 2
I C Bus Address Register 2
I C Bus Data Register 2
XX 0 XXXXXB
Prohibited
(Continued)
25
MB90330A Series
Address
000086H
000087H
000088H
000089H
00008AH
00008BH
Register
abbreviation
TCDT
TCCS
CPCLR
Read/
Write
Register
Resource name
Initial Value
Timer Data Register Lower
R/W
0 0 0 0 0 0 0 0B
Timer Data Register Upper
R/W
0 0 0 0 0 0 0 0B
Timer Control Status Register Lower
R/W
Timer Control Status Register Upper
R/W
Compare Clear Register Lower
R/W
XXXXXXXXB
Compare Clear Register Upper
R/W
XXXXXXXXB
0 0 0 0 0 0 0 0B
00008CH
to
00009AH
16-bit Free-Run
Timer
0 0 0 0 0 0 0 0B
0 - - 0 0 0 0 0B
Prohibited
00009BH
DCSR
DMA Descriptor Channel
Specification Register
R/W
00009CH
DSRL
DMA Status Register Lower
R/W
00009DH
DSRH
DMA Status Register Upper
R/W
00009EH
PACSR
Program Address Detection Control
Status Register
R/W
Address Match
Detection
0 0 0 0 0 0 0 0B
00009FH
DIRR
Delay Interruption Factor Generation/
Release Register
R/W
Delay Interrupt
- - - - - - - 0B
0000A0H
LPMCR
Low Power Consumption Mode
Control Register
R/W
Low Power
Consumption
Control Circuit
0 0 0 1 1 0 0 0B
0000A1H
CKSCR
Clock Selection Register
R/W
Clock
1 1 1 1 1 1 0 0B
R/W
µDMAC
0 0 0 0 0 0 0 0B
0000A2H
µDMAC
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Prohibited
0000A3H
0000A4H
DSSR
DMA Stop Status Register
0000A5H
ARSR
Automatic Ready Function Selection
Register
W
0000A6H
HACR
External Address Output Control
Register
W
0000A7H
EPCR
Bus Control Signal Selection Register
W
0000A8H
WDTC
Watchdog Timer Control Register
R/W
Watchdog Timer
X - XXX 1 1 1B
0000A9H
TBTC
Time-base Timer Control Register
R/W
Time-base Timer
1 - - 0 0 1 0 0B
0000AAH
WTC
Watch Timer Control Register
R/W
Watch Timer
1 0 0 0 1 0 0 0B
0000ABH
External Pin
∗∗∗∗∗∗∗∗B
1 0 0 0 ∗ 1 0 -B
Prohibited
0000ACH
DERL
DMA Enable Register Lower
R/W
0000ADH
DERH
DMA Enable Register Upper
R/W
0000AEH
FMCS
Flash Memory Control Status
Register
R/W
0000AFH
0 0 1 1- - 0 0B
µDMAC
Flash Memory
I/F
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 X 0 0 0 0B
Prohibited
(Continued)
26
MB90330A Series
Address
Register
abbreviation
0000B0H
ICR00
Interrupt Control Register 00
R/W
0 0 0 0 0 1 1 1B
0000B1H
ICR01
Interrupt Control Register 01
R/W
0 0 0 0 0 1 1 1B
0000B2H
ICR02
Interrupt Control Register 02
R/W
0 0 0 0 0 1 1 1B
0000B3H
ICR03
Interrupt Control Register 03
R/W
0 0 0 0 0 1 1 1B
0000B4H
ICR04
Interrupt Control Register 04
R/W
0 0 0 0 0 1 1 1B
0000B5H
ICR05
Interrupt Control Register 05
R/W
0 0 0 0 0 1 1 1B
0000B6H
ICR06
Interrupt Control Register 06
R/W
0 0 0 0 0 1 1 1B
0000B7H
ICR07
Interrupt Control Register 07
R/W
0000B8H
ICR08
Interrupt Control Register 08
R/W
0000B9H
ICR09
Interrupt Control Register 09
R/W
0 0 0 0 0 1 1 1B
0000BAH
ICR10
Interrupt Control Register 10
R/W
0 0 0 0 0 1 1 1B
0000BBH
ICR11
Interrupt Control Register 11
R/W
0 0 0 0 0 1 1 1B
0000BCH
ICR12
Interrupt Control Register 12
R/W
0 0 0 0 0 1 1 1B
0000BDH
ICR13
Interrupt Control Register 13
R/W
0 0 0 0 0 1 1 1B
0000BEH
ICR14
Interrupt Control Register 14
R/W
0 0 0 0 0 1 1 1B
0000BFH
ICR15
Interrupt Control Register 15
R/W
0 0 0 0 0 1 1 1B
0000C0H
HCNT0
Host Control Register 0
R/W
0 0 0 0 0 0 0 0B
0000C1H
HCNT1
Host Control Register 1
R/W
0 0 0 0 0 0 0 1B
0000C2H
HIRQ
Host Interruption Register
R/W
0 0 0 0 0 0 0 0B
0000C3H
HERR
Host Error Status Register
R/W
0 0 0 0 0 0 1 1B
0000C4H
HSTATE
Host State Status Register
R/W
XX 0 1 0 0 1 0B
0000C5H
HFCOMP
SOF Interrupt FRAME Compare Register
R/W
0 0 0 0 0 0 0 0B
HRTIMER
Retry Timer Setting Register
Read/
Write
Register
0000C6H
0000C7H
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
HADR
Host Address Register
HEOF
EOF Setting Register
R/W
HFRAME
FRAME Setting Register
HTOKEN
Host Token End Point Register
0000CFH
0000D0H
0000D1H
Interrupt
Controller
R/W
0000C8H
0000C9H
Resource name
Initial Value
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 0 0 0B
USB Mini-HOST
0 0 0 0 0 0 0 0B
R/W
XXXXXX 0 0B
R/W
X 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
XX 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
XXXXX 0 0 0B
R/W
0 0 0 0 0 0 0 0B
Prohibited
UDCC
UDC Control Register
R/W
R/W
USB Function
1 0 1 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Continued)
27
MB90330A Series
Address
0000D2H
Register
abbreviation
Register
EP0C
EP0 Control Register
EP1C
EP1 Control Register
EP2C
EP2 Control Register
EP3C
EP3 Control Register
EP4C
EP4 Control Register
EP5C
EP5 Control Register
TMSP
Time Stamp Register
0000E0H
UDCS
UDC Status Register
0000E1H
UDCIE
UDC Interrupt Enable Register
EP0IS
EP0I Status Register
EP0OS
EP0O Status Register
0000D3H
0000D4H
0000D5H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
0000DBH
0000DCH
0000DDH
0000DEH
0000DFH
0000E2H
0000E3H
0000E4H
0000E5H
0000E6H
0000E7H
0000E8H
0000E9H
0000EAH
0000EBH
0000ECH
0000EDH
0000EEH
0000EFH
0000F0H
0000F1H
0000F2H
0000F3H
0000F4H
0000F5H
0000F6H
0000F7H
EP1S
EP1 Status Register
EP2S
EP2 Status Register
EP3S
EP3 Status Register
EP4S
EP4 Status Register
EP5S
EP5 Status Register
EP0DT
EP0 Data Register
EP1DT
EP1 Data Register
EP2DT
EP2 Data Register
EP3DT
EP3 Data Register
Read/
Write
Resource name
Initial Value
R/W
0 1 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 1B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R
0 0 0 0 0 0 0 0B
R
XXXXX0 0 0B
R/W
XX0 0 0 0 0 0B
R/W, R
0 0 0 0 0 0 0 0B
R/W
XXXXXXXXB
R/W
1 0 XXX 1 XXB
R/W, R
R/W
USB Function
0 XXXXXXXB
1 0 0 XX 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 XB
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
(Continued)
28
MB90330A Series
Address
0000F8H
0000F9H
0000FAH
0000FBH
Register
abbreviation
EP4DT
EP5DT
Read/
Write
Register
Resource name
R/W
EP4 Data Register
R/W
R/W
EP5 Data Register
Initial Value
XXXXXXXXB
USB Function
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
Program Address Detection Register
ch.0 Lower
R/W
XXXXXXXXB
Program Address Detection Register
ch.0 Middle
R/W
XXXXXXXXB
001FF2H
Program Address Detection Register
ch.0 Upper
R/W
001FF3H
Program Address Detection Register
ch.1 Lower
R/W
Program Address Detection Register
ch.1 Middle
R/W
XXXXXXXXB
Program Address Detection Register
ch.1 Upper
R/W
XXXXXXXXB
0000FCH
to
0000FFH
Prohibited
000100H
to
#H
RAM Area
001FF0H
001FF1H
001FF4H
PADR0
PADR1
001FF5H
#H
to
0078FFH
XXXXXXXXB
XXXXXXXXB
Unused Area
007900H
PRLL0
007901H
007902H
PPG Reload Register Lower ch.0
R/W
PRLH0
PPG Reload Register Upper ch.0
R/W
PRLL1
PPG Reload Register Lower ch.1
R/W
007903H
PRLH1
PPG Reload Register Upper ch.1
R/W
007904H
PRLL2
PPG Reload Register Lower ch.2
R/W
007905H
PRLH2
PPG Reload Register Upper ch.2
R/W
007906H
PRLL3
PPG Reload Register Lower ch.3
R/W
007907H
PRLH3
PPG Reload Register Upper ch.3
R/W
007908H
PRLL4
PPG Reload Register Lower ch.4
R/W
007909H
PRLH4
PPG Reload Register Upper ch.4
R/W
00790AH
PRLL5
PPG Reload Register Lower ch.5
R/W
00790BH
PRLH5
PPG Reload Register Upper ch.5
R/W
00790CH
to
00790FH
Address Match
Detection
PPG ch.0
PPG ch.1
PPG ch.2
PPG ch.3
PPG ch.4
PPG ch.5
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Prohibited
(Continued)
29
MB90330A Series
(Continued)
Address
007910H
007911H
007912H
007913H
007914H
007915H
007916H
007917H
007918H
007919H
00791AH
00791BH
00791CH
00791DH
00791EH
00791FH
Register
abbreviation
IPCP0
IPCP1
IPCP2
IPCP3
OCCP0
OCCP1
OCCP2
OCCP3
Register
Read/
Write
Input Capture Data Register Lower ch.0
R
Input Capture Data Register Upper ch.0
R
Input Capture Data Register Lower ch.1
R
Input Capture Data Register Upper ch.1
R
XXXXXXXXB
Input Capture Data Register Lower ch.2
R
XXXXXXXXB
Input Capture Data Register Upper ch.2
R
Input Capture Data Register Lower ch.3
R
Input Capture Data Register Upper ch.3
Resource name
XXXXXXXXB
Input Capture
ch.0/ch.1
Input Capture
ch.2/ch.3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R
XXXXXXXXB
Output Compare Register Lower ch.0
R/W
XXXXXXXXB
Output Compare Register Upper ch.0
R/W
Output Compare Register Lower ch.1
R/W
Output Compare
ch.0/ch.1
XXXXXXXXB
XXXXXXXXB
Output Compare Register Upper ch.1
R/W
XXXXXXXXB
Output Compare Register Lower ch.2
R/W
XXXXXXXXB
Output Compare Register Upper ch.2
R/W
Output Compare Register Lower ch.3
R/W
Output Compare
ch.2/ch.3
XXXXXXXXB
XXXXXXXXB
Output Compare Register Upper ch.3
R/W
XXXXXXXXB
007920H
DBAPL
DMA Buffer Address Pointer Lower 8-bit
R/W
XXXXXXXXB
007921H
DBAPM
DMA Buffer Address Pointer Middle 8-bit
R/W
XXXXXXXXB
007922H
DBAPH
DMA Buffer Address Pointer Upper 8-bit
R/W
XXXXXXXXB
007923H
DMACS
DMA Control Register
R/W
XXXXXXXXB
R/W
007924H
DIOAL
DMA I/O Register Address Pointer
Lower 8-bit
007925H
DIOAH
DMA I/O Register Address Pointer
Upper 8-bit
R/W
XXXXXXXXB
007926H
DDCTL
DMA Data Counter Lower 8-bit
R/W
XXXXXXXXB
007927H
DDCTH
DMA Data Counter Upper 8-bit
R/W
XXXXXXXXB
007928H
to
007FFFH
µDMAC
Prohibited
• Explanation on read/write
R/W : Readable / Writable
R
: Read only
W : Write only
• Explanation on initial values
0
: Initial value is “0”.
1
: Initial value is “1”.
X
: Initial value is undefined.
: Initial value is undefined (None) .
∗
: Initial value of this bit is “1” or “0”.
Note : No I/O instruction can be used for registers located between 007900H and 007FFFH.
30
Initial Value
XXXXXXXXB
MB90330A Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
µDMAC
support
Interrupt control
register
Priority
Address ICR Address
Interrupt vector
Number*1
Reset
×
×
#08
08H FFFFDCH
⎯
⎯
INT 9 instruction
×
×
#09
09H
FFFFD8H
⎯
⎯
Exceptional treatment
×
×
#10
0AH
FFFFD4H
⎯
⎯
USB Function1
×
0, 1
#11
0BH
FFFFD0H
USB Function2
×
#12
0CH FFFFCCH
USB Function3
×
×
#13
0DH FFFFC8H
USB Function4
×
×
#14
0EH
FFFFC4H
USB Mini-HOST1
×
×
#15
0FH
FFFFC0H
USB Mini-HOST2
×
×
#16
10H
FFFFBCH
I2C ch.0
×
×
#17
11H
FFFFB8H
×
#18
12H
FFFFB4H
×
#19
13H
FFFFB0H
×
#20
14H
FFFFACH
×
#21
15H
FFFFA8H
×
#22
16H
FFFFA4H
14
#23
17H
FFFFA0H
DTP/External interrupt ch.6/ch.7
×
#24
18H
FFFF9CH
Input capture ch.0/ch.1
7
#25
19H
FFFF98H
Reload timer ch.1
×
#26
1AH
FFFF94H
Input capture ch.2/ch.3
8
#27
1BH
FFFF90H
Reload timer ch.2
×
#28
1CH FFFF8CH
Output compare ch.0/ch.1
×
#29
1DH
FFFF88H
×
#30
1EH
FFFF84H
×
#31
1FH
FFFF80H
×
#32
20H
FFFF7CH
11
#33
21H
FFFF78H
×
#34
22H
FFFF74H
UART (Reception completed) ch.2/ch.3
10
#35
23H
FFFF70H
A/D converter/Free-run timer
15
#36
24H
FFFF6CH
UART (Send completed) ch.0/ch.1
13
#37
25H
FFFF68H
9
#38
26H
FFFF64H
12
#39
27H
FFFF60H
DTP/External interrupt ch.0/ch.1
I2C ch.1
×
DTP/External interrupt ch.2/ch.3
I2C ch.2
×
DTP/External interrupt ch.4/ch.5
PWC/Reload timer ch.0
PPG ch.0/ch.1
×
Output compare ch.2/ch.3
PPG ch.2/ch.3
×
UART (Send completed) ch.2/ch.3
PPG ch.4/ch.5
Extended serial I/O
×
×
UART (Reception completed) ch.0/ch.1
2 to 6*
2
Time-base timer/Watch timer
×
×
#40
28H
FFFF5CH
Flash memory status
×
×
#41
29H
FFFF58H
Delay interrupt output module
×
×
#42
2AH
FFFF54H
High
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
ICR06 0000B6H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
ICR12 0000BCH
ICR13 0000BDH
ICR14 0000BEH
ICR15 0000BFH
Low
(Continued)
31
MB90330A Series
(Continued)
: Available, EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.
With a stop request).
: Available (The interrupt request flag is cleared by the interrupt clear signal.)
: Available when any interrupt source sharing ICR is not used.
× : Unavailable
*1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority.
*2 : ch.2 and 3 can also be used during Mini-HOST operation.
Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted,
the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation
factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt
requests when using the EI2OS.
• The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt
factors in the same interrupt control register (ICR).
• If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are
cleared by the µDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the
DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “0” in the
appropriate resource, and take measures by software polling.
• Content of USB interruption factor
USB interrupt factor
Details
USB function 1
End Point0-IN End Point0-OUT
USB function 2
End Point1-5 *
USB function 3
SUSP SOF BRST WKUP CONF
USB function 4
SPK
USB Mini-HOST1
DIRQ CNNIRQ URIRQ RWKIRQ
USB Mini-HOST2
SOFIRQ CMPIRQ
* : Endpoints 1 and 2 can also be used during Mini-HOST operation.
32
MB90330A Series
■ PERIPHERAL RESOURCES
1. I/O port
The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90330A series model is
provided with 12 ports (94 inputs) . The ports function as input/output pins for peripheral functions also.
The port data register (PDR) can be used to send output data to the I/O pin and to receive the signal input to
the I/O port. The port direction register (DDR) can be used to set the I/O direction of the I/O pin in bit units.
The following table lists the I/O ports and the peripheral functions with which they share pins.
Port Pin Name
Pin Name (Peripheral)
Port 0
P00 to P07
⎯
(External bus)
Port 1
P10 to P17
⎯
(External bus)
P20 to P23
⎯
(External bus)
P24 to P27
PPG0 to PPG3
8/16-bit PPG timer 0, 1 (External bus)
P30 to P33
TIN1, TOT1, TIN2, TOT2
16-bit Reload timer 1, 2 (External bus)
P34 to P37
⎯
P40, P41
TIN0, TOT0
P42 to P47
SIN0, SOT0, SCK0,
SIN1, SOT1, SCK1
P50 to P57
⎯
P60, P61
INT0, INT1
P62 to P64
INT2 to INT4,
SIN, SOT, SCK
P65
INT5, PWC
External interrupt, PWC
P66, P67
INT6, INT7, SCL0, SDA0
External interrupt, I2C 0
Port 7
P70 to P77
AN0 to AN7
8/10-bit A/D converter
Port 8
P80 to P87
AN8 to AN15
8/10-bit A/D converter
P90 to P95
SIN2, SOT2, SCK2,
SIN3, SOT3, SCK3
P96
ADTG, FRCK
PA0 to PA3
IN0 to IN3
PA4 to PA7
OUT0 to OUT3
PB0 to PB3
SCL1, SDA1, SCL2, SDA2
PB4
⎯
PB5, PB6
PPG4, PPG5
Port 2
Port 3
Port 4
Port 5
Port 6
Port 9
Port A
Port B
Peripheral Function that Shares Pin
(External bus)
16-bit Reload timer 0 (External bus)
UART0, UART1 (External bus)
(External bus)
External interrupt
External interrupt, Serial I/O
UART2, 3
8/10-bit A/D converter, Free-run timer
Input capture 0, 1, 2, 3
Output compare 0, 1, 2, 3
I2C 1, 2
⎯
PPG timer 2
Note : These pins also serve as the analog input pins for ports 7 and 8. To use them as general-purpose ports, be
sure to set the corresponding bits in the analog input enable register (ADER) to 0B. The ADER is initialized
to FFH at a reset.
33
MB90330A Series
• Register list (port data register)
PDR0
bit
7
6
5
4
3
2
1
0
Initial Value
Access
Address : 000000H
P07
P06
P05
P04
P03
P02
P01
P00
XXXXXXXXB
R/W*
PDR1
15
14
13
12
11
10
9
8
P17
P16
P15
P14
P13
P12
P11
P10
XXXXXXXXB
R/W*
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
- XXXXXXXB
R/W*
XXXXXXXXB
R/W*
- XXXXXXXB
R/W*
bit
Address : 000001H
PDR2
bit
Address : 000002H
PDR3
bit
Address : 000003H
PDR4
bit
Address : 000004H
PDR5
bit
Address : 000005H
PDR6
bit
Address : 000006H
PDR7
bit
15
14
13
12
11
10
9
8
P37
P36
P35
P34
P33
P32
P31
P30
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
15
14
13
12
11
10
9
8
P57
P56
P55
P54
P53
P52
P51
P50
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
15
14
13
12
11
10
9
8
P77
P76
P75
P74
P73
P72
P71
P70
7
6
5
4
3
2
1
0
Address : 000008H
P87
P86
P85
P84
P83
P82
P81
P80
PDR9
bit
15
14
13
12
11
10
9
8
Address : 000009H
⎯
P96
P95
P94
P93
P92
P91
P90
PDRA
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
bit
7
6
5
4
3
2
1
0
Address : 00000CH
⎯
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Address : 000007H
PDR8
bit
bit
Address : 00000AH
PDRB
* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows :
• Input mode
Read : The level at the relevant pin is read.
Write : Data is written to the output latch.
• Output mode
Read : The data register latch value is read.
Write : Data is output to the relevant pin.
34
MB90330A Series
• Register list (port direction register)
DDR0
bit
Address : 000010H
DDR1
bit
Address : 000011H
DDR2
bit
Address : 000012H
DDR3
bit
Address : 000013H
DDR4
bit
Address : 000014H
DDR5
bit
Address : 000015H
DDR6
bit
Address : 000016H
DDR7
bit
Address : 000017H
DDR8
bit
Address : 000018H
DDR9
bit
Address : 000019H
DDRA
bit
Address : 00001AH
DDRB
bit
Address : 00000DH
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
15
14
13
12
11
10
9
8
D17
D16
D15
D14
D13
D12
D11
D10
7
6
5
4
3
2
1
0
D27
D26
D25
D24
D23
D22
D21
D20
15
14
13
12
11
10
9
8
D37
D36
D35
D34
D33
D32
D31
D30
7
6
5
4
3
2
1
0
D47
D46
D45
D44
D43
D42
D41
D40
15
14
13
12
11
10
9
8
D57
D56
D55
D54
D53
D52
D51
D50
7
6
5
4
3
2
1
0
D67
D66
D65
D64
D63
D62
D61
D60
15
14
13
12
11
10
9
8
D77
D76
D75
D74
D73
D72
D71
D70
7
6
5
4
3
2
1
0
D85
D84
D83
D82
D81
D80
D87
D86
15
14
13
12
11
10
9
8
⎯
D96
D95
D94
D93
D92
D91
D90
7
6
5
4
3
2
1
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
11
10
9
8
DB3
DB2
DB1
DB0
15
14
13
12
⎯
DB6
DB5
DB4
Initial Value Access
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
-0000000B
R/W
00000000B
R/W
-0000000B
R/W
• When each pin is serving as a port, the corresponding pin is controlled as follows :
0 : Input mode
1 : Output mode
This bit becomes 0 after a reset.
Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits
manipulated by the instruction are set to prescribed values but those other bits in output registers which
have been set for input are rewritten to current input values of the pins. When switching a pin from input port
to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output.
35
MB90330A Series
• Register list (Analog input enable register)
ADER0
bit
Address : 00001EH
ADER1
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
14
13
Initial Value Access
11111111B
R/W
11111111B
R/W
bit
15
Address : 00001FH
ADE15
ADE14 ADE13
12
11
10
9
8
ADE12
ADE11
ADE10
ADE9
ADE8
This register controls the port 7, 8 pins as follows.
0 : Port input/output mode.
1 : Analog input mode.
This bit becomes 1 after a reset.
• Register list (Port pull-up resistance register)
RDR0
bit
Address : 00001CH
RDR1
bit
Address : 00001DH
7
6
5
4
3
2
1
0
RD07
RD06
RD05
RD04
RD03
RD02
RD01
RD00
15
14
13
12
11
10
9
8
RD17
RD16
RD15
RD14
RD13
RD12
RD11
RD10
Initial Value Access
00000000B
R/W
00000000B
R/W
Controls the pull-up resistor in input mode.
0 : Without pull-up resistor in input mode.
1 : With pull-up resistor in input mode.
Meaningless in output mode. (Without pull-up resistor)/The input/output mode is decided by the setting of the
port direction register (DDR).
Without pull-up resistor is used in stop mode (SPL = 1). (High-Z) This function is disabled when the external
bus is used. Do not attempt to write to this register.
• Register list (Output pin register)
ODR4
bit
Address : 00001BH
7
6
5
4
3
2
1
0
OD47
OD46
OD45
OD44
OD43
OD42
OD41
OD40
Initial Value Access
00000000B
R/W
Controls open-drain in output mode.
0 : Serves as a standard output port in output mode.
1 : Serves as an open-drain output port in output mode.
Meaningless in input mode (output High-Z)./The input/output mode is decided by the setting of the port direction
register (DDR). This function is disabled when the external bus is used. Do not attempt to write to this register.
36
MB90330A Series
• Block diagram of port 0 pin and port 1 pin
Internal data bus
Pull-up resistor
setting register
(RDRx)
Internal pull-up
resistor
PDRx read
PDRx
write
Port data
register
(PDRx)
I/O decision
circuit
Port direction
register
(DDRx)
Input
buffer
Output
buffer
Port
pin
Standby control (LPMCR : SPL = “1”)
• Block diagram of port 2 pin, port 3 pin, port 4 pin, port 5 pin, port 6 pin, port 9 pin, port A pin and port B pin
Internal data bus
Resource input
PDRx read
PDRx
write
Port data
register
(PDRx)
I/O decision
circuit
Port direction
register
(DDRx)
Input
buffer
Output
buffer
Port
pin
Standby control (LPMCR : SPL = “1”)
Resource output control signal
Resource output
37
MB90330A Series
• Block diagram of port 7 pin and port 8 pin
Internal data bus
Analog input
enable
register (ADER)
A/D converter
analog input
signal
PDRx read
PDRx
write
Port data
register
(PDRx)
Port direction
register
(DDRx)
I/O decision
circuit
Input
buffer
Output
buffer
Port
pin
Standby control (LPMCR : SPL = “1”)
Notes : • When using as an input port, set “0” in the corresponding bit of the port-7 and port-8 direction register
(DDR7 and DDR8) and “0” in the related bit of the analog input enable register (ADER).
• When using as an analog input pin, set “0” in the corresponding bit of the port-7 and port-8 direction
register (DDR7 and DDR8) and “1” in the related bit of the analog input enable register (ADER).
38
MB90330A Series
2. Time-base timer
The time-base timer is an 18-bit free-run counter (time-base timer counter) that counts in synchronization with
the main clock (2 cycles of the oscillation clock HCLK). Four different time intervals can be selected, for each of
which an interrupt request can be generated. Operating clock signals are supplied to peripheral resources such
as the oscillation stabilization wait timer and watchdog timer.
• Interval time of time-base timer
Internal count clock cycle
Interval time
12
2 /HCLK (Approx. 0.68 ms)
214/HCLK (Approx. 2.7 ms)
2/HCLK (0.33 µs)
216/HCLK (Approx. 10.9 ms)
219/HCLK (Approx. 87.4 ms)
Notes : • HCLK : Oscillation clock frequency
• The parenthesized values assume an oscillator clock frequency of 6 MHz.
• Clock cycles supplied from time-base timer
Where to supply clock
Clock cycle
213/HCLK (Approx. 1.36 ms)
Main clock oscillation
stabilization wait
215/HCLK (Approx. 5.46 ms)
217/HCLK (Approx. 21.84 ms)
212/HCLK (Approx. 0.68 ms)
214/HCLK (Approx. 2.7 ms)
Watch dog timer
216/HCLK (Approx. 10.9 ms)
219/HCLK (Approx. 87.4 ms)
Notes : • HCLK : Oscillation clock frequency
• The parenthesized values assume an oscillator clock frequency of 6 MHz.
• Register list
Time-base timer control register (TBTC)
bit
15
14
Address : 0000A9H
RESV
⎯
( R/W )
(⎯)
13
12
11
10
9
8
⎯
TBIE
TBOF
TBR
TBC1
TBC0
(⎯)
( R/W )
( R/W )
(W)
( R/W )
( R/W )
Initial Value
1 - - 00100B
39
MB90330A Series
• Block Diagram
To PPG timer
To watchdog
timer
Time-base
timer counter
Dividing
HCLK by 2
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
Power-on reset
Stop mode start
Hold state start
CKSCR : MCS = 1→0*1
CKSCR : SCS = 0→1*2
To clock controller
oscillation stabilizing
wait time selector
Counter
clear
control
circuit
Interval timer selector
TBOF set
TBOF clear
Time-base timer control register (TBTC) RESV
⎯
⎯
TBIE TBOF TBR TBC1 TBC0
Time-base timer interrupt signal
−
OF
HCLK
*1
*2
: Unused
: Overflow
: Oscillation clock
: Switching the machine clock from main clock or sub clock to PLL clock
: Switching the machine clock from sub clock to main clock
Actual interrupt request number of time-base timer is as follows :
Interrupt request number : #40 (28H)
40
MB90330A Series
3. Watchdog timer
The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating
with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is
not cleared for a preset period of time after start.
• Interval time of watchdog timer
HCLK : Oscillation clock(6 MHz) SCLK : Sub clock(8 kHz)
Min
Max
Clock cycle
Approx. 2.39 ms
Approx. 3.07 ms
(214 ± 211) /HCLK
Approx. 9.56 ms
Approx. 12.29 ms
(216 ± 213) /HCLK
Approx. 38.23 ms
Approx. 49.15 ms
(218 ± 215) /HCLK
Approx. 305.83 ms
Approx. 393.22 ms
(221 ± 218) /HCLK
Approx. 0.448 s
Approx. 0.576 s
(212 ± 29) /SCLK
Approx. 3.584 s
Approx. 4.608 s
(215 ± 212) /SCLK
Approx. 7.168 s
Approx. 9.216 s
(216 ± 213) /SCLK
Approx. 14.336 s
Approx. 18.432 s
(217 ± 214) /SCLK
Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.
• The watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or
watch timer.
• Interval time of watchdog timer is longer than the set time during the following conditions.
- When clearing the timebase timer during operation on oscillation (HCLK)
- When clearing the watch timer during operation on sub clock (SCLK)
• Events that stop the watchdog timer
• Stop due to a power-on reset
• Watchdog reset
• Clear factor of watchdog timer
• External reset input by RST pin
• Writing “0” to the software reset bit
• Writing “0” to the watchdog timer control bit (second and subsequent times)
• Transition to sleep mode (clearing the watchdog timer to suspend counting)
• Transition to time-base timer mode (clearing the watchdog timer to suspend counting)
• Transition to stop mode (clearing the watchdog timer to suspend counting)
41
MB90330A Series
• Register list
Watchdog timer control register (WDTC)
bit
7
6
5
Address : 0000A8H
⎯
PONR
WRST
(⎯)
(R)
(R)
4
3
2
1
0
ERST
SRST
WTE
WT1
WT0
(R)
(R)
(W)
(W)
(W)
Initial Value
X-XXX111B
• Block Diagram
Watchdog timer control register (WDTC)
PONR
⎯
WRST ERST SRST WTE
WT1
WT0
WDCS bit of WTC
Watch mode start
Time-base timer mode start
Sleep mode start
Hold state start
Stop mode start
SCM bit of CKSCR
2
Watchdog timer
CLR and start
Counter
clear
control
circuit
Count
clock
selector
2-bit
counter
CLR
Watchdog
timer reset
generation
circuit
CLR
4
Clear
4
(Time-base timer counter)
Main clock
(dividing HCLK by 2)
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
SCLK
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK: Oscillation clock
SCLK: Sub clock
42
To
internal
reset
generation
circuit
MB90330A Series
4. Watch timer
The watch timer is a 15-bit timer using the sub clock. It can generate interval interrupts. It can also be used as
a clock source for the watchdog timer.
• Register list
Watch timer control register (WTC)
bit
7
6
Address : 0000AAH
WDCS
SCE
( R/W )
(R)
5
4
3
2
1
0
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
Initial Value
10001000B
• Block Diagram
Watch timer control register (WTC)
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
Clear
28
Sub clock
29
10
Watch counter 2
211
212
Interval
selector
Interrupt
generation
circuit
Watch timer
interrupt
213
210
213
214
215
214
To watchdog timer
43
MB90330A Series
5. 16-bit reload timer
The 16-bit reload timer has the internal clock mode to decrement in synchronization with 3 different internal
clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the
external pin. Either can be selected. This timer defines when the count value changes from 0000H to FFFFH as
an underflow. The timer therefore causes an underflow when the count reaches [reload register setting + 1].
Either mode can be selected for the count operation from the reload mode which repeats the count by reloading
the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow
occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.
• Register list
• TMCSR (Timer control status register 0 to 2)
Timer control status register (upper) (TMCSR0 to TMCSR2)
bit
Address : 000063H
000067H
00006BH
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
CSL1
CSL0
MOD2
MOD1
(⎯)
(⎯)
(⎯)
(⎯)
( R/W )
( R/W )
( R/W )
( R/W )
Initial Value
XXXX0000B
Timer control status register (lower) (TMCSR0 to TMCSR2)
bit
Address : 000062H
000066H
00006AH
7
6
5
4
3
2
1
0
MOD0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
Initial Value
00000000B
( R/W )
• 16-bit timer register/16-bit reload register
TMR0 to TMR2/TMRLR0 to TMRLR2 (upper)
bit
Address : 000065H
000069H
00006DH
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D09
D08
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
( R/W )
TMR0 to TMR2/TMRLR0 to TMRLR2 (lower)
bit
Address : 000064H
000068H
00006CH
44
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
Initial Value
XXXXXXXXB
MB90330A Series
• Block diagram
Internal data bus
TMRLR0∗1
TMRLR1∗2
TMRLR2∗3
16-bit reload register
TMR0∗1
TMR1∗2
TMR2∗3
Reload signal
∗5
UF
16-bit timer register
Count clock
generation circuit
Machine
clock φ
3
Prescaler
Clear
Trigger
Pin
TIN0∗1
TIN1∗2
TIN2∗3
Reload
control circuit
CLK
Gate
input
Valid
clock
decision
circuit
Internal
clock
Input
control
circuit
Wait signal
CLK
Clock
selector
External clock
3
2
Output control
circuit
Output signal
generation
circuit
Select
signal
⎯
⎯
⎯
EN
TOT0∗1
TOT1∗2
TOT2∗3
Operating
control
circuit
Select function
⎯
Pin
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
UF CNTE TRG
Timer control status register (TMCSR0 to TMCSR2)
*1 : ch.0
*2 : ch.1
*3 : ch.2
*4 : Interrupt number
*5 : Underflow
Interrupt request
output
#23 (17H) *1, *4
#26 (1AH) *2, *4
#28 (1CH) *3, *4
45
MB90330A Series
6. Multi function timer
The multi-function timer enables the following based on the 16-bit free-run timer.
• Output of independent waveform
• Measurement of input pulse width
• Measurement of external clock cycle
• Configuration of a multi-functional timer
16-bit free-run timer 16-bit Output Compare 16-bit Input Capture 8/16-bit PPG timer 16-bit PWC timer
1 channel
4 channels
4 channels
8-bit × 6 channels
(16-bit × 3 channels)
1 channel
• 16-bit free-run timer : 1 channel
The 16-bit free-run timer consists of a 16-bit up counter (timer data register (TCDT)), compare clear register
(CPCLR), timer control status register (TCCS), and prescaler.
The counter output value of the 16-bit free-run timer is used as the base timer for the output compare and input
capture units.
• The count clock can be set, selected from among the following eight types.
1/φ, 2/φ, 4/φ, 8/φ, 16/φ, 32/φ, 64/φ, 128/φ
φ : Machine clock frequency
• During the following conditions, the interrupt should be output.
- The counter value of 16-bit free run timer will be overflowed.
- The counter value of 16-bit free run timer will be cleared after the counter value of 16-bit free run timer = the
compare clear register value (CPCLR) (TCCS : ICRE = “1”, MODE = “1”)
• The counter value of 16-bit free run timer should be cleared to “0000H” during the following conditions.
• Reset
• When setting the clear bit (SCLR) of timer control status register (TCCS) to “1”
• When the counter value of the 16-bit free run timer = the compare clear register value (CPCLR) (TCCS :
MODE = “1”)
• When setting “0000H” to the timer data register (TCDT)
• Output compare : 4 channels
The output compare unit consists of compare registers (OCCP0 to OCCP3), compare control registers (OCS0
to OCS3), and a compare output latch.
The output compare unit can invert the output level and output an interrupt when a compare register (OCCP0
to OCCP3) value matches the counter value of the 16-bit free-run timer.
• Output compare registers can operate as 4 independent channels. The output compare registers (OCCP0 to
OCCP3) of each channel have interrupt request flags of their respective output pins.
• Pin output can be inverted by using 2 channels of output compare registers (OCCP0 to OCCP3).
• If the counter value of 16-bit free run timer = the output compare register (OCCP0 to OCCP3) (OCS0, OCS2 :
ICP0 = “1”, ICP1 = “1”), the interrupt request should be generated. (OCS0, OCS2 : ICE0 = “1”, ICE1 = “1”)
• The initial value for pin output of each channel can be set.
• Input capture : 4 channels
The input capture unit consists of the input capture data registers (IPCP0 to IPCP3) corresponding to external
input pins (IN0 to IN3) and input capture control registers (ICS01, ICS23).
The input capture unit can capture the counter value of the 16-bit free-run timer into the input capture data
register (IPCP0 to IPCP3) to generated an interrupt request upon detection of the effective edge of the signal
input through the external input.
46
MB90330A Series
• The input capture unit in each channel can operate independently.
• The effective edge of the external signal can be selected (rising edge, falling edge, both edges).
• An interrupt request can be generated upon detection of the selected effective edge of the external signal.(ICS01, ICS2 : ICE0 = “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”).
• Register list (16-bit free-run timer)
Compare clear register (CPCLR)
bit
15
14
Address : 00008BH
CL15
CL14
bit
Address : 00008AH
11
10
9
CL10
CL09
8
CL13
CL12
CL11
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
( R/W )
( R/W )
Timer data register (TCDT)
bit
15
Address : 000087H
T15
( R/W )
( R/W ) ( R/W )
( R/W ) ( R/W )
( R/W ) ( R/W )
CL08
13
12
11
10
9
8
T14
T13
T12
T11
T10
T09
T08
( R/W )
( R/W )
( R/W ) ( R/W )
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
( R/W )
( R/W )
13
12
11
10
9
8
⎯
MSI2
MSI1
MSI0
ICLR
ICRE
( R/W )
( R/W )
Timer control/status register (TCCS)
bit
15
14
Address : 000089H
ECKE
⎯
( R/W )
( R/W ) ( R/W )
( R/W ) ( R/W )
( R/W ) ( R/W )
Initial Value
0--00000B
( R/W )
6
5
4
3
2
1
0
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
CLK0
( R/W ) ( R/W ) ( R/W )
( R/W )
( R/W ) ( R/W )
Initial Value
00000000B
( R/W )
7
( R/W )
Initial Value
00000000B
( R/W )
6
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
( R/W )
14
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
( R/W )
7
( R/W )
bit
Address : 000088H
12
( R/W )
( R/W )
bit
Address : 000086H
13
Initial Value
00000000B
( R/W )
47
MB90330A Series
• Register list (output compare)
Compare register (OCCP0 to OCCP3)
bit
15
14
13
12
11
10
9
8
Address : 007919H
C15
C14
C13
C12
C11
C10
C09
C08
00791BH
00791DH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
00791FH
bit
7
6
5
4
3
2
1
0
Address : 007918H
C07
C06
C05
C04
C03
C02
C01
C00
00791AH
00791CH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
00791EH
Control register (OCS1/OCS3)
bit
15
Address : 000055H
⎯
000057H
(⎯)
Control register (OCS0/OCS2)
bit
7
Address : 000054H
ICP1
000056H
( R/W )
48
14
13
12
11
10
9
8
⎯
⎯
CMOD
OTE1
OTE0
OTD1
OTD0
(⎯)
(⎯)
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
6
5
4
3
2
1
0
ICP0
ICE1
ICE0
⎯
⎯
CST1
CST0
( R/W )
(⎯)
(⎯)
( R/W )
( R/W )
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
---00000B
Initial Value
0000--00B
MB90330A Series
• Register list (input capture)
Input capture data register (IPCP0 to IPCP3)
bit
15
14
13
Address : 007911H
CP15
CP14
CP13
007913H
(R)
(R)
(R)
007915H
007917H
bit
Address : 007910H
007912H
007914H
007916H
12
11
10
9
8
CP12
CP11
CP10
CP09
CP08
(R)
(R)
(R)
(R)
(R)
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
12
11
10
9
8
ICE2
EG31
EG30
EG21
EG20
( R/W )
( R/W )
4
3
Input capture control status register (ICS23)
bit
15
14
13
Address : 000053H
ICP3
ICP2
ICE3
( R/W )
( R/W ) ( R/W )
Input capture control status register (ICS01)
bit
7
6
5
Address : 000052H
ICP1
ICP0
ICE1
( R/W )
( R/W ) ( R/W )
ICE0
EG11
( R/W )
( R/W )
( R/W ) ( R/W )
2
1
EG10
EG01
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
00000000B
( R/W )
0
EG00
Initial Value
00000000B
( R/W )
49
MB90330A Series
• Block diagram of the 16-bit free-run timer, input capture units, and output compare units
To interrupt
#36 (24H)*
φ
3
8
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
Divider
CLK0
Clock
16-bit free-run timer
16
16-bit compare clear register
To interrupt
#36 (24H)*
Compare circuit
16
Compare register 0/2
Internal data bus
Compare circuit
16
Compare register 1/3
ICLR
MSI2 to MSI0
ICRE
T
Q
OTE0
OUT0/OUT2
T
Q
OTE1
OUT1/OUT3
CMOD
Compare circuit
4
ICP1
ICP0
IOE1
IOE0
To interrupt
#29 (1DH)*
#31 (1FH)*
Edge
detection
Capture data register 0/2
4
EG11
EG31
EG10
EG30
EG01
EG21
Edge
detection
Capture data register 1/3
4
IN0/IN2
ICP1
ICP3
ICP0
ICP2
ICE1
ICE3
ICE0
ICE2
EG00
EG20
IN1/IN3
To interrupt
#25 (19H)*
#27 (1BH)*
* : Interrupt number
φ : Machine clock frequency
50
MB90330A Series
• 8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels)
8/16-bit PPG timer consists of an 8-bit down counter (PCNT), PPG operation mode control register (PPGC0 to
PPGC5), PPG output control register (PPG01, PPG23, PPG45) and PPG reload register (PRLL0 to PRLL5,
PRLH0 to PRLH5).
When used as an 8-/16-bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an
arbitrary duty ratio at an arbitrary frequency.
• 8-bit PPG mode
Each channel operates as an independent 8-bit PPG.
• 8-bit prescaler + 8-bit PPG mode
Operates as an arbitrary-cycle 8-bit PPG with PPG0 (PPG2, PPG4) operating as an 8-bit prescaler and PPG1
(PPG3, PPG5) counted by the borrow output of PPG0 (PPG2, PPG4).
• 16-bit PPG mode
Operates as a 16-bit PPG with PPG0 (PPG2, PPG4) and PPG1 (PPG3, PPG5) connected.
• PPG operation
The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of
pulse waveform) at an arbitrary frequency. This can also be used as a D/A converter by an external circuit.
51
MB90330A Series
• Register list
PPG operation mode control register
(PPGC1/PPGC3/PPGC5)
bit
15
14
Address : 000047H
PEN1
⎯
000049H
00004BH ( R/W ) ( ⎯ )
(PPGC0/PPGC2/PPGC4)
bit
7
Address : 000046H
PEN0
000048H
00004AH ( R/W )
13
12
11
10
9
8
PE10
PIE1
PUF1
MD1
MD0
Reserved
( R/W )
( R/W )
( R/W )
6
5
4
3
2
1
0
⎯
PE00
PIE0
PUF0
⎯
⎯
Reserved
(⎯)
( R/W )
( R/W )
( R/W )
(⎯)
(⎯)
( R/W )
( R/W ) ( R/W )
Initial Value
0X000001B
( R/W )
PPG output control register (PPG01/PPG23/PPG45)
bit
7
6
5
4
3
2
1
0
Address : 00004CH
PCS2
PCS1
PCS0
PCM2
PCM1
PCM0 Reserved Reserved
00004EH
000050H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value
0X000XX1B
Initial Value
000000XXB
PPG reload register
(PRLH0 to PRLH5)
bit
15
14
13
12
11
10
9
8
Address : 007901H
D15
D14
D13
D12
D11
D10
D09
D08
007903H
007905H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
007907H
007909H
00790BH
Initial Value
XXXXXXXXB
(PRLL0 to PRLL5)
bit
7
6
5
4
3
2
1
0
Address : 007900H
D07
D06
D05
D04
D03
D02
D01
D00
007902H
007904H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
007906H
007908H
00790AH
52
Initial Value
XXXXXXXXB
MB90330A Series
• 8/16-bit PPG ch.0/ch.2/ch.4 block diagram
Peripheral clock dividing by 16
Peripheral clock dividing by 8
Peripheral clock dividing by 4
Peripheral clock dividing by 2
Peripheral clock
PPG0/PPG2/PPG4
output enable
PPG0/PPG2/PPG4
A/D converter
PPG0/PPG2/PPG4
output latch
PEN0
To interrupt
#30 (1EH)*
#32 (20H)*
IRQ #34 (22H)*
S
R Q
PCNT
(down counter)
Count clock
select
ch.1/ch.3/ch.5 borrow
“L”/“H” selector
Dividing by 512 of timebase
counter output main clock
PUF0
PIE0
“L”/“H” select
PRLL
PRLBH
PPGC0 (operating mode control)
PRLL
“L” data bus
“H” data bus
* : Interrupt number
53
MB90330A Series
• 8-bit PPG ch.1/ch.3/ch.5 block diagram
Peripheral clock dividing by 16
Peripheral clock dividing by 8
Peripheral clock dividing by 4
Peripheral clock dividing by 2
Peripheral clock
PPG1/PPG3/PPG5
output enable
PPG1/PPG3/PPG5
PPG1/PPG3/PPG5
output latch
PEN1
S
R Q
PCNT
(down counter)
IRQ
Count clock
select
To interrupt
#30 (1EH)*
#32 (20H)*
#34 (22H)*
“L”/“H” selector
Dividing by 512 timebase
counter output main clock
PUF1
PIE1
“L”/“H” select
PRLL
PRLBH
PPGC1 (operating mode control)
PRLL
“L” data bus
“H” data bus
* : Interrupt number
54
MB90330A Series
• PWC timer
The PWC timer is a 16-bit multi-function up-count timer capable of measuring the input signal pulse width.
• Register list
PWC control status register (PWCSR)
bit
15
14
Address : 00005DH
STRT
STOP
( R/W )
bit
Address : 00005CH
( R/W )
Address : 00005EH
12
11
10
9
8
EDIR
EDIE
OVIR
OVIE
ERR
Reserved
(R)
( R/W )
( R/W )
( R/W )
(R)
( R/W )
7
6
5
4
3
2
1
0
CKS1
CKS0
PIS1
PIS0
S/C
MOD2
MOD1
MOD0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
13
12
11
10
9
8
D13
D12
D11
D10
D9
D8
PWC data buffer register (PWCR)
bit
15
14
Address : 00005FH
D15
D14
bit
13
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
PWC ratio of dividing frequency control register (DIVR)
bit
7
6
5
4
Address : 000060H
⎯
⎯
⎯
⎯
(⎯)
(⎯)
(⎯)
(⎯)
( R/W ) ( R/W )
( R/W ) ( R/W )
( R/W )
3
2
1
0
⎯
⎯
DIV1
DIV0
(⎯)
(⎯)
( R/W )
( R/W )
Initial Value
0000000XB
Initial Value
00000000B
Initial Value
00000000B
Initial Value
00000000B
Initial Value
------00B
55
MB90330A Series
• Block Diagram
PWCR read
Error
detection
ERR
PWCR
16
Internal clock
(machine clock/4)
Reload
Data transfer
16
Clock
Overflow
22
F2MC-16 bus
16-bit up count timer
Control bit output
Flag set etc...
Control circuit
Overflow interrupt
request
15
PWCSR
Divider ON/OFF
8-bit
divider
PIS0/PIS1
ERR
CKS0/CKS1
Divide ratio select
2
DIVR
56
CKS1/CKS0
Count enable
Edge
detection
Measurement termination
interrupt request
Clock
divider
Divider
clear
End edge
selection
Start edge
selection
Measurement
starting edge
Measurement
termination edge
2
Timer
clear
3
Input
waveform
comparator
PWC
MB90330A Series
7. UART
UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. It supports bi-directional communication (normal mode)
and master/slave communication (multi-processor mode: supported on master side only). An interrupt can be
generated upon completion of reception, detection of a reception error, or completion of transmission. EI2OS is
supported.
• UART functions
UART, or a generic serial data communication interface that sends and receives serial data to and from other
CPU and peripherals, has the functions listed in following.
Function
Data buffer
Transmission mode
Baud rate
Data length
Signal system
Reception error detection
Interrupt request
Master/slave type
communication function
(multi processor mode)
Full-duplex double-buffered
• Clock synchronous (without start/stop bit)
• Clock asynchronous (start-stop synchronous)
• Special-purpose baud-rate generator
It is optional from 8 kinds.
• Baud rate by external clock (SCK0/SCK1/SCK2/SCK3 terminal input)
• 8-bit or 7-bit (in the asynchronous normal mode only)
• 1-bit to 8-bit (synchronous mode only)
Non Return to Zero (NRZ) system
• Framing error
• Overrun error
• Parity error (Not supported in operation mode 1)
• Receive interrupt (reception completed, reception error detected)
• Transmission interrupt (transmission completed)
• Both the transmission and reception support EI2OS.
Capable of 1 (master) to many (slaves) communication (available just as master)
Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.
• UART operation modes
Operation mode
Data length
Without parity
With parity
7-bit or 8-bit
Synchronization
0
Normal mode
Asynchronous
1
Multi processor mode
8-bit + 1*1
⎯
Asynchronous
2
Normal mode
1 to 8-bit
⎯
Synchronous
Stop bit length
1-bit or 2-bit *2
No
⎯ : Setting disabled
*1 : + 1 is an address/data setting bit (A/D) which is used for communication control.
*2 : Only one bit can be detected as a stop bit at reception.
57
MB90330A Series
• Register list
Serial mode register (SMR0 to SMR3)
bit
7
6
5
4
3
2
1
0
Address : 000020H
M2L0
MD1
MD0
SCKL
M2L2
M2L1
SCKE
SOE
000026H
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
00002CH
000032H
Serial control register (SCR0 to SCR3)
bit
15
14
13
12
11
Address : 000021H
PEN
P
SBL
CL
A/D
000027H
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
00002DH
000033H
9
8
Initial Value
REC
RXE
TXE
00000100B
(W)
( R/W )
( R/W )
Initial Value
XXXXXXXXB
13
12
11
10
9
8
Initial Value
FRE
RDRF
TDRE
BDS
RIE
TIE
00001000B
(R)
(R)
(R)
( R/W )
( R/W )
( R/W )
UART prescaler reload register (UTRLR0 to UTRLR3)
bit
7
6
5
4
3
2
1
0
Address : 000024H
D7
D6
D5
D4
D3
D2
D1
D0
00002AH
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
000030H
000036H
UART prescaler control register (UTCR0 to UTCR3)
bit
15
14
13
12
11
Address : 000025H
Reserved
MD
SRST
CKS
⎯
00002BH
( R/W ) ( R/W ) ( R/W ) ( R/W )
(⎯)
000031H
000037H
58
00100000B
10
Serial input/output data register (SIDR0 to SIDR3 / SODR0 to SODR3)
bit
7
6
5
4
3
2
1
0
Address : 000022H
D7
D6
D5
D4
D3
D2
D1
D0
000028H
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
00002EH
000034H
Serial status register (SSR0 to SSR3)
bit
15
14
Address : 000023H
PE
ORE
000029H
(R)
(R)
00002FH
000035H
Initial Value
Initial Value
00000000B
10
9
8
Initial Value
D10
D9
D8
0000-000B
( R/W )
( R/W )
( R/W )
MB90330A Series
• Block Diagram
Control bus
Special-purpose
baud-rate generator
(UART prescaler
control register
UTCR0 to UTCR3)
(UART prescaler
reload UTRLR0 to
UTRLR3)
Transmission
clock
Clock
selector
Reception Reception
control
clock
Transmission
control circuit
circuit
Reception interrupt
signal
#39 (27H)*
#35 (23H)*
Send interrupt
signal
#37 (25H)*
#33 (21H)*
Pin
SCK0 to SCK3
Start bit
detection circuit
Transmission
start circuit
Reception bit
counter
Transmission
bit counter
Reception parity
counter
Transmission
parity counter
Pin
SOT0 to SOT3
Pin
Shift register for
reception
Shift register for
transmission
SIDR0 to SIDR3
SODR0 to SODR3
SIN0 to SIN3
Reception
complete
Receive status decision
circuit
Start transmission
Reception error
occurrence signal for
EI2OS • µDMAC (to CPU)
Internal data bus
SMR0 to
SMR3
MD1
MD0
SCKL
M2L2
M2L1
M2L0
SCKE
SOE
SCR0 to
SCR3
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0 to
SSR3
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
* : Interrupt number
59
MB90330A Series
8. Extended I/O serial interface
The extended I/O serial interface is a serial I/O interface in an 8-bit, single-channel, capable of clock synchronous
data transfer. LSB-first or MSB-first transfer mode can be selected for data transfer.
There are 2 serial I/O operation modes available:
• Internal shift clock mode: Transfer data in synchronization with the internal clock.
• External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK).
By manipulating the general-purpose port sharing the external pin (SCK) in this mode, data can also be
transferred by a CPU instruction.
• Register list
Serial mode control status register (SMCS)
bit
15
14
13
Address : 000059H
bit
Address : 000058H
12
11
10
9
8
Initial Value
SIE
SIR
BUSY
STOP
STRT
00000010B
( R/W )
(R)
( R/W )
( R/W )
SMD2
SMD1
SMD0
( R/W )
( R/W )
( R/W ) ( R/W )
7
6
5
4
3
2
1
0
Initial Value
⎯
⎯
⎯
⎯
MODE
BDS
SOE
SCOE
XXXX0000B
(⎯)
(⎯)
(⎯)
(⎯)
( R/W )
( R/W )
( R/W )
( R/W )
Serial data register (SDR)
bit
7
6
5
4
3
2
1
0
Initial Value
Address : 00005AH
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
Communication prescaler control register (SDCR)
bit
15
14
13
12
MD
⎯
⎯
⎯
Address : 00005BH
( R/W )
60
(⎯)
(⎯)
(⎯)
( R/W ) ( R/W )
( R/W )
11
10
9
8
Initial Value
DIV3
DIV2
DIV1
DIV0
0XXX0000B
( R/W )
( R/W ) ( R/W )
( R/W )
MB90330A Series
• Block Diagram
Internal data bus
Initial value
D7 to D0 (LSB fast)
Transfer direction selection
(MSB fast) D0 to D7
SIN
SDR (serial data register)
Read
Write
SOT
SCK
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
SOE SCOE
Interrupt
request
Internal data bus
61
MB90330A Series
9. I2C Interface
The I2C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I2C
bus and has the following features.
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address and general call address detection function
• Detecting transmitting direction function
• Start condition repeated generation and detection function
• Bus error detection function
• Register list
I2C bus status register (IBSR0 to IBSR2)
bit
Address : 000070H
000076H
00007CH
7
6
5
4
3
2
1
0
Initial Value
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
00000000B
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
I2C bus control register (IBCR0 to IBCR2)
bit
Address : 000071H
000077H
00007DH
15
14
13
12
11
10
9
8
Initial Value
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
I2C bus clock control register (ICCR0 to ICCR2)
bit
Address : 000072H
000078H
00007EH
7
6
5
4
3
2
1
0
Initial Value
⎯
⎯
EN
CS4
CS3
CS2
CS1
CS0
XX0XXXXXB
( ⎯ )
( ⎯ )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
I2C bus address register (IADR0 to IADR2)
bit
Address : 000073H
000079H
00007FH
15
14
13
12
11
10
9
8
Initial Value
⎯
A6
A5
A4
A3
A2
A1
A0
XXXXXXXXB
( ⎯ )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
I2C bus data register (IDAR0 to IDAR2)
bit
Address : 000074H
00007AH
000080H
62
7
6
5
4
3
2
1
0
Initial Value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
MB90330A Series
• Block Diagram
ICCRx
EN
ICCRx
CS4
CS3
CS2
CS1
CS0
I2C enable
Clock divide 1
5
6
7
Peripheral clock
8
Clock selector 1
Clock divide 2
2 4 8 16
32
64
128
256
Sync
Generating shift clock
Clock selector 2
Shift clock edge change timing
F2MC-16 bus
IBSRx
BB
RSC
LRB
TRX
Bus busy
Repeat start
Last Bit
Start stop
condition detection
Error
Send/receive
First Byte
FBT
AL
Arbitration lost detection
IBCRx
SCLx
BER
BEIE
Interrupt request
IRQ
SDAx
INTE
INT
IBCRx
SCC
MSS
ACK
GCAA
End
Start
Master
ACK enable
Start stop condition
generation
GC-ACK enable
IDAR
IBSRx
AAS
GCA
Slave
Global call
Slave address
compare
IADR
63
MB90330A Series
10. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.
• Feature of USB function
• Correspond to USB Full Speed
• Full speed (12 Mbps) is supported.
• The device status is auto-answer.
• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16
• Toggle check by data synchronization bit
• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these
3 commands can be processed the same way as the class vendor commands).
• The class vendor commands can be received as data and responded via firmware.
• Supports up to 6 EndPoints (EndPoint0 is fixed to control transfer)
• 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0)
• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0)
• Register list
UDC control register (UDCC)
bit
7
Address : 0000D0H
RST
6
RESUM HCON
( R/W ) ( R/W )
bit
Address : 0000D1H
15
5
14
4
3
2
1
0
USTP Reserved Reserved
RFBK
PWC
( R/W )
( R/W )
(⎯)
(⎯)
( R/W )
( R/W )
13
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
Initial Value
10100000B
Initial Value
00000000B
EP0 control register (EP0C)
bit
Address : 0000D2H
7
6
5
4
3
2
1
0
Reserved
PKS0
PKS0
PKS0
PKS0
PKS0
PKS0
PKS0
(⎯)
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
STAL
Reserved
(⎯)
(⎯)
(⎯)
(⎯)
( R/W )
(⎯)
bit
Address : 0000D3H
Reserved Reserved
(⎯)
(⎯)
Initial Value
01000000B
Initial Value
XXXX0000B
EP1 control register (EP1C)
bit
Address : 0000D4H
bit
Address : 0000D5H
7
6
5
4
3
2
1
0
PKS1
PKS1
PKS1
PKS1
PKS1
PKS1
PKS1
PKS1
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
EPEN
TYPE
TYPE
DIR
DMAE
NULE
STAL
PKS1
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
Initial Value
00000000B
( R/W )
Initial Value
01100001B
(Continued)
64
MB90330A Series
EP2/3/4/5 control register (EP2C to EP5C)
bit
Address : 0000D6H
0000D8H
0000DAH
0000DCH
bit
Address : 0000D7H
0000D9H
0000DBH
0000DDH
7
6
5
4
3
2
1
0
Reserved PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
EPEN
TYPE
TYPE
DIR
DMAE
NULE
STAL
Reserved
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
TMSP
TMSP
TMSP
TMSP
TMSP
TMSP
TMSP
TMSP
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
TMSP
TMSP
TMSP
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(R)
(R)
(R)
7
6
5
4
3
2
1
0
⎯
⎯
SUSP
SOF
BRST
WKUP
SETP
CONF
(⎯)
(⎯)
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
13
12
11
10
9
8
Initial Value
01000000B
Initial Value
01100000B
Time stamp register (TMSP)
bit
Address : 0000DEH
bit
Address : 0000DFH
Initial Value
00000000B
Initial Value
XXXXX000B
UDC status register (UDCS)
bit
Address : 0000E0H
Initial Value
XX000000B
UDC Interrupt enable register (UDCIE)
bit
Address : 0000E1H
15
14
Reserved Reserved SUSPIE
(⎯)
(⎯)
( R/W )
SOFIE
BRSTIE WKUPIE CONFN CONFIE
( R/W )
( R/W )
( R/W )
(R)
Initial Value
00000000B
( R/W )
EP0I status register (EP0IS)
bit
Address : 0000E2H
bit
Address : 0000E3H
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
15
14
13
12
11
10
9
8
BFINI
DRQIIE
⎯
⎯
⎯
DRQI
⎯
⎯
( R/W )
( R/W )
(⎯)
(⎯)
(⎯)
( R/W )
(⎯)
(⎯)
Initial Value
XXXXXXXXB
Initial Value
10XXX1XXB
(Continued)
65
MB90330A Series
(Continued)
EP0O status register (EP0OS)
bit
Address : 0000E4H
7
6
5
4
3
2
1
0
Reserved
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
(⎯)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
15
14
13
12
11
10
9
8
⎯
⎯
DRQO
SPK
Reserved
bit
Address : 0000E5H
BFINI
DRQOIE SPKIE
( R/W )
( R/W )
( R/W )
(⎯)
(⎯)
( R/W )
( R/W )
(⎯)
7
6
5
4
3
2
1
0
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
15
14
13
12
11
10
9
8
BFINI
DRQIE
SPKIE Reserved
BUSY
DRQ
SPK
SIZE
( R/W )
( R/W )
( R/W )
(⎯)
(R)
( R/W )
( R/W )
(R)
Initial Value
0XXXXXXXB
Initial Value
100XX000B
EP1 status register (EP1S)
bit
Address : 0000E6H
bit
Address : 0000E7H
Initial Value
XXXXXXXXB
Initial Value
1000000XB
EP2/3/4/5 status register (EP2S to EP5S)
bit
Address : 0000E8H
0000EAH
0000ECH
0000EEH
7
6
5
4
3
2
1
0
Reserved
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
SIZE
(⎯)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
12
11
10
9
8
Reserved
BUSY
DRQ
SPK
Reserved
(⎯)
(R)
( R/W )
( R/W )
(⎯)
Initial Value
XXXXXXXXB
;
bit
15
14
13
Address : 0000E9H
BFINI DRQIE SPKIE
0000EBH
( R/W ) ( R/W ) ( R/W )
0000EDH
0000EFH
EP0/1/2/3/4/5 data register (EP0DT to EP5DT)
bit
Address : 0000F0H
0000F2H
0000F4H
0000F6H
0000F8H
0000FAH
bit
Address : 0000F1H
0000F3H
0000F5H
0000F7H
0000F9H
0000FBH
66
7
6
5
4
3
2
1
0
BFDT
BFDT
BFDT
BFDT
BFDT
BFDT
BFDT
BFDT
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
BFDT
BFDT
BFDT
BFDT
BFDT
BFDT
BFDT
BFDT
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
Initial Value
10000000B
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
MB90330A Series
11. USB Mini-HOST
USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred
to and from Device without PC intervention.
• Feature of USB Mini-HOST
• Automatic detection of Low Speed/Full Speed transfer
• Low Speed/Full Speed transfer support
• Automatic detection of connection and cutting device
• Reset sending function support to USB-bus
• Support of IN/OUT/SETUP/SOF token
• In-token handshake packet automatic transmission (excluding STALL)
• Out-token handshake packet automatic detection
• Supports a maximum packet length of 256 bytes.
• Error (CRC error/toggle error/time-out) various supports
• Wake-Up function support
• Differences between the USB HOST and USB Mini-HOST
HOST
Mini-HOST
×
Hub support
Bulk transfer
Transfer
Control transfer
Interrupt transfer
ISO transfer
Transfer speed
×
Low Speed
Full Speed
×
PRE packet support
SOF packet support
CRC error
Error
Toggle error
Time-out
Maximum packet < receive data
Detection of connection and cutting of device
Transfer speed detection
: Supported
× : Not supported
67
MB90330A Series
• Register list
Host control register 0 (HCNT0)
bit
Address : 0000C0H
7
6
5
4
RWKIRE URIRE CMPIRE CNNIRE
( R/W )
3
2
1
0
DIRE
SOFIRE
URST
HOST
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
14
13
12
11
10
9
8
Initial Value
00000000B
Host control register 1 (HCNT1)
bit
Address : 0000C1H
15
Reserved Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
6
5
4
3
2
1
0
DIRQ
SOFIRQ
Initial Value
00000001B
Host interruption register (HIRQ)
bit
Address : 0000C2H
7
TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
14
13
12
11
10
9
8
TOUT
CRC
HS
HS
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
5
4
3
2
1
0
Initial Value
00000000B
Host error status register (HERR)
bit
Address : 0000C3H
15
LSTSOF RERR
( R/W )
( R/W )
TGERR STUFF
Initial Value
00000011B
Host state status register (HSTATE)
bit
Address : 0000C4H
7
6
⎯
⎯
(⎯)
(⎯)
ALIVE CLKSEL SOFBUSY SUSP
( R/W )
( R/W )
( R/W )
( R/W )
TMODE CSTAT
(R)
Initial Value
XX010010B
(R)
SOF interruption FRAME comparison register (HFCOMP)
bit
Address : 0000C5H
15
14
13
12
11
10
9
8
FRAME
COMP
FRAME
COMP
FRAME
COMP
FRAME
COMP
FRAME
COMP
FRAME
COMP
FRAME
COMP
FRAME
COMP
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
Initial Value
00000000B
(Continued)
68
MB90330A Series
(Continued)
Retry timer setting register (HRTIMER)
bit
Address : 0000C6H
7
6
4
3
2
1
0
RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0
( R/W )
bit
Address : 0000C7H
5
( R/W )
15
14
( R/W )
13
( R/W )
12
( R/W )
11
( R/W )
10
( R/W )
9
( R/W )
8
RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1
( R/W )
bit
Address : 0000C8H
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
Initial Value
00000000B
( R/W )
( R/W )
1
0
7
6
5
4
3
2
⎯
⎯
⎯
⎯
⎯
⎯
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
( R/W )
( R/W )
14
13
12
11
10
9
8
RTIMER2 RTIMER2
Initial Value
00000000B
Initial Value
XXXXXX00B
Host address register (HADR)
bit
Address : 0000C9H
15
⎯
(⎯)
ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
7
6
5
4
3
2
1
0
EOF0
EOF0
EOF0
EOF0
EOF0
EOF0
EOF0
EOF0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
⎯
⎯
EOF1
EOF1
EOF1
EOF1
EOF1
EOF1
(⎯)
(⎯)
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
6
5
4
3
2
1
0
Initial Value
X0000000B
EOF setting register (HEOF)
bit
Address : 0000CAH
bit
Address : 0000CBH
Initial Value
00000000B
Initial Value
XX000000B
FRAME setting register (HFRAME)
bit
Address : 0000CCH
bit
Address : 0000CDH
7
FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
( R/W )
( R/W )
( R/W )
5
4
3
2
1
0
FRAME1 FRAME1 FRAME1
Initial Value
00000000B
Initial Value
XXXXX000B
Host token end point register (HTOKEN)
bit
Address : 0000CEH
7
6
TGGL
TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
Initial Value
00000000B
( R/W )
69
MB90330A Series
12. 8/10-bit A/D converter
The A/D converter converts analog input voltages into digital values and has the following features.
• RC sequential compare conversion method with sample and hold circuit
• Selectable 8-bit resolution or 10-bit resolution
• Analog input program-selectable from among 16 channels
Single conversion mode : Convert 1 selected channel
Scan conversion mode : Continuous plural channels (maximum 16 channels can be programmed) are converted.
Continuous conversion mode : Repeatedly convert the specified channels.
Stop conversion mode: Convert 1 channel then suspend conversion to remain on standby until the next
activation (Simultaneous conversion start available).
• An interrupt request to the CPU can be generated upon completion of A/D conversion. Suitable for continuous
processing as this interrupt activates µDMA to transfer the data resulting from A/D conversion to memory.
• The activation source can be selected from among software, external trigger (falling edge), and timer (rising
edge).
• Register list
A/D control status register lower/upper (ADCS0/ADCS1)
bit
7
6
5
4
3
Address : 000040H
MD1
MD0
⎯
⎯
⎯
bit
Address : 000041H
Address : 000043H
0
⎯
⎯
Reserved
( R/W )
(⎯)
(⎯)
(⎯)
(⎯)
(⎯)
( R/W )
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
(W)
( R/W )
4
3
2
1
0
D4
D3
D2
D1
D0
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
15
14
13
12
11
10
9
8
S10
ST1
ST0
CT1
CT0
⎯
D9
D8
( R/W )
(W)
(W)
(W)
(W)
(⎯)
(R)
(R)
11
10
9
8
ANE3
ANE2
ANE1
ANE0
( R/W ) ( R/W )
( R/W )
( R/W )
A/D conversion channel selection register (ADMR)
bit
15
14
13
12
Address : 000045H
ANS3
ANS2
ANS1
ANS0
( R/W )
70
1
( R/W )
A/D data register lower/upper (ADCR0/ADCR1)
bit
7
6
5
Address : 000042H
D7
D6
D5
bit
2
( R/W )
( R/W )
( R/W )
Initial Value
00 - - - - - 0B
Initial Value
00000000B
Initial Value
XXXXXXXXB
Initial Value
00101XXXB
Initial Value
00000000B
MB90330A Series
• Block Diagram
AVCC
AVRH
AVSS
Conversion channel
selection
ADMR
D/A converter
MP
ADTG
Sequential comparison
register
Comparator
Input
circuit
Data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
Sample & hold
circuit
Data register
Decoder
Trigger start
Timer
(PPG1 output)
Timer start
φ
ADCR0, ADCR1
A/D control status register
upper
A/D control status register
lower
ADCS0, ADCS1
Operating clock
Prescaler
71
MB90330A Series
13. DTP/External interrupt circuit
DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external
interrupt input terminal (INT7 to INT0) , and outputs the interrupt request.
• DTP/External interrupt circuit function
The DTP/External interrupt function outputs an interrupt request upon detection of the edge or level signal input
to the external interrupt input pins (INT7 to INT0).
If CPU accepts the interrupt request, and if the extended intelligent I/O service (EI2OS) is enabled, branches to
the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI2OS.
And if EI2OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer
(DTP function) performed by EI2OS.
• Overview of DTP/External interrupt circuit
External interrupt
Input pin
Interrupt source
DTP function
8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK,
P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)
The detection level or the type of the edge for each terminal can be set in the
request level setting register (ELVR).
Input of H level/L level/rising edge/falling edge.
72
Interrupt number
#18 (12H), #20 (14H), #22 (16H), #24 (18H)
Interrupt control
Enabling/disabling the interrupt request output using the DTP/interrupt enable
register (ENIR)
Interrupt flag
Holding the interrupt causes using the DTP/interrupt cause register (EIRR)
Process setting
Disable EI2OS (ICR: ISE=“0”)
Enable EI2OS (ICR: ISE=“1”)
Process
Branched to the interrupt handling
routine
After an automatic data transfer by
EI2OS, branched to the interrupt
handling routine
MB90330A Series
• Register list
DTP/Interrupt enable register (ENIR)
bit
7
6
Address : 00003CH
EN7
EN6
(R/W)
(R/W)
DTP/Interrupt source register (EIRR)
bit
15
14
Address : 00003DH
ER7
ER6
(R/W)
(R/W)
Request level setting register (ELVR)
bit
7
6
Address : 00003EH
LB3
LA3
bit
Address : 00003FH
5
4
3
2
1
0
EN5
EN4
EN3
EN2
EN1
EN0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
13
12
11
10
9
8
ER5
ER4
ER3
ER2
ER1
ER0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
5
4
3
2
1
0
LB2
LA2
LB1
LA1
LB0
LA0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial Value
00000000B
Initial Value
00000000B
Initial Value
00000000B
Initial Value
00000000B
73
MB90330A Series
• Block Diagram
Request level setting register (ELVR)
LB7
LA7
2
Pin
LB6
LA6
2
LB5
LA5
2
LB4
LA4
2
LB3
LA3
2
LB2
LA2
2
LB1
LA1
2
DTP/external interrupt input
detection circuit
Selector
LB0
LA0
2
Selector
Pin
Selector
Selector
Internal data bus
Pin
P61/INT1
P66/INT6/
SCL0
Selector
Pin
Selector
Pin
P62/INT2/
SIN
P65/INT5/
PWC
Selector
Pin
Selector
Pin
P63/INT3/
SOT
P64/INT4/
SCK
DTP/interrupt
source register
(EIRR)
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
Interrupt request signal
#18(12H)*
#20(14H)*
#22(16H)*
DTP/interrupt
enable register
(ENIR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
* : Interrupt number
74
Pin
P60/INT0
P67/INT7/
SDA0
#24(18H)*
MB90330A Series
14. Interrupt controller
The interrupt control register is located inside the interrupt controller; it exists for every I/O having an interrupt
function. This register has the following functions.
• Setting of the interrupt levels of relevant resources
• Register list
Interrupt control register (ICR01, ICR03, ICR05, ICR07, ICR09, ICR11, ICR13, ICR15)
bit
15
14
13
12
11
10
9
8
Address : ICR01 : 0000B1H
ICR03 : 0000B3H
ICS3
ICS2
ICS1
ICS0
IL2
IL1
IL0
ISE
ICR05 : 0000B5H
(W)
(W)
(W)
( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
ICR07 : 0000B7H
ICR09 : 0000B9H
ICR11 : 0000BBH
ICR13 : 0000BDH
ICR15 : 0000BFH
Interrupt control register (ICR00, ICR02, ICR04, ICR06, ICR08, ICR10, ICR12, ICR14)
bit
7
6
5
4
3
2
1
0
Address : ICR00 : 0000B0H
ICS3
ICS2
ICS1
ICS0
IL2
IL1
IL0
ISE
ICR02 : 0000B2H
ICR04 : 0000B4H
(W)
(W)
(W)
( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
ICR06 : 0000B6H
ICR08 : 0000B8H
ICR10 : 0000BAH
ICR12 : 0000BCH
ICR14 : 0000BEH
Initial Value
00000111B
Initial Value
00000111B
Note : Do not access interrupt control registers using any read modify write instruction because it causes a
malfunction.
• Block Diagram
3
3
F2MC-16LX bus
IL 2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IL 1
32
Interrupt request
(peripheral resource)
IL 0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Determine
priority
of
interrupt
3
(CPU)
Interrupt level
75
MB90330A Series
15. µDMAC
µDMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the
following features.
• Performs automatic data transfer between the peripheral resource (I/O) and memory
• The program execution of CPU stops in the DMA start-up
• Capable of selecting whether to increment the transfer source and destination addresses
• DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register, and
descriptor.
• A STOP request is available for stopping DMA transfer from the resource.
Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA
status register is set and a termination interrupt is output to the transfer controller.
• Register list
DMA enable register upper (DERH)
bit
15
14
Address : 0000ADH EN15 EN14
( R/W )
( R/W )
DMA enable register lower (DERL)
bit
7
6
Address : 0000ACH
EN7
EN6
( R/W )
( R/W )
DMA stop status register (DSSR)
bit
7
6
Address : 0000A4H STP7 STP6
13
12
11
10
9
8
EN13
EN12
EN11
EN10
EN9
EN8
( R/W )
( R/W )
( R/W )
5
4
3
2
1
0
EN5
EN4
EN3
EN2
EN1
EN0
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
4
STP4
STP12
3
STP3
STP11
2
STP2
STP10
0
STP0
STP8
( R/W )
( R/W )
( R/W ) ( R/W )
STP15
STP14
5
STP5
STP13
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
DMA status register upper (DSRH)
bit
15
14
13
12
11
10
Address : 00009DH DTE15 DTE14 DTE13 DTE12 DTE11 DTE10
( R/W )
( R/W )
DMA status register lower (DSRL)
bit
7
6
Address : 00009CH DTE7 DTE6
( R/W )
( R/W )
1
STP1
STP9
( R/W )
( R/W )
9
8
DTE9
DTE8
( R/W ) ( R/W )
( R/W )
( R/W )
( R/W )
5
4
3
2
1
0
DTE5
DTE4
DTE3
DTE2
DTE1
DTE0
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W ) ( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
Initial Value
00000000B
Initial Value
00000000B
*
Initial Value
00000000B
( R/W )
DMA descriptor channel specification register (DCSR)
bit
15
14
13
12
11
10
9
8
Address : 00009BH
Reserved
Reserved
Reserved
STP
DCSR3 DCSR2 DCSR1 DCSR0
( R/W )
Initial Value
00000000B
Initial Value
00000000B
Initial Value
00000000B
( R/W )
* : The DSSR is lower when the STP bit of DCSR in the DSSR is “0”.
The DSSR is upper when the STP bit of DCSR in the DSSR is “1”.
(Continued)
76
MB90330A Series
(Continued)
DMA buffer address pointer lower 8-bit (DBAPL)
bit
7
6
5
4
3
2
1
0
Address : 007920H DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
DMA buffer address pointer middle 8-bit (DBAPM)
bit
15
14
13
12
11
10
9
8
Address : 007921H DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
14
13
12
11
10
9
8
RDY1
BYTEL
IF
BW
BF
DIR
SE
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
DMA I/O register address pointer lower 8-bit (DIOAL)
bit
7
6
5
4
Address : 007924H
A07
A06
A05
A04
( R/W )
( R/W )
( R/W )
( R/W )
DMA I/O register address pointer upper 8-bit (DIOAH)
bit
15
14
13
12
Address : 007925H
A15
A14
A13
A12
( R/W )
( R/W )
DMA data counter lower 8-bit (DDCTL)
bit
7
6
Address : 007926H
B07
B06
( R/W )
( R/W )
DMA data counter upper 8-bit (DDCTH)
bit
15
14
Address : 007927H
B15
B14
( R/W )
( R/W )
2
1
0
A03
A02
A01
A00
( R/W )
( R/W )
11
10
9
8
A11
A10
A09
A08
( R/W ) ( R/W )
( R/W )
( R/W )
( R/W )
5
4
3
2
1
0
B05
B04
B03
B02
B01
B00
( R/W )
( R/W )
( R/W )
13
12
11
10
9
8
B13
B12
B11
B10
B09
B08
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W )
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
( R/W )
3
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
( R/W )
DMA control register (DMACS)
bit
15
Address : 007923H
RDY2
( R/W ) ( R/W )
Initial Value
XXXXXXXXB
( R/W )
DMA buffer address pointer upper 8-bit (DBAPH)
bit
7
6
5
4
3
2
1
0
Address : 007922H DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH
( R/W )
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
( R/W )
Initial Value
XXXXXXXXB
( R/W )
Initial Value
XXXXXXXXB
( R/W )
Note : The above register is switched for each channel depending on the DCSR.
77
MB90330A Series
16. External bus pin control circuit
The external bus pin control circuit controls external bus pins to extend the CPU address and data buses to
externals.
• Register list
• Automatic ready function selection register (ARSR)
bit
15
14
13
12
Address : 0000A5H
11
10
9
8
ICR1
ICR0
HMR1
HMR0
⎯
⎯
LMR1
LMR0
(W)
(W)
(W)
(W)
(⎯)
(⎯)
(W)
(W)
4
3
2
1
0
• External address output control register (HACR)
bit
7
6
5
Address : 0000A6H
E23
E22
E21
E20
E19
E18
E17
E16
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
12
11
10
9
8
(W)RE
LMBS
⎯
(W)
(W)
(⎯)
• Bus control signal selection register (EPCR)
bit
15
14
13
Address : 0000A7H
CKE
RYE
HDE
(W)
(W)
(W)
Reserved HMBS
(W)
(W)
Initial Value
0011- - 00B
Initial Value
********B
Initial Value
1000*10 -B
W :Write only
− :Unused
* :“1” or “0”
• Block Diagram
P5
P0
P0 data
P0 direction
RB
Data control
Address control
Access
control
78
Access control
P1
P2
P3
P4
P5
P0
MB90330A Series
17. Address matching detection function
When the address is equal to the value set in the address detection register, the instruction code to be read into
the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9
instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the
program patch function is enabled.
2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address
matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code
to be read into the CPU is forcibly replaced with the INT9 instruction code.
• Register list
• Program address detect register 0 to 2 (PADR0)
PADR0 (lower)
bit
7
6
5
4
3
2
1
0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Address : 001FF0H
PADR0 (middle)
bit
Address : 001FF1H
PADR0 (upper)
bit
Address : 001FF2H
• Program address detect register 3 to 5 (PADR1)
PADR1 (lower)
bit
15
14
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
3
2
1
0
ADIE
Reserved
(R/W)
(R/W)
Address : 001FF3H
PADR1 (middle)
bit
Address : 001FF4H
PADR1 (upper)
bit
Address : 001FF5H
• Program address detection control status register (PACSR)
PACSR
bit
7
Address : 00009EH
6
5
4
Reserved Reserved Reserved Reserved
(R/W)
(R/W)
(R/W)
(R/W)
ADDE Reserved
(R/W)
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Initial Value
00000000B
(R/W)
R/W : Readable and Writable
X
: Undefined
79
MB90330A Series
18. Delay interrupt generator module
The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware
interrupt can be generated by software.
• Delay interrupt generator module function
Function and control
Interrupt source
• Setting the R0 bit in the delayed interrupt request generation/release register to 1
(DIRR: R0 = 1) generates a delayed interrupt request.
• Setting the R0 bit in the delayed interrupt request generation/release register to 0
(DIRR: R0 = 0) cancels the delayed interrupt request.
Interrupt control
No setting of permission register is provided.
Interrupt flag
Set in bit R0 of the delayed interrupt request generation /clear register (DIRR : R0)
2
Not ready for extended intelligent I/O service (EI2OS).
EI OS support
• Block Diagram
Internal data bus
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Delay interrupt factor generation/release
register(DIRR)
⎯ : Undefined
80
R0
S Interrupt
request
R latch
Interrupt
request
signal
MB90330A Series
19. ROM mirror function selection module
The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read
by accessing bank 00.
• ROM mirroring function selection module function
Description
Mirror setting address
Interrupt source
EI2OS support
FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in
the 00 bank.
None.
Not ready for extended intelligent I/O service (EI2OS) .
• Block Diagram
ROM mirror function selection register (ROMM)
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
MI
Internal data bus
Address
FF bank
Address area
00 bank
Data
ROM
81
MB90330A Series
20. Low power consumption (standby) mode
The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode.
• CPU operation mode and functional description
CPU
Operation
operating
mode
clock
Normal run
PLL clock
Sleep
Description
The CPU and peripheral resources operate at the clock frequency obtained by PLL
multiplication of oscillator clock (HCLK) frequency.
Only peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) .
Time-base Only the time-base timer operates at the clock frequency obtained by PLL multiplicatimer
tion of the oscillator clock (HCLK) frequency.
Main clock
Stop
The CPU and peripheral resources are suspended with the oscillator clock stopped.
Normal run
The CPU and peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two.
Sleep
Only peripheral resources operate at the clock frequency obtained by dividing the
oscillator clock (HCLK) frequency by two.
Time-base Only the time-base timer operates at the clock frequency obtained by dividing the
timer
oscillator clock (HCLK) frequency by two.
Stop
Normal run
Sub clock
CPU
intermittent
operation
mode
The CPU and peripheral resources are suspended with the oscillator clock stopped.
The CPU and peripheral resources operate at the clock frequency obtained by
dividing the sub clock (SCLK) frequency by four.
Sleep
Only peripheral resources operate at the clock frequency obtained by dividing the sub
clock (SCLK) frequency by four.
Watch
mode
Only the watch timer operates at the clock frequency obtained by dividing the
sub clock (SCLK) frequency by four.
Stop
The CPU and peripheral resources are suspended with the sub clock stopped.
Normal run
The halved or PLL-multiplied oscillator clock (HCLK) frequency or the sub clock
(SCLK) frequency is used for operation while being decimated in a certain period.
• Register list
Low power consumption mode control register (LPMCR)
bit
7
6
5
4
3
Address : 0000A0H
STP
SLP
SPL
RST
TMD
(W)
82
(W)
( R/W )
(W)
( R/W )
2
1
0
CG1
CG0
Reserved
( R/W ) ( R/W )
( R/W )
Initial Value
00011000B
MB90330A Series
21. Clock
The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The
internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on
source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation is referred to
as PLL clock.
• Register list
Clock selection register (CKSCR)
bit
15
14
Address : 0000A1H
SCM
MCM
(R)
(R)
13
12
11
10
9
8
WS1
WS0
SCS
MCS
CS1
CS0
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
Initial Value
11111100B
83
MB90330A Series
22. 3 Mbits flash memory
The description that follows applies to the flash memory built in the MB90F334A; it is not applicable to evaluation
ROM or MASK ROM.
The flash memory is located in bank FF in the CPU memory map.
• Function to flash memory
Description
Memory capacity
Memory configuration
Sector configuration
Sector protect function
Program algorithm
84
3072 Kbits (384 Kbytes)
384 Kwords × 8 bits/192 Kwords × 16 bits
64 Kbytes × 5 + 32 Kbytes + 8 Kbytes × 2 + 16 Kbytes
Possibility that set up with a recommendation parallel writer
Automatic program algorithm (Embedded Algorithm : Similar to MBM29LV400TC)
Operation command
• Compatibility with the JEDEC standard-type command
• Built-in deletion pause/deletion resume function
• Detection of programming/erasure completion using data polling and the toggle bit
• Capable of erasing data sector by sector (in arbitrary combination of sectors)
Program/Erase cycle
At least 10000 times guaranteed
How to program and
erase memory
• Parallel programmer available for programming and erasure
(Flash Support Group, Inc. : AF9708, AF9709, AF9709B)
• Can be written and erased using a dedicated serial writer
(Yokogawa Digital Computer Corporation : AF220/AF210/AF120/AF110)
• Write/delete operation by program execution
Interrupt source
Programming/erasure completion sources
EI2OS supports
Not ready for expanded intelligent I/O service (EI2OS).
MB90330A Series
• Sector configuration of flash memory
Flash Memory CPU address Writer address *
Prohibited
SA0 (64 Kbytes)
SA1 (64 Kbytes)
SA2 (64 Kbytes)
Prohibited
SA3 (64 Kbytes)
SA4 (64 Kbytes)
SA5 (32 Kbytes)
SA6 (8 Kbytes)
SA7 (8 Kbytes)
SA8 (16 Kbytes)
F80000H
00000H
F8FFFFH
0FFFFH
F90000H
10000H
F9FFFFH
1FFFFH
FA0000H
20000H
FAFFFFH
2FFFFH
FB0000H
30000H
FBFFFFH
3FFFFH
FC0000H
40000H
FCFFFFH
4FFFFH
FD0000H
50000H
FDFFFFH
5FFFFH
FE0000H
60000H
FEFFFFH
6FFFFH
FF0000H
70000H
FF7FFFH
77FFFH
FF8000H
78000H
FF9FFFH
79FFFH
FFA000H
7A000H
FFBFFFH
7BFFFH
FFC000H
7C000H
FFFFFFH
7FFFFH
* : The writer address is relative to the CPU address when data is programmed into flash memory by a
parallel programmer. Programming and erasing by the general-purpose parallel programmer are
executed based on writer addresses.
• Register list
Flash memory control status register (FMCS)
bit
7
6
5
Address : 0000AEH
INTE RDYINT
WE
( R/W )
( R/W )
( R/W )
4
3
RDY
Reserved
(R)
(W)
2
1
0
LPM1 Reserved
LPM0
( R/W )
( R/W )
(W)
Initial Value
000X0000B
85
MB90330A Series
• Standard configuration for Fujitsu Microelectronics standard serial on-board writing
The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corporation is used for Fujitsu Microelectronics standard serial on-board writing.
Host interface cable (AZ201)
RS232C
General-purpose common cable (AZ210)
Flash
microcontroller
programmer
+
Memory card
CLK synchronous
serial
MB90F334A
user system
Can operate stand alone
Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the
AF220, AF210, AF120 and AF110 flash microcontroller programmer, general-purpose common cable for
connection (AZ210) and connectors.
• Pins Used for Fujitsu Microelectronics Standard Serial On-board Programming
Pin
86
Function
Description
MD2,
Mode input pins
MD1, MD0
The device enters the serial program mode by setting MD2=1, MD1=1
and MD0 =0.
X0, X1
Oscillation pins
Because the internal CPU operation clock is set to be the 1 multiplication
PLL clock in the serial write mode, the internal operation clock frequency
is the same as the oscillation clock frequency.
P60, P61
Programming program
start pins
Input a Low level to P60 and a High level to P61.
RST
Reset input pin
SIN0
Serial data input pins.
SOT0
Serial data output pin
SCK0
Serial clock input pin
⎯
UART0 is used as CLK synchronous mode.
In program mode, the pins used for the UART0 CLK synchronous mode
are SIN0, SOT0 and SCK0.
VCC
Power source input pin
When supplying the write voltage (MB90F334A : 3.3 V ± 0.3 V) from the
user system, connection with the flash microcontroller programmer is not
necessary.
When connecting, do not short-circuit with the user power supply.
VSS
GND Pin
Share GND with the flash microcontroller programmer.
MB90330A Series
The control circuit shown in the figure is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the
user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcontroller programmer.
• Control circuit
AF220, AF210, AF120, AF110
program control pin
MB90F334A program control
pin
10 kΩ
AF220, AF210, AF120, AF110,
/TICS pin
User
The MB90F334A serial clock frequency that can be input is determined by the following expression:
Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the
oscillator clock frequency to be used.
Inputable serial clock frequency = 0.125 × oscillation clock frequency.
• Maximum serial clock frequency
Maximum serial clock
Oscillation
frequency acceptable to the
clock frequency
flash microcontroller
At 6 MHz
Maximum serial clock
frequency that can be set
with the AF220, AF210,
AF120 or AF110
Maximum serial clock
frequency that can be set
with the AF200
500 kHz
500 kHz
750 kHz
• System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa Digital
Computer Corporation)
Part number
Unit
Function
AF220/AC4P
Model with internal Ethernet interface
/100 V to 220 V power adapter
AF210/AC4P
Standard model
/100 V to 220 V power adapter
AF120/AC4P
Single key internal Ethernet interface mode
/100 V to 220 V power adapter
AF110/AC4P
Single key model
/100 V to 220 V power adapter
AZ221
PC/AT RS232C cable for writer
AZ210
Standard target probe (a) length : 1 m
FF201
Control module for Fujitsu Microelectronics F2MC-16LX flash microcontroller control
module
AZ290
Remote controller
/P4
4 Mbytes PC Card (option) Flash memory capacity to 512 Kbytes correspondence
Contact to : Yokogawa Digital Computer Corporation TEL : 81-423-33-6224
Note : The AF200 flash microcontroller programmer is a retired product, but it can be supported using control
module FF201.
87
MB90330A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
AVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ AVCC*2
AVRH
VSS − 0.3
VSS + 4.0
V
AVCC ≥ AVR ≥ 0 V*3
VSS − 0.3
VSS + 4.0
V
*4
VSS − 0.3
VSS + 6.0
V
N-ch open-drain
(Withstand voltage of
5 V I/O)*5
− 0.5
VSS + 4.5
V
USB I/O
VSS − 0.3
VSS + 4.0
V
*4
− 0.5
VSS + 4.5
V
USB I/O
ICLAMP
− 2.0
+2.0
mA
*6
Σ⏐ICLAMP⏐
⎯
20
mA
*6
IOL1
⎯
10
mA
Other than USB I/O*7
IOL2
⎯
43
mA
USB I/O*7
IOLAV1
⎯
4
mA
*8
IOLAV2
⎯
15/4.5
mA
USB-IO (Full speed/
Low speed) *8
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*9
IOH1
⎯
− 10
mA
Other than USB I/O*7
IOH2
⎯
− 43
mA
USB I/O*7
IOHAV1
⎯
−4
mA
*8
IOHAV2
⎯
−15/−4.5
mA
USB-IO (Full speed/
Low speed) *8
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
340
mW
Operating temperature
TA
− 40
+ 85
°C
− 55
+ 150
°C
− 55
+ 125
°C
1
Power supply voltage*
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum total output current
“L” level average total output current
“H” level maximum output current
“H” level average output current
“H” level maximum total output current
“H” level average total output current
Storage temperature
VI
VO
Tstg
*9
USB I/O
*1 : The parameter is based on VSS = AVSS = 0.0 V.
*2 : Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*3 : Be careful not to let AVRH exceed AVcc.
*4 : VI and VO must not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*5 : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST
(Continued)
88
MB90330A Series
(Continued)
*6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,
P80 to P87, P90 to P95, PB5, PB6
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, DVP, DVM,
HVP, HVM, UTEST, HCON
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*7 : A peak value of an applicable one pin is specified as a maximum output current.
*8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a
period of 100 ms.
*9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during
a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
89
MB90330A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
3.0
3.6
V
At normal operation (when using USB)
2.7
3.6
V
At normal operation (when not using USB)
1.8
3.6
V
Hold state of stop operation
VIH
0.7 VCC
VCC + 0.3
V
CMOS input pin
VIHS1
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input pin
VIHS2
0.8 VCC
VSS + 5.3
V
N-ch open-drain
(Withstand voltage of 5 V I/O)*
VIHM
VCC − 0.3
VCC + 0.3
V
MD pin input
VIHUSB
2.0
VCC + 0.3
V
USB pin input
VIL
VSS − 0.3
0.3 VCC
V
CMOS input pin
VILS
VSS − 0.3
0.2 VCC
V
CMOS hysteresis input pin
VILM
VSS − 0.3
VSS + 0.3
V
MD pin input
VILUSB
VSS
0.8
V
USB pin input
Differential input
sensitivity
VDI
0.2
⎯
V
USB pin input
Differential common
mode input voltage
range
VCM
0.8
2.5
V
USB pin input
Operating
temperature
TA
− 40
+ 85
°C
When not using USB
0
+ 70
°C
When using USB
Power supply voltage
Input “H” voltage
Input “L” voltage
VCC
* : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
90
MB90330A Series
3. DC Characteristics
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Output “H”
voltage
Output “L”
voltage
Input leak
current
Symbol
VOH
VOL
IIL
Pin name
Output pins other than
P60 to P67, P96,
PA0 to PA7, PB0 to PB4,
HVP, HVM, DVP, DVM
HVP, HVM, DVP, DVM
Output pins other than
HVP, HVM, DVP, DVM
HVP, HVM, DVP, DVM
Output pins other than
P60 to P67, P96,
PA0 to PA7,
PB0 to PB4, HVP, HVM,
DVP, DVM
HVP, HVM, DVP, DVM
Conditions
Value
Unit
Min Typ Max
Remarks
VCC
− 0.5
⎯
Vcc
V
RL = 15 kΩ ± 5%
2.8
⎯
V
IOL = 4.0 mA
Vss
⎯
V
0
⎯
3.6
Vss
+ 0.4
0.3
VCC = 3.3 V,
Vss < VI < VCC
− 10
⎯
+ 10
µA
⎯
−5
⎯
+5
µA
25
50
100
kΩ
⎯
0.1
10
µA
⎯
75
85
mA MB90F334A
⎯
65
75
mA MB90333A
⎯
70
80
mA MB90F334A
⎯
60
70
mA MB90333A
⎯
27
40
mA
⎯
3.5
10
mA
⎯
1
2
mA
⎯
25
150
µA
IOH = − 4.0 mA
RL = 1.5 kΩ ± 5%
Pull-up
VCC = 3.3 V,
RPULL P00 to P07, P10 to P17
resistance
TA = + 25 °C
Open drain
P60 to P67, P96,
output
ILIOD
⎯
PA0 to PA7, PB0 to PB4
current
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating
At USB operating
(USTP = 0)
ICC
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating
At non-operating USB
(USTP = 1)
VCC = 3.3 V,
Power
Internal frequency 24 MHz,
ICCS
supply
VCC
At sleep mode
current
VCC = 3.3 V,
Internal frequency 24 MHz,
At timer mode
ICTS
VCC = 3.3 V,
Internal frequency 3 MHz,
At timer mode
VCC = 3.3 V,
Internal frequency 8 kHz,
ICCL
At sub clock operation,
(TA = +25 °C)
V
(Continued)
91
MB90330A Series
(Continued)
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Value
Unit
Min
Typ
Max
VCC = 3.3 V,
Internal frequency 8 kHz,
At sub clock,
At sleep operating,
(TA = + 25 °C)
⎯
10
50
µA
ICCT
VCC = 3.3 V,
Internal frequency 8 kHz,
Watch mode,
(TA = + 25 °C)
⎯
1.5
40
µA
ICCH
TA = + 25 °C,
At stop
⎯
1
40
µA
ICCLs
Power
supply
current
Conditions
VCC
Input
capacitance
CIN
Other than AVcc,
AVss, Vcc, Vss
⎯
⎯
5
15
pF
Pull-up
resistor
Rup
RST
⎯
25
50
100
kΩ
USB I/O
output
impedance
ZUSB
DVP, DVM
HVP, HVM
⎯
3
⎯
14
Ω
Remarks
Note : P60 to P67, P96, PA0 to PA7, and PB0 to PB4 are N-ch open-drain pins usually used as CMOS.
92
MB90330A Series
4. AC Characteristics
(1)Clock input timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
SymPin name
bol
Parameter
Value
Min
Typ
Max
Unit
Remarks
⎯
6
⎯
MHz When oscillator is used
6
⎯
24
MHz External clock input
⎯
32.768
⎯
kHz
⎯
166.7
⎯
ns
When oscillator is used
166.7
⎯
41.7
ns
External clock input
⎯
30.5
⎯
s
X0
10
⎯
⎯
ns
PWHL
PWLL
X0A
⎯
15.2
⎯
s
Input clock rise time and fall
time
tcr
tcf
X0
⎯
⎯
5
ns
Internal operating clock
frequency
fCP
⎯
3
⎯
24
MHz When main clock is used
fCPL
⎯
⎯
8.192
⎯
kHz When sub clock is used
tCP
⎯
42
⎯
333
ns
When main clock is used
tCPL
⎯
⎯
122.1
⎯
s
When sub clock is used
fCH
X0, X1
fCL
X0A, X1A
tHCYL
X0, X1
tLCYL
X0A, X1A
PWH
PWL
Clock frequency
Clock cycle time
Input clock pulse width
Internal operating clock
cycle time
A reference duty ratio is
30% to 70%.
At external clock
• Clock Timing
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tcr
tcf
tLCYL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tcf
tcr
93
MB90330A Series
• PLL operation guarantee range
Relation between power supply voltage and internal operation clock frequency
PLL operation guarantee range
Power voltage VCC (V)
3.6
3.0
2.7
Normal Operation
Assurance Range
3
6
12
24
Internal clock FCP (MHz)
Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V.
Relation between internal operation clock frequency and external clock frequency
Multiplied by 4
Internal clock FCP (MHz)
24
Multiplied by 2
12
External clock
6
Multiplied by 1
3
6
24
External clock Fc (MHz)
94
MB90330A Series
The AC standards assume the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Hysteresis input/other than MD input pin
0.7 VCC
0.3 VCC
95
MB90330A Series
(2)Clock output timing
Parameter
Cycle time
CLK↑→CLK↓
Symbol Pin name
tCYC
tCHCL
Conditions
⎯
CLK
CLK
VCC = 3.0 V to 3.6 V
(VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Unit
Remarks
Min
Max
tCP
⎯
ns
tCP/2 − 15
tCP/2 + 15
ns
At fcp = 24 MHz
tCP/2 − 20
tCP/2 + 20
ns
At fcp = 12 MHz
tCP/2 − 64
tCP/2 + 64
ns
At fcp = 6 MHz
Note : tCP : Refer to “ (1) Clock input timing”.
tCYC
tCHCL
2.4 V
CLK
96
2.4 V
0.8 V
MB90330A Series
(3) Reset
Parameter
Symbol
Pin
name
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Conditions
Unit
Remarks
Min
Max
⎯
500
Reset input time
tRSTL
RST
ns
At normal operating,
At time base timer mode,
At main sleep mode,
At PLL sleep mode
µs
At stop mode,
At sub clock mode,
At sub sleep mode,
At watch mode
⎯
Oscillation time
of oscillator* +
500 ns
⎯
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. It takes several milliseconds to several
dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a
ceramic oscillator, and 0 milliseconds on an external clock.
• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 Vcc
0.2 Vcc
• During stop mode, sub clock mode, sub-sleep mode and watch mode
tRSTL
RST
0.2 Vcc
X0
Internal
operation
clock
0.2 Vcc
90% of
amplitude
Oscillation time
of oscillator
500 ns
Oscillation stabilization wait time
Execute
instruction
Internal reset
97
MB90330A Series
(4) Power-on reset
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to +85 °C)
Parameter
Power supply rising
time
Power supply shutdown
time
Symbol Pin name Conditions
tR
VCC
tOFF
VCC
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
⎯
Remarks
Waiting time until
power-on
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Notes : • VCC must be lower than 0.2 V before the power supply is turned on.
• The above standard is a value for performing a power-on reset.
• In the device, there are internal registers which is initialized only by a power-on reset.
When the initialization of these items is expected, turn on the power supply according to the standards.
• Sudden change of power supply voltage may activate the power-on reset function.
When changing the power supply voltage during operation as illustrated below, voltage fluctuation should
be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL
clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms
or less.
3.0 V
VSS
98
RAM data hold
MB90330A Series
(5) UART0, UART1, UART2, UART3 I/O extended serial timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCKx
SCK↓→SOT delay time
tSLOV
SCKx,
SOTx
Valid SIN→SCK↑
tIVSH
SCKx,
SINx
SCK↑→valid SIN hold time
tSHIX
Serial clock H pulse width
Conditions
Value
Unit
Min
Max
8 tCP
⎯
ns
− 80
+ 80
ns
100
⎯
ns
SCKx,
SINx
60
⎯
ns
tSHSL
SCKx, SINx
4 tCP
⎯
ns
Serial clock L pulse width
tSLSH
SCKx, SINx
4 tCP
⎯
ns
SCK↓→SOT delay time
tSLOV
SCKx,
SOTx
⎯
150
ns
Valid SIN→SCK↑
tIVSH
SCKx,
SINx
60
⎯
ns
SCK↑→valid SIN hold time
tSHIX
SCKx,
SINx
60
⎯
ns
Internal shift clock
mode output pin is :
CL = 80 pF + 1TTL
External shift clock
mode output pin is :
CL = 80 pF + 1TTL
Notes : • Above rating is the case of CLK synchronous mode.
• CL is a load capacitance value on pins for testing.
• tCP : Refer to “ (1) Clock input timing”.
99
MB90330A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
100
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90330A Series
(6) I2C timing
Parameter
SCL clock frequency
(Repeat) [start] condition hold
time
SDA ↓ → SCL ↓
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Conditions
Unit
Min
Max
fSCL
tHDSTA
SCL clock “L” width
tLOW
SCL clock “H” width
tHIGH
Repeat [start] condition setup time
SCL ↑ → SDA ↓
tSUSTA
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data setup time
SDA ↓ ↑ → SCL ↑
[Stop] condition setup time
SCL ↑ → SDA ↑
Bus free time between [stop]
condition and [start] condition
tSUDAT
tSUSTO
tBUS
0
100
kHz
4.0
⎯
µs
4.7
⎯
µs
4.0
⎯
µs
4.7
⎯
µs
0
3.45*3
µs
Power-supply voltage of external pull-up
resistor at 5.0 V.
fCP*1 ≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
250*4
⎯
Power-supply voltage of external pull-up
resistor at 5.0 V.
fCP*1 > 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
fCP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2
200*4
⎯
4.0
⎯
µs
4.7
⎯
µs
Power-supply voltage of external pull-up
resistor at 5.0 V.
R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
R = 1.0 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 5.0 V.
R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
R = 1.0 kΩ, C = 50 pF*2
ns
*1 : fCP is internal operating clock frequency. Refer to “ (1) Clock input timing”.
*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA, SCL set-up time”.
101
MB90330A Series
• Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending
on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating
of the input data set-up time cannot be satisfied.
•Timing definition
SDA
tLOW
tBUS
tHDSTA
tSUDAT
SCL
tHDSTA
102
tHDDAT
tHIGH
tSUSTA
tSUSTO
MB90330A Series
(7) Timer input timing
Parameter
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit
Min
Max
FRCK,
INx, TINx,
PWC
tTIWH
tTIWL
Input pulse width
⎯
⎯
4 tCP
ns
Note : tCP : Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
PWC
TINx
INx
FRCK
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(8) Timer output timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Conditions
Unit
Min
Max
Parameter
CLK↑→TOUT change time
TOTx,
PPG0 to PPG5 change time
tTO
⎯
PPGx,
OUT0 to OUT3 change time
⎯
30
ns
OUTx
2.4 V
CLK
tTO
PPGx
OUTx
2.4 V
0.8 V
(9) Trigger input timing
Parameter
Input pulse width
Symbol
tTRGH
tTRGL
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name Conditions
Unit
Remarks
Min
Max
INTx,
ADTG
⎯
5 tCP
⎯
ns
At normal operating
1
⎯
µs
In Stop mode
Note : tCP : Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
0.2 VCC
INTx
ADTGx
tTRGH
0.2 VCC
tTRGL
103
MB90330A Series
(10) Bus read timing
Parameter
ALE pulse width
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
SymPin name Conditions
Unit
Remarks
bol
Min
Max
tLHLL
ALE
⎯
ns
At fcp = 24 MHz
tCP/2 − 20
⎯
ns
At fcp = 12 MHz
tCP/2 − 35
⎯
ns
At fcp = 6 MHz
tCP/2 − 17
⎯
ns
tCP/2 − 40
⎯
ns
Valid address→ALE↓time
tAVLL
Address,
ALE
⎯
ALE↓→Address valid time
tLLAX
ALE,
Address
⎯
tCP/2 − 15
⎯
ns
Valid address→RD↓time
tAVRL
RD,
Address
⎯
tCP − 25
⎯
ns
Valid address→valid data
input
tAVDV
Address/
data
⎯
⎯
5 tCP/2 − 55
ns
⎯
5 tCP/2 − 80
ns
At fcp = 6 MHz
RD pulse width
tRLRH
RD
⎯
3 tCP/2 − 25
⎯
ns
At fcp = 24 MHz
3 tCP/2 − 20
⎯
ns
At fcp = 12 MHz
RD↓→valid data input
tRLDV
RD,
Data
⎯
⎯
3 tCP/2 − 55
ns
⎯
3 tCP/2 − 80
ns
RD↓→data hold time
tRHDX
RD,
Data
⎯
0
⎯
ns
RD↑→ALE↑time
tRHLH
RD, ALE
⎯
tCP/2 − 15
⎯
ns
RD↑→address valid time
tRHAX
Address,
RD
⎯
tCP/2 − 10
⎯
ns
Valid address→CLK↑time
tAVCH
Address,
CLK
⎯
tCP/2 − 17
⎯
ns
RD↓→CLK↑time
tRLCH
RD, CLK
⎯
tCP/2 − 17
⎯
ns
ALE↓→RD↓time
tLLRL
RD, ALE
⎯
tCP/2 − 15
⎯
ns
Note : tCP : Refer to “ (1) Clock input timing”.
104
⎯
tCP/2 − 15
At fcp = 6 MHz
At fcp = 6 MHz
MB90330A Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
ALE
2.4 V
2.4 V
tLHLL
2.4 V
0.8 V
tRLRH
2.4 V
RD
tAVLL
tLLAX
0.8 V
tLLRL
In multiplex mode
tAVRL
A23 to A16
tRLDV
2.4 V
2.4 V
0.8 V
0.8 V
tAVDV
AD15 to AD00
2.4 V
2.4 V
tRHDX
0.7 VCC
0.7 VCC
Read data
Address
0.8 V
0.8 V
0.3 VCC
0.3 VCC
tRHAX
In non-multiplex mode
A23 to A00
tRHAX
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
D15 to D00
0.7 VCC
0.7 VCC
Read data
0.3 VCC
0.3 VCC
105
MB90330A Series
(11) Bus write timing
Parameter
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Pin name Conditions
Unit
Remarks
Min
Max
Valid address→WR↓
time
tAVWL
Address,
WR
WR pulse width
tWLWH
WRL, WRH
Valid data output→WR↑
time
tDVWH
Data, WR
tWHDX
WR,
Data
WR↑→data hold time
⎯
tCP − 15
⎯
ns
⎯
3 tCP/2 − 25
⎯
ns
At fcp = 24 MHz
⎯
3 tCP/2 − 20
⎯
ns
At fcp = 12 MHz
⎯
3 tCP/2 − 15
⎯
ns
⎯
10
⎯
ns
At fcp = 24 MHz
⎯
20
⎯
ns
At fcp = 12 MHz
⎯
30
⎯
ns
At fcp = 6 MHz
WR↑→address valid time
tWHAX
WR,
Address
⎯
tCP/2 − 10
⎯
ns
WR↑→ALE↑time
tWHLH
WR, ALE
⎯
tCP/2 − 15
⎯
ns
WR↓→CLK↑time
tWLCH
WR, CLK
⎯
tCP/2 − 17
⎯
ns
Note : tCP : Refer to “ (1) Clock input timing”.
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tWLWH
2.4 V
WR
(WRL, WRH)
0.8 V
In multiplex mode
tAVWL
A23 to A16
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
2.4 V
Address
0.8 V
2.4 V
0.8 V
0.8 V
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
D15 to D00
2.4 V
0.8 V
106
2.4 V
Write data
In non-multiplex mode
A23 to A00
tWHDX
Write data
tWHDX
2.4 V
0.8 V
MB90330A Series
(12) Ready input timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
RDY set-up time
tRYHS
RDY hold time
tRYHH
Pin name
RDY
Conditions
Value
Unit
Min
Max
⎯
35
⎯
ns
⎯
70
⎯
ns
⎯
0
⎯
ns
2.4 V
Remarks
fcp = 6 MHz
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
RDY
wait not
applied
RDY
wait applies
(1cycle)
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tRYHS
107
MB90330A Series
(13) Hold timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
Pin name
Pin floating → HAK ↓ time
tXHAL
HAK
HAK ↓ → pin valid time
tHAHV
HAK
Conditions
⎯
Value
Max
30
tCP
ns
tCP
2 tCP
ns
Notes : • It takes one cycle or more for HAK to change after the HRQ pin is captured.
• tCP : Refer to “ (1) Clock input timing”.
HAK
2.4 V
0.8 V
tXHAL
2.4 V
Each pin
108
0.8 V
tHAHV
High-Z
Unit
Min
2.4 V
0.8 V
MB90330A Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Resolution
⎯
Total error
Parameter
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
± 3.0
LSB
Nonlinear error
⎯
⎯
⎯
⎯
± 2.5
LSB
Differential linear
error
⎯
⎯
⎯
⎯
± 1.9
LSB
Zero transition
voltage
VOT
AN0 to AN15
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
mV
VFST
AN0 to AN15
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
mV
Conversion time
⎯
⎯
⎯
176 tCP*1
⎯
ns
Sampling time
⎯
⎯
⎯
64 tCP*1
⎯
ns
Analog port input
current
IAIN
AN0 to AN15
⎯
⎯
10
µA
Analog input
voltage
VAIN
AN0 to AN15
0
⎯
AVRH
V
Reference
voltage
⎯
AVRH
2.7
⎯
AVCC
V
Power supply
current
IA
AVCC
⎯
1.4
3.5
mA
IAH
AVCC
⎯
⎯
5
µA
Full-scale transition
voltage
Remarks
1 LSB = AVRH/1024
Reference voltage
supplying current
IR
AVRH
⎯
95
170
µA
IRH
AVRH
⎯
⎯
5
µA
Interchannel
disparity
⎯
AN0 to AN15
⎯
⎯
4
LSB
*2
*2
*1 : tCP : Refer to “ 4. AC Characteristics (1) Clock input timing”.
*2 : The current when the CPU is in stop mode and the A/D converter is not operating (For VCC = AVCC = AVRH = 3.3 V).
109
MB90330A Series
Notes :
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
R
1.9 kΩ (Max)
1.9 kΩ (Max)
1.9 kΩ (Max)
MB90333A
MB90F334A
MB90V330A
C
32.3 pF (Max)
25.0 pF (Max)
32.3 pF (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
MB90333A/
MB90V330A
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB90F334A
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
MB90333A/
MB90V330A
20
18
16
14
12
10
8
6
4
2
0
MB90F334A
0
1
2
3
4
5
6
7
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH| becomes smaller, values of relative errors grow larger.
110
8
MB90330A Series
A/D Converter Glossary
Resolution :
Analog changes that are identifiable with the A/D converter.
Linearity error :
The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error :
The total error is defined as a difference between the actual value and the theoretical
value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FFH
3FEH
Digital output
3FDH
Actual conversion
value
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Measured value)
003H
Actual conversion
value
002H
Theoretical
characteristics
001H
0.5 LSB
AVRL
AVRH
Analog input
Total error for digital output N =
1 LSB (Theoretical value) =
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVss [V]
1024
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V]
VFST (Theoretical value) = AVR − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) H to NH
(Continued)
111
MB90330A Series
(Continued)
Linearity error
Actual conversion
value
3FEH
{1 LSB × (N − 1)
+ VOT }
Digital output
3FDH
Theoretical
characteristics
(N + 1)H
VFST
(Measured
value)
004H
003H
002H
001H
VNT
(Measured value)
Digital output
3FFH
Differential linearity error
Actual conversion
value
Actual conversion
value
NH
V (N + 1) T
(Measured
value)
(N − 1)H
VNT
(Measured value)
(N − 2)H
Actual conversion
value
Theoretical
characteristics
VOT (Measured value)
AVRL
AVRH
AVRL
Linearity error of
=
digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linearity error
V (N + 1) T − VNT
=
1 LSB
of digital output N
1 LSB =
AVRH
Analog input
Analog input
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
112
MB90330A Series
6. USB characteristics
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Symbol
Min
Max
VIH
2.0
⎯
V
VIL
⎯
0.8
V
VDI
0.2
⎯
V
Differential common mode range
VCM
0.8
2.5
V
Output High level voltage
VOH
2.8
3.6
V
IOH = − 200 µA
Output Low level voltage
VOL
0.0
0.3
V
IOL = 2 mA
Cross over voltage
VCRS
1.3
2.0
V
tFR
4
20
ns
Full Speed
tLR
75
300
ns
Low Speed
tFF
4
20
ns
Full Speed
tLF
75
300
ns
Low Speed
tRFM
90
111.11
%
(TFR/TFF)
tRLM
80
125
%
(TLR/TLF)
ZDRV
28
44
Ω
Including Rs = 27 Ω
RS
25
30
Ω
Recommended value =
27 Ω at using USB*
Parameter
Input High level voltage
Input Low level voltage
Input
characteristics Differential input sensitivity
Rise time
Output
characteristics
Fall time
Rising/falling time matching
Output impedance
Series resistance
Unit
Remarks
* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV.
• Data signal timing (Full Speed)
Rise time
DVP/HVP
90%
Vcrs
Fall time
90%
10%
10%
DVM/HVM
tFF
tFR
• Data signal timing (Low Speed)
Rise time
HVP
HVM
90%
Vcrs
Fall time
90%
10%
10%
tLR
tLF
113
MB90330A Series
• Load condition (Full Speed)
ZUSB
DVP/HVP
RS = 27 Ω
Testing point
CL = 50 pF
ZUSB
DVM/HVM
RS = 27 Ω
Testing point
CL = 50 pF
• Load condition (Low Speed)
ZUSB
HVP
RS = 27 Ω
Testing point
CL = 50 pF to 150 pF
ZUSB
HVM
RS = 27 Ω
Testing point
CL = 50 pF to 150 pF
114
MB90330A Series
7. Flash memory write/erase characteristics
Parameter
Condition
Unit
Remarks
15
s
Excludes 00H programming
prior to erasure.
9
⎯
s
Excludes 00H programming
prior to erasure.
⎯
16
3600
µs
Except for over head time of
system level
⎯
10000
⎯
⎯
cycle
Average
TA = + 85 °C
20
⎯
⎯
year
Sector erase time
Chip erase time
TA = + 25 °C
VCC = 3.0 V
Word (16-bit width)
programming time
Programming/erase cycle
Flash memory data
retaining period
Value
Min
Typ
Max
⎯
1
⎯
*
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
115
MB90330A Series
■ ORDERING INFORMATION
Part number
116
Package
MB90F334APFF
MB90333APFF
120-pin plastic LQFP
(FPT-120P-M05)
MB90F334APMC
MB90333APMC
120-pin plastic LQFP
(FPT-120P-M21)
MB90V330A
299-pin ceramic PGA
(PGA-299C-A01)
Remarks
For evaluation
MB90330A Series
■ PACKAGE DIMENSIONS
120-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
14.0 × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.62 g
Code
(Reference)
P-LFQFP120-14×14-0.40
(FPT-120P-M05)
120-pin plastic LQFP
(FPT-120P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8˚
LEAD No.
1
0.40(.016)
30
0.16±0.03
(.006±.001)
0.07(.003)
M
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
C
2003 FUJITSU LIMITED F120006S-c-4-5
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
117
MB90330A Series
(Continued)
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
M ounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
1
30
0.50(.020)
C
"A"
31
0.22±0.05
(.009±.002)
0.08(.003)
M
2002 FUJITSU LIMITED F120033S-c-4-4
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
118
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB90330A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
3
■ INTERNAL PERIPHERAL FUNCTION
(RESOURCE)
4
■ PRODUCT LINEUP
64
■ PERIPHERAL RESOURCES
10. USB Function
• Feature of USB function
Change Results
Changed as follows
conform to USB2.0 Full Speed →
correspond to USB Full Speed
The vertical lines marked in the left side of the page show the changes
119
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
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Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
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Germany
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Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
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FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited
Strategic Business Development Dept.