FUJITSU SEMICONDUCTOR
DATA SHEET
Preliminary
2004.07.22
16-bit Proprietary Microcontroller
CMOS
R
MB90800 Series
MB90803/F804/V800
■ DESCRIPTION
The MB90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed realtime processing required for industrial and office automation equipment and process control, etc. The LCD
controller of 48 segment four common is built into.
Instruction set has taken over the same AT architecture as in the F2MC*-8L and F2MC 16L, and is further enhanced
to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and
enrichment of bit processing. In addition, long word processing is now available by introducing a 32-bit accumulator.
* : F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or 1 to 4 times the oscillation (at
oscillation of 6.25 MHz, 6.25 MHz to 25 MHz).
• Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock, operation
at Vcc = 3.3 V)
• The maximum memory space:16 MB
• 24-bit internal addressing
• Bank addressing
(Continued)
■ PACKAGE
100-pin plastic QFP
(FPT-100P-M06)
MB90800 Series
(Continued)
• Optimized instruction set for controller applications
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• High code efficiency
• Enhanced high-precision computing with 32-bit accumulator
• Enhanced Multiply/Divide instructions with sign and the RETI instruction
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Instruction set has symmetry and barrel shift instructions
• Program Patch Function (2 address pointer)
• 4-byte instruction queue
• Interrupt function
• The priority level can be set to programmable.
• Interrupt function with 32 factors
• Data transfer function
• Expanded intelligent I/O service function (EI 2 OS): Maximum of 16 channels]
• Low Power Consumption Mode
• Sleep mode (a mode that helts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock and time-base timer)
• Watch timer mode (mode in which only the subclock and watch timers operate)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode (operating CPU at each set cycle)
• Package
• LQFP-120P (FPT-100P-M06:0.65 mm pin pitch)
• Process : CMOS technology
2
MB90800 Series
■ BUILT-IN PERIPHERAL FUNCTION (RESOURCE)
• I/O port : 68 or less (sub-clocking 70 unused)
• Time-base timer : 1channel
• Watchdog timer : 1 channel
• Watch timer : 1channel
• LCD Controller
• 48SEG 4COM
• 8/10-bit A/D converter : 12 channels
• 8-bit resolution or 10-bit resolution can be set.
• 16-bit reload timer : 3 channels
• Multi-functional timer
• 16-bit free run timer : 1 channel
• 16-bit Output Compare : 2 channels
An interrupt request can be output when the count value of the 16-bit free-run timer and the setting value in
the compare register match.
• Input capture : 2 channels
Upon detecting a valid edge of the signal input from the external input pin, the count value of the 16-bit freerun timer is loaded into the input capture data register and an interrupt request can be output.
• 16-bit PPG timer : 2 channels
• 16-bit reload timer : 3 channels
• UART : 2 channels
• Extended I/O serial interface : 2 channels
• DTP/External interrupt circuit : 4 channels
• Activate the extended intelligent I/O service by external interrupt input
• Interrupt output by external interrupt input
• Timer clock output circuit
• Delay interrupt output module
• Output an interrupt request for task switching
• I2C Interface : 1 channel
3
MB90800 Series
■ PRODUCT LINEUP
1. MB90800 Series
Part number
MB90F804-101/201
MB90803/S
FLASH MEMORY
Mask ROM
Type
For evaluation
built-in type
built-in type
On-chip PLL clock multiplication method( × 1, × 2, × 3, × 4, 1/2 when PLL stops)
System clock
Minimum instruction execution time of 40.0 ns
(at oscillation of 6.25 MHz, four times the PLL clock)
ROM capacity
No
256 Kbytes
128 Kbytes
RAM capacity
28 Kbytes
16 Kbytes
4 Kbytes
Number of basic instructions : 351
Minimum instruction execution time : 40.0 ns/6.25 MHz oscillator
(When four times is used : machine clock
CPU functions
25 MHz, Power supply voltage : 3.3 V ± 0.3 V)
Addressing type : 23 types
Program Patch Function : 2 address pointers
The maximum memory space : 16MB
I/O port (CMOS) 68 ports (shared with resources), (70 ports when the subclock is
Ports
not used)
Segment driver that can drive the LCD panel (liquid crystal display) directly, and
LCD controller/driver
common driver 48 SEG × 4 COM
16-bit free-run
1 channel
timer
Overflow interrupt
16-bit
input/
Output compare
2 channels
output
(OCU)
Pin input factor: matching of the compare register
timer
Input capture
2 channels
(ICU)
Rewriting a register value upon a pin input (rising edge, falling edge, or both edges)
16-bit reload timer operation (toggle output, single shot output selectable)
16-Bit Reload Timer
The event count function is optional. The event count function is optional.
Three channels are built in.
Output pin × 2 ports
16-bit PPG timer
Operating clock frequency : fcp, fcp/22, fcp/24, fcp/26
Two channels are built in.
Clock with a frequency of external input clock divided by 16/32/64/128 can be
Timer clock output circuit
output externally.
2
I C bus
I2C Interface. 1 channel is built-in.
12 channels (input multiplex)
8/10-bit A/D converter
The 8-bit resolution or 10-bit resolution can be set.
Conversion time : 5.9 µs (When machine clock 16.8 MHz works).
Full-duplex double buffer
UART
Asynchronous/synchronous transmit (with start/stop bits) are supported.
Two channels are built in.
Extended I/O serial interface
Two channels are built in.
Four channel independence (A/D input and using combinedly)
Interrupt delay interrupt
Interrupt causes : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable
8 channels (The 8 channels include with the shared A/D input)
DTP/External interrupt
Interrupt causes：“L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable
Low Power Consumption Mode Sleep mode/Timebase timer mode/Watch mode/Stop mode/CPU intermittent mode
Process
CMOS
Operating voltage
2.7 V to 3.6 V
4
MB90V800
MB90800 Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P23/SEG31
P22/SEG30
P21/SEG29
P20/SEG28
P17/SEG27
P16/SEG26
P15/SEG25
X0
X1
VSS
VCC
P14/SEG24
P13/SEG23
P12/SEG22
P11/SEG21
P10/SEG20
P07/SEG19
P06/SEG18
P05/SEG17
P04/SEG16
(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P03/SEG15
P02/SEG14
P01/SEG13
P00/SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
VSS
VCC
SEG1
SEG0
P84/COM3
P83/COM2
COM1
COM0
V3
V2/P82
V1/P81
V0/P80
RST
MD0
MD1
MD2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P56/SO0
AVCC
P57/SI1
P76
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5/INT0
P66/AN6/INT1
P67/AN7/INT2
VSS
P70/AN8/INT3
P71/AN9/SC1
P72/AN10/SO1
P73/AN11/SI2
P74/SDA/SC2
P75/SCL/SO2
P24/SEG32
P25/SEG33
P26/SEG34
P27/SEG35
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P33/SEG39/TMCK
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37SEG43/OCU1
X0A/P90
X1A/P91
VCC
VSS
P40/LED0
P41/LED1
P42/LED2
P43/LED3
P44/LED4
P45/LED5/TOT0
P46/LED6/TOT1
P47/LED7/TOT2
P50/SEG44/TIN0
P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
P54/SI0
P55/SO0
(FPT-100P-M06)
5
MB90800 Series
■ PIN DESCRIPTION
Pin No.
QFP
Pin Name
Circuit Status/function
Type*
at reset
Description
X0, X1
A
Oscillation
status
It is a terminal which connects the oscillator.
When connecting an external clock, leave the x1 pin
side unconnected.
X0A, X1A
B
Oscillation
status
It is 32 kHz oscillation pin.
(Dual-line model)
P90, P91
G
Port input
(High-Z)
General purpose input/output port.
(Single-line model)
51
MD2
M
Mode Pins
Input pin for selecting operation mode.
Connect directly to Vss.
52, 53
MD1, MD0
L
Mode Pins
Input pin for selecting operation mode.
Connect directly to Vcc.
54
RST
K
Reset input
External reset input pin.
63, 64,
67 to 72,
73 to 76
SEG0 to
SEG11
D
LCD SEG
output
92, 93
13, 14
77 to 84
SEG12 to
SEG19
A segment output terminal of the LCD controller/
driver.
E
P00 to P07
85 to 89,
94 to 96
97 to 100,
1 to 4
SEG20 to
SEG27
General purpose input/output port.
E
General purpose input/output port.
A segment output terminal of the LCD controller/
driver.
E
P20 to P27
General purpose input/output port.
Port input
(High-Z)
SEG36
5
A segment output terminal of the LCD controller/
driver.
P10 to P17
SEG28 to
SEG35
P30
E
General purpose input/output port.
A segment output terminal of the LCD controller/
driver.
SEG37
P31
A segment output terminal of the LCD controller/
driver.
Serial data output pin of serial I/O channel 3.
Valid when serial data output of serial I/O channel 3
is enabled.
SO3
6
A segment output terminal of the LCD controller/
driver.
E
SC3
General purpose input/output port.
Serial clock I/O pin of serial I/O channel 3.
Valid when serial clock output of serial I/O channel 3
is enabled.
* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.
(Continued)
6
MB90800 Series
Pin No.
QFP
Pin Name
Circuit Status/function
Type*
at reset
A segment output terminal of the LCD controller/
driver.
SEG38
P32
7
General purpose input/output port.
E
Serial data input pin of serial I/O channel 3.
This pin may be used at any time during serial I/O
channel 3 in input mode, so do not use it as other pin
function.
SI3
A segment output terminal of the LCD controller/
driver.
SEG39
8
9, 10
11, 12
P33
E
General purpose input/output port.
TMCK
Timer clock output pin.
It is effective when permitting the power output.
SEG40,
SEG41
A segment output terminal of the LCD controller/
driver.
P34, P35
E
General purpose input/output port.
IC0, IC1
External trigger input pin of input capture channel 0/
channel 1.
SEG42,
SEG43
A segment output terminal of the LCD controller/
driver.
P36, P37
E
Port input
(High-Z)
OCU0,
OCU1
17 to 21
Description
LED0 to
LED4
Output terminal for the Output Compares.
F
P40 to P44
It is a output terminal for LED (IOL = 15 mA).
P45 to P47
General purpose input/output port.
F
TOT0 to
TOT2
SEG44 to
SEG45
External event output pin of reload timer channel 0
to chanel 2.
It is effective when permitting the external event
output.
A segment output terminal of the LCD controller/
driver.
P50, P51
25, 26
It is a output terminal for LED (IOL = 15 mA).
General purpose input/output port.
LED5 to
LED7
22 to 24
General purpose input/output port.
General purpose input/output port.
E
TIN0,
TIN1
External clock input pin of reload timer channel 0,
channel 1.
It is effective when permitting the external clock
input.
* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.
(Continued)
7
MB90800 Series
Pin No.
QFP
Pin Name
Circuit Status/function
Type*
at reset
A segment output terminal of the LCD controller/
driver.
SEG46
P52
27
28
General purpose input/output port.
E
TIN2
External clock input pin of reload timer channel 2.
It is effective when permitting the external clock
input.
PPG0
PPG timer (ch0) output pin.
SEG47
A segment output terminal of the LCD controller/
driver.
P53
E
General purpose input/output port.
PPG1
29
SIO
PPG (ch1) timer output pin.
Serial data input pin of UART channel 0.
This pin may be used at any time during UART
channel 0 in receiving mode, so do not use it as other
pin function.
G
P54
30
31
33
Description
SC0
General purpose input/output port.
Port input
(High-Z)
G
Serial clock input/output pin of UART channel 0.
It is effective when permitting the serial clock output
of UART channel 0.
P55
General purpose input/output port.
SO0
Serial data output pin of UART channel 0.
It is effective when permitting the serial clock output
of UART channel 0.
G
P56
General purpose input/output port.
SI1
Serial data input pin of UART channel 1.
This pin may be used at any time during UART
channel 1 in receiving mode, so do not use it as other
pin function.
G
P57
34
P76
36 to 40
AN0 to
AN4
General purpose input/output port.
G
General purpose input/output port.
I
Analog input pin channel 0 to channel 4 of A/D
converter. Enabled when analog input setting is
" enabled "(set by ADER).
P60 to P64
General purpose input/output port.
* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.
(Continued)
8
MB90800 Series
Pin No.
QFP
Pin Name
Circuit
Type*
Status/function
at reset
Analog input pin channel 5 to channel 7 of A/D
converter. Enabled when analog input setting is
" enabled "(set by ADER).
AN5 to
AN7
41 to 43
P65 to P67
I
INT0 to
INT2
General purpose input/output port.
Analog input
(High-Z)
AN8
45
46
47
48
Description
I
Functions as an external interrupt ch0 to ch2 input
pin.
Analog input pin channel 8 of A/D converter.
Enabled when analog input setting is " enabled "(set
by ADER).
P70
General purpose input/output port.
INT3
Functions as an external interrupt ch3 input pin.
AN9
Analog input pin channel 9 of A/D converter.
Enabled when analog input setting is " enabled "(set
by ADER).
P71
I
General purpose input/output port.
SC1
Serial clock input/output pin of UART channel 1.
It is effective when permitting the serial clock output
of UART channel 1.
AN10
Analog input pin channel 10 of A/D converter.
Enabled when analog input setting is " enabled "(set
by ADER).
P72
I
Port input
(High-Z)
General purpose input/output port.
SO1
Serial data output pin of serial I/O channel 1.
Valid when serial data output of serial I/O channel 1
is enabled.
AN11
Analog input pin channel 11 of A/D converter.
Enabled when analog input setting is " enabled "(set
by ADER).
P73
I
SI2
General purpose input/output port.
Serial data input pin of serial I/O channel 2.
This pin may be used at any time during serial I/O
channel 2 in input mode, so do not use it as other pin
function.
* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.
(Continued)
9
MB90800 Series
(Continued)
Pin No.
QFP
Pin Name
Circuit Status/function
Type*
at reset
Data input/output pin of I2C Interface.
This function is enabled when the operation of the
I2C interface is permitted. While the I2C interface is
running, the port must be set for input use.
SDA
49
P74
H
General purpose input/output port.
(N-ch open drain)
SC2
Port input
(High-Z)
SCL
50
P75
H
55 to 57
COM0,
COM1
J
LCD controller/driver.
LCD drive power Reference power terminals of LCD controller/driver.
supply input
General purpose input/output port.
D
LCD COM
output
Port input
(Hi-Z)
P83, P84
A common output terminal of the LCD controller/
driver.
General purpose input/output port.
61, 62
COM2,
COM3
E
32
AVCC
C
A/D converter exclusive power supply input pin.
35
AVSS
C
A/D converter-exclusive GND power supply pin.
58
V3
J
15, 65, 90
VCC
These are power supply input pins.
16, 44,
66, 91
VSS
GND power supply pin.
Power supply
* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.
10
Clock input/output pin of I2C Interface.
This function is enabled when the operation of the
I2C interface is permitted. While the I2C interface is
running, the port must be set for input use.
Serial data output pin of serial I/O channel 2.
Valid when serial data output of serial I/O channel 2
is enabled.
P80 to P82
59, 60
Serial clock input pin of serial I/O channel 2.
Valid when serial clock output of serial I/O channel 2
is enabled.
General purpose input/output port.
(N-ch open drain)
SO2
V0 to V2
Description
A common output terminal of the LCD controller/
driver.
LCD controller/driver
Reference power terminals of LCD controller/driver.
MB90800 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Clock input
Pch
A
• Oscillation feedback resistance :
1 MΩ approx.
Nch
X0
Standby control signal
X1A
Clock input
Pch
B
• Low-rate oscillation feedback resistor,
approx.10 MΩ
Nch
X0A
Standby control signal
• Analog power supply input protection
circuit
Pch
C
AVP
Nch
• LCDC output
Pch
LCDC output
D
Nch
• CMOS output
• LCDC output
• Hysteresis input
(With input interception function at
standby)
Pch
Nch
E
LCDC output
Input signal
Standby control signal
(Continued)
11
MB90800 Series
Type
Circuit
Remarks
• CMOS output
(Heavy-current IOL =15 mA for LED
drive)
• Hysteresis input
(With input interception function at
standby)
Pch
Nch
F
Input signal
Standby control signal
Pch
Nch
G
Input signal
Standby control signal
Nch
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
<Note>
Output of input/output port and built-in
resource share one output buffer.
Input of input/output port and built-in
resource share one input buffer.
• Hysteresis input
(With input interception function at
standby)
• N-ch open drain output
Nout
H
Input signal
Standby control signal
Pch
Nch
I
Input signal
Standby control signal
A/D converter
Analog input
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• Analog input
(If the bit of analog input enable
register = 1, the analog input of A/D
converter is enabled.)
<Note>
Outp put of input/output port and built-in
resource share one output buffer.
Input of input/output port and built-in
resource share one input buffer.
(Continued)
12
MB90800 Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• LCD drive power supply input
Pch
Nch
J
Input signal
Standby control signal
LCD drive power supply
• CMOS hysteresis input with pull-up
resistor.
K
Reset input
• CMOS hysteresis input
L
M
Reset input
Input
• CMOS hysteresis input with pull-down
resistor
13
MB90800 Series
■ HANDLING DEVICES
1. Preventing Latchup, Turning on Power Supply
Latchup may occur on CMOSICs under the following conditions:
• If a voltage higher than VCC or lower than VSS is applied to input and output pins,
• A voltage higher than the rated voltage is applied between VCC and VSS.
• If the AVCC power supply is turned on before the VCC voltage.
Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the
digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as
VCC and the digital power supply).
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using CMOSICs, take great care to prevent the occurrence of latchup.
2. Treatment of unused pins
Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down
registor. If the A/D converter is not used, connect the pins under the following conditions: AVcc = Vcc and
AVss = Vss.
3. About the attention when the external clock is used
・Using external clock
X0
OPEN
X1
4. Treatment of power supply pins (VCC/VSS)
To prevent malfunctions of strobe signals due to the rise in the ground level, lower the level of unnecessary
electro-magnetic emission, and prevent latchup, and conform to the total current rating in designing devices if
multiple VCC or VSS pins exist. Pay attention to connect a power supply to VCC and VSS of MB90800 series device
in a lowest-possible impedance. In addition, near pins of MB90800 series device, connecting a bypass capacitor
is recommended at 0.1 µF across VCC and VSS.
5. Crystal oscillators circuit
Noise near the X0/X1 and X0A/X1A pin may cause the device to malfunction. Design a print circuit so that X0/
X1 and X0A/X1A, a crystal oscillator (or a ceramic oscillator) , and bypass capacitor to the ground become as
close as possible to each other. Furthermore, avoid wires to crossing each other as much as possible. It is highly
recommended that you should use a printed circuit board artwork because you can expect stable operations
from it.
6. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed. Performance of this operation, however, cannot be guaranteed.
14
MB90800 Series
7. Stabilization of Supply Power Supply
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage
operating range.Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should
be controlled so that VCC ripple variations (peak- to-peak values) at commercial frequencies (50 MHz/60 Mhz)
fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at
instantaneous power switching.
8. Note on Using the two-subsystem product as one-subsystem product
If you are using only one subsystem of the MB90800 series that come in one two-subsystem product, use it with
X0A = VSS and X1A = OPEN.
9. Write to FLASH
Ensure that you must write to FLASH at the operating voltage VCC = 3.13 V to 3.6 V.
Ensure that you must normal write to FLASH at the operating voltage VCC = 3.0 V to 3.6 V.
15
MB90800 Series
■ BLOCK DIAGRAM
X0, X1
X0A∗, X1A∗
RST
Clock control
circuit
V0/P80
V1/P81
V2/P82
V3
COM0
COM1
P83/COM2
P84/COM3
RAM (4/16/28 KB)
12
P20-P27/SEG28-SEG35
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P33/SEG39/TMCK
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37/SEG43/OCU1
8
8
8
Port
0
LCD
Controller/
Driver
F2MC-16LX BUS
P10-P17/SEG20-SEG27
ROM/FLASH (128/256 KB)
Port
8
SEG0-SEG11
P00-P07/SEG12-SEG19
CPU F2MC-16LX
core
Interrupt controller
Port
6
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5/INT0
P66/AN6/INT1
P67/AN7/INT2
Port
7
P70/AN8/INT3
P71/AN9/SC1
P72/AN10/SO1
P73/AN11/SI2
P74/SDA/SC2
P75/SCL/SO2
P76
Port
9
P90∗
P91∗
10 bits PPG
A/D converter
External
interrupt (4 ch)
Port
1
I 2C
Port
2
Serial I/O 2/3
Port
3
Prescaler
2/3
OCU0/1
Free-run timer
P40/LED0
P41/LED1
P42/LED2
P43/LED3
P44/LED4
P45/LED5/TOT0
P46/LED6/TOT1
P47/LED7/TOT2
P50/SEG44/TIN0
P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
P54/SI0
P55/SC0
P56/SO0
P57/SI1
16
Port
4
ICU0/1
＊：X0A/X1A and P90/P91 can be switched
by mask option.
Timer clock output
Reload timer
0/1/2
Port
5
PPG0/1
UART0/1
Prescaler
0/1
Specification of the evaluation device (MB90V800)
• Built-in ROM is not exist.
• The device has 28 KB built-in RAM.
MB90800 Series
■ MEMORY MAP
ROM mirror function
FFFFFFH
ROM area
Address #2
00FFFFH
ROM mirror area
008000H
007917H
007900H
Extended IO area 2
Address #2
RAM area
Register
000100H
0000CFH
0000C0H
0000BFH
000000H
Extended IO area 1
IO area
Part number
Address #1
Address #2
MB90803
0010FFH
FE0000H
MB90F804
0040FFH
FC0000H
MB90V800
0070FFH
F80000H*
* : ROM is not built into V products.
I must think ROM decipherment region on the tool side.
Memory Map of MB90800 Series
Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses
( "FF4000H to FFFFFFH" ) of bank FF is visible from the higher addresses ( " 008000H to 00FFFFH " ) of
bank 00.
• For setting of the ROM mirror function, see “■ PERIPHERAL RESOURCE 17. ROM Mirror Function
Selection Module”.
Reference:
• The ROM mirror function is for using the C compiler small model.
• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Note that because the ROM area
of bank FF exceeds
32 K bytes, all data in the ROM area cannot be shown in mirror image in bank 00.
• When the C compiler small model is used, the data table mirror image can be shown at " 008000H to 00FFFFH
" by storing the data table at " FF8000H to FFFFFFH. Therefore, data tables in the ROM area can be referenced
without declaring the far addressing with the pointer.
17
MB90800 Series
■ F2MC-16L CPUProgramming model
• Dedicated Registers
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
• General purpose registers
MSB
LSB
16 bit
000180H + RP × 10H
RW0
RL0
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
• Processor status
13 12
15
PS
18
ILM
8 7
RP
0
CCR
MB90800 Series
■ I/O MAP
Address
Register
abbreviation
Read/
Write
Resource name
Initial Value
000000H
PDR0
Port 0 data register
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
Port 7
- XXXXXXXB
000008H
PDR8
Port 8 data register
R/W
Port 8
- - - XXXXXB
000009H
PDR9
Port 9 data register
R/W
Port 9
- - - - - - XXB
Register
00000AH
to
00000FH
Prohibited
000010H
DDR0
Port 0 direction register
R/W
Port 0
0 0 0 0 0 0 0 0B
000011H
DDR1
Port 1 direction register
R/W
Port 1
0 0 0 0 0 0 0 0B
000012H
DDR2
Port 2 direction register
R/W
Port 2
0 0 0 0 0 0 0 0B
000013H
DDR3
Port 3 direction register
R/W
Port 3
0 0 0 0 0 0 0 0B
000014H
DDR4
Port 4 direction register
R/W
Port 4
0 0 0 0 0 0 0 0B
000015H
DDR5
Port 5 direction register
R/W
Port 5
0 0 0 0 0 0 0 0B
000016H
DDR6
Port 6 direction register
R/W
Port 6
0 0 0 0 0 0 0 0B
000017H
DDR7
Port 7 direction register
R/W
Port 7
- 0 0 0 0 0 0 0B
000018H
DDR8
Port 8 direction register
R/W
Port 8
- - - 0 0 0 0 0B
000019H
DDR9
Port 9 direction register
R/W
Port 9
- - - - - - 0 0B
00001AH
to
00001DH
Prohibited
00001EH
ADER0
Analog input enable 0
R/W
Port 6, A/D
1 1 1 1 1 1 1 1B
00001FH
ADER1
Analog input enable 1
R/W
Port 7, A/D
- - - - 1 1 1 1B
000020H
SMR0
Mode Register ch0
R/W
000021H
SCR0
Control register ch0
R/W
000022H
S1DR0/
SODR0
000023H
SSR0
000024H
000025H
000026H
to
000027H
Input/output data register ch0
R/W
Status register ch0
0 0 0 0 0 - 0 0B
0 0 0 0 0 1 0 0B
UART0
R/W
XXXXXXXXB
0 0 0 0 10 0 0B
Prohibited.
CDCR0
Communication prescaler control
register ch0
R/W
Prescaler 0
0 0 - - 0 0 0 0B
Prohibited
(Continued)
19
MB90800 Series
Read/
Write
Address
Register
abbreviation
000028H
SMR1
Mode Register ch1
R/W
0 0 0 0 0 - 0 0B
000029H
SCR1
Control register ch1
R/W
0 0 0 0 0 1 0 0B
00002AH
SIDR1/
SODR1
Input/output data register ch1
R/W
00002BH
SSR1
Status register ch1
R/W
Register
00002CH
00002DH
Resource name
UART1
Initial Value
XXXXXXXXB
0 0 0 0 1 0 0 0B
Prohibited
CDCR1
Communication prescaler control register ch1
00002EH
R/W
Prescaler 1
0 0 - - 0 0 0 0B
Prohibited
00002FH
000030H
ENIR
External interrupt enable
R/W
000031H
EIRR
External interrupt request
R/W
000032H
ELVR
External interrupt level (lower)
R/W
0 0 0 0 0 0 0 0B
00------B
000033H
ADCS0
A/D control status register (lower)
R/W
000035H
ADCS1
A/D control status register (upper)
R/W
000036H
ADCR0
A/D data register (lower)
R
000037H
ADCR1
A/D data register (upper)
R/W
000038H
00003AH
00003BH
00003CH
00003DH
External interrupt
XXXXXXXXB
Prohibited
000034H
000039H
- - - - 0 0 0 0B
A/D converter
0 0 0 0 0 0 0 0B
XXXXXXXXB
0 0 1 0 1 XXXB
Prohibited
ADMR
A/D conversion channel set register
R/W
CPCLR
Compare clear register
R/W
Timer Data register
R/W
TCDT
A/D converter
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
16-bit free-run
timer
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
00003EH
TCCSL
Timer control status register (lower)
R/W
0 0 0 0 0 0 0 0B
00003FH
TCCSH
Timer control status register (upper)
R/W
0 - - 0 0 0 0 0B
000040H
to
000043H
000044H
000045H
000046H
000047H
000048H
Prohibited
IPCP0
R
IPCP1
Input Capture register 1
ICS01
Input capture control status 0/1
000049H
00004AH
00004BH
00004CH
00004DH
XXXXXXXXB
Input Capture register 0
XXXXXXXXB
Input Capture 0/1
XXXXXXXXB
XXXXXXXXB
R/W
0 0 0 0 0 0 0 0B
Prohibited
OCCP0
Output Compare register 0
R/W
Output compare 0
OCCP1
Output Compare register 1
R/W
Output compare 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
20
MB90800 Series
Address
Register
abbreviation
Register
Read/
Write
00004EH
OCSL
Output compare control status (lower)
R/W
00004FH
OCSH
Output compare control status (upper)
R/W
000050H
TMCSR0L
Timer control status register 0 (lower)
R/W
000051H
TMCSR0H
Timer Control Status register 0 (upper)
R/W
000052H
TMR0/
TMRLR0
Timer register 0/Reload register 0
R/W
000053H
000054H
TMCSR1L
Timer control status register 1 (lower)
R/W
000055H
TMCSR1H
Timer control status register 1 (upper)
R/W
000056H
000057H
TMR1/
TMRLR1
Timer register 1/Reload register 1
R/W
000058H
TMCSR2L
Timer control status register 2 (lower)
R/W
000059H
TMCSR2H
Timer control status register 2 (upper)
R/W
00005AH
TMR2/
TMRLR2
Timer register 2/Reload register 2
R/W
00005BH
00005CH
LCRL
LCDC control register (lower)
R/W
00005DH
LCRH
LCDC control register (upper)
R/W
00005EH
LCRR
LCDC range register
R/W
00005FH
000060H
000061H
SMCS0
Serial mode control status register
(ch2)
R/W
Serial Data Register (ch2)
R/W
SDR0
000063H
SDCR0
Control register of clock dividing
frequency (ch2)
R/W
SMCS1
Serial mode control status register
(ch3)
R/W
Serial Data Register (ch3)
R/W
Control register of clock dividing
frequency (ch3)
R/W
000065H
000066H
SDR1
000067H
SDCR1
000068H
00006BH
Output Compare
0/1
0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
0 0 0 0 0 0 0 0B
16-bit reload
timer 0
- - - - 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
Reload timer 1
- - - - 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
Reload timer 2
- - - - 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 1 0 0 0 0B
LCD controller/
driver
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - 0 0 0 0B
SIO
(Extended Serial
I/O)
0 0 0 0 0 0 1 0B
Communication
prescaler (SIO)
0 - - - 0 0 0 0B
SIO
(Extended Serial
I/O)
0 0 0 0 0 0 1 0B
Communication
prescaler (SIO)
0 - - - 0 0 0 0B
XXXXXXXXB
- - - - 0 0 0 0B
XXXXXXXXB
Prohibited
000069H
00006AH
Initial Value
Prohibited
000062H
000064H
Resource name
IBSR
IBCR
I2C bus status register
2
I C bus control register
2
R
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
2
IC
00006CH
ICCR
I C bus clock selection register
R/W
00006DH
IADR
I2C bus address register
R/W
- XXXXXXXB
00006EH
IDAR
I2C bus data register
R/W
XXXXXXXXB
00006FH
ROMM
ROM mirror
W
ROM mirror
- - 0XXXXXB
XXXXXXX1B
(Continued)
21
MB90800 Series
Address
Register
abbreviation
000070H
PDCRL0
000071H
PDCRH0
000072H
PCSRL0
000073H
PCSRH0
000074H
PDUTL0
000075H
PDUTH0
000076H
PCNTL0
000077H
PCNTH0
000078H
PDCRL1
000079H
PDCRH1
00007AH
PCSRL1
00007BH
PCSRH1
00007CH
PDUTL1
00007DH
PDUTH1
00007EH
PCNTL1
00007FH
PCNTH1
Read/
Write
Register
PPG0 down counter register
R
PPG0 cycle set register
W
PPG0 duty setting register
R/W
PPG1 down counter register
R
PPG1 cycle set register
W
PPG1 duty setting register
PPG1 control status register
000097H
(Reserved)
000098H
to
00009DH
Prohibited
DIRR
0000A0H
0000A1H
XXXXXXXXB
- - 0 0 0 0 0 0B
0 0 0 0 0 0 0 -B
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
- - 0 0 0 0 0 0B
R/W
Prohibited
XXXXXXXXB
XXXXXXXXB
W
000096H
00009FH
XXXXXXXXB
16 bit
PPG1
(Reserved)
PACSR
1 1 1 1 1 1 1 1B
W
PPG0 control status register
Initial Value
1 1 1 1 1 1 1 1B
16 bit
PPG0
000080H
to
000095H
00009EH
Resource name
0 0 0 0 0 0 0 -B
ROM correction control register
R/W
ROM Correction
0 0 0 0 0 0 0 0B
Delayed interrupt/release
R/W
Delayed interrupt
- - - - - - - 0B
LPMCR
Low power consumption mode
R/W
0 0 0 1 1 0 0 0B
CKSCR
Clock selector
R/W
Low power
consumption
control circuit
1 1 1 1 1 1 0 0B
0000A2H
to
0000A7H
Prohibited
0000A8H
WDTC
Watchdog control
R/W
Watchdog timer
XXXXX 1 1 1B
0000A9H
TBTC
Time-base timer control register
R/W
Time-base timer
1 - - 0 0 1 0 0B
0000AAH
WTC
Watch timer control register
R/W
Watch timer
(Sub clock)
1 X0 1 1 0 0 0B
0000ABH
to
0000ADH
Prohibited
(Continued)
22
MB90800 Series
(Continued)
Read/
Write
Resource name
Initial Value
Flash control register
R/W
Flash I/F
0 0 0 X 0 0 0 0B
TMCS
Timer clock output control register
R/W
Timer clock
devide
XXXXX 0 0 0B
0000B0H
ICR00
Interrupt control register 00
R/W
0 0 0 0 0 1 1 1B
0000B1H
ICR01
Interrupt control register 01
R/W
0 0 0 0 0 1 1 1B
0000B2H
ICR02
Interrupt control register 02
R/W
0 0 0 0 0 1 1 1B
0000B3H
ICR03
Interrupt control register 03
R/W
0 0 0 0 0 1 1 1B
0000B4H
ICR04
Interrupt control register 04
R/W
0 0 0 0 0 1 1 1B
0000B5H
ICR05
Interrupt control register 05
R/W
0 0 0 0 0 1 1 1B
0000B6H
ICR06
Interrupt control register 06
R/W
0 0 0 0 0 1 1 1B
0000B7H
ICR07
Interrupt control register 07
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
0 0 0 0 0 1 1 1B
0000BAH
ICR10
Interrupt control register 10
R/W
0 0 0 0 0 1 1 1B
0000BBH
ICR11
Interrupt control register 11
R/W
0 0 0 0 0 1 1 1B
0000BCH
ICR12
Interrupt control register 12
R/W
0 0 0 0 0 1 1 1B
0000BDH
ICR13
Interrupt control register 13
R/W
0 0 0 0 0 1 1 1B
0000BEH
ICR14
Interrupt control register 14
R/W
0 0 0 0 0 1 1 1B
0000BFH
ICR15
Interrupt control register 15
R/W
0 0 0 0 0 1 1 1B
R/W
XXXXXXXXB
Address
Register
abbreviation
0000AEH
FMCS
0000AFH
Register
001FF0H
001FF1H
PADR0
Program address detection register 0
R/W
001FF2H
R/W
001FF3H
R/W
001FF4H
PADR1
Program address detection register 1
001FF5H
007900H
to
007917H
VRAM
LCD display RAM
Interrupt
controller
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
XXXXXXXXB
Address
matching
detection function
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
LCD controller/
driver
XXXXXXXXB
• Read/Write
R/W Readable and Writable
R Read only
W Write only
• Initial values
0 Initial Value is “0”.
1 Initial Value is “1”.
X Initial Value is Indeterminate.
23
MB90800 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
readiness
Interrupt vector
Number*
Interrupt control register
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
INT 9 instruction
×
#09
09H
FFFFD8H
Exceptional treatment
×
#10
0AH
FFFFD4H
DTP/External interrupt ch0
#11
0BH
FFFFD0H
ICR00
0000B0H
DTP/External interrupt ch1
#13
0DH
FFFFC8H
ICR01
0000B1H
#15
0FH
FFFFC0H
#16
10H
FFFFBCH
ICR02
0000B2H
#17
11H
FFFFB8H
#18
12H
FFFFB4H
ICR03
0000B3H
#19
13H
FFFFB0H
ICR04
0000B4H
16-Bit Reload Timer ch2
#21
15H
FFFFA8H
ICR05
0000B5H
16-Bit Reload Timer ch0
#23
17H
FFFFA0H
16-Bit Reload Timer ch1
#24
18H
FFFF9CH
ICR06
0000B6H
Input capture ch0
#25
19H
FFFF98H
Input capture ch1
#26
1AH
FFFF94H
ICR07
0000B7H
PPG timer ch0 counter-borrow
#27
1BH
FFFF90H
ICR08
0000B8H
Output compare match
#29
1DH
FFFF88H
ICR09
0000B9H
PPG timer ch1 counter-borrow
#31
1FH
FFFF80H
ICR10
0000BAH
#33
21H
FFFF78H
ICR11
0000BBH
UART0 reception end
#35
23H
FFFF70H
UART0 transmission end
#36
24H
FFFF6CH
ICR12
0000BCH
A/D converter conversion termination
#37
25H
FFFF68H
#38
26H
FFFF64H
ICR13
0000BDH
UART1 : Reception
#39
27H
FFFF60H
UART1 : Transmission
#40
28H
FFFF5CH
ICR14
0000BEH
ICR15
0000BFH
Serial I/O ch2
×
DTP/External interrupt ch2/3
Serial I/O ch3
×
16-bit free-run timer
Watch timer
Time-base timer
2
I C Interface
×
×
×
Flash memory status
×
#41
29H
FFFF58H
Delayed interrupt output module
×
#42
2AH
FFFF54H
Priority
High
Low
: Available
× : Unavailable
: Available El2OS function is provided.
: Available when a cause of interrupt sharing a same ICR is not used.
* : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector
number has the priority.
• When there are two interrupt causes in the same interrupt control register (ICR) and use of IIOS is enabled,
IIOS is started upon detection of one of the interrupt causes. As interrupts other than the start cause are
masked during IIOS start, masking one of the interrupt requests is recommended when using IIOS.
• For a resource that has two interrupt causes in the same interrupt control register (ICR), the interrupt flag is
cleared by an IIOS interrupt clear signal.
24
MB90800 Series
■ PERIPHERAL RESOURCES
1. I/O port
The I/O ports function to output data from the CPU to I/O pins via their port data register (PDR) and send signals
input to I/O pins to the CPU. In addition, the port can randomly set the direction of the input/output of the I/O pin
in bit by the port direction register (DDR).
The MB90800 series has 68 (70 ports when the subclock is not used) input/output pins. Port0 to port8 (port0 to
port9 when the subclock is not used) are input/output port.
(1) Port data register
PDR0
7
6
5
4
3
2
1
0
Initial Value
Access
Address : 000000H
P07
P06
P05
P04
P03
P02
P01
P00
Indeterminate
R/W*
PDR1
15
14
13
12
11
10
9
8
P17
P16
P15
P14
P13
P12
P11
P10
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Address : 000001H
PDR2
Address : 000002H
PDR3
Address : 000003H
PDR4
Address : 000004H
PDR5
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
15
14
13
12
11
10
9
8
P37
P36
P35
P34
P33
P32
P31
P30
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
15
14
13
12
11
10
9
8
P57
P56
P55
P54
P53
P52
P51
P50
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
PDR7
15
14
13
12
11
10
9
8
Address : 000007H
P76
P75
P74
P73
P72
P71
P70
PDR8
7
6
5
4
3
2
1
0
Address : 000008H
P84
P83
P82
P81
P80
PDR9
15
14
13
12
11
10
9
8
Address : 000009H
P91
P90
Address : 000005H
PDR6
Address : 000006H
When reading : Read the corresponding pin level.
When writing : Write into the latch for the input/output.
• Output mode
When reading : Read the value of the data register latch.
When writing : Write into the corresponding pin.
25
MB90800 Series
(2) Port direction register
DDR0
Address : 000010H
DDR1
Address : 000011H
DDR2
Address : 000012H
DDR3
Address : 000013H
DDR4
Address : 000014H
DDR5
Address : 000015H
DDR6
Address : 000016H
DDR7
Address : 000017H
DDR8
Address : 000018H
DDR9
Address : 000019H
7
6
5
4
3
2
1
0
Initial Value
Access
D07
D06
D05
D04
D03
D02
D01
D 00
00000000B
R/W
15
14
13
12
11
10
9
8
D17
D16
D15
D14
D13
D12
D11
D10
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
- 0000000B
R/W
- - - 00000B
R/W
- - - - - - 00B
R/W
7
6
5
4
3
2
1
0
D27
D26
D25
D24
D23
D22
D21
D20
15
14
13
12
11
10
9
8
D37
D36
D35
D34
D33
D32
D31
D30
7
6
5
4
3
2
1
0
D47
D46
D45
D44
D43
D42
D41
D40
15
14
13
12
11
10
9
8
D57
D56
D55
D54
D53
D52
D51
D50
7
6
5
4
3
2
1
0
D67
D66
D65
D64
D63
D62
D61
D60
15
14
13
12
11
10
9
8
D76
D75
D74
D73
D72
D71
D70
7
6
5
4
3
2
1
0
D84
D83
D82
D81
D80
15
14
13
12
11
10
9
8
D91
D90
• When each terminal functions as a port, each correspondent pin are controlled to following;
0 : Input mode
1 : Output mode This bit becomes “0” after a reset.
Note : When accessing this register by using the instruction of the read modify write system (instructions such as
bit set) is mode, the bit targeted by an instruction becomes the defined value, while the content of the output
register set with the other. Therefore, be sure to write an expected value into PDR firstly, and then set DDR
and finally change to the output when changing the input pin to the output pin is made.
26
MB90800 Series
(3) Analog Input Enable register
ADER0
Address : 00001EH
ADER1
Address : 00001FH
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
15
14
13
12
11
10
9
8
ADE11
ADE10
ADE9
ADE8
Initial Value Access
11111111B
R/W
- - - -1111B
R/W
Control each pin of Port 6 as follows.
0 : Port input/output mode.
1 : Analog input mode.This bit becomes “1” after a reset.
27
MB90800 Series
2. UART
UART is a serial I/O port for asynchronous (start-stop synchronization) communication or CLK synchronous
communications.
• With full-duplex double buffer
• Clock asynchronous (start-stop synchronization) , CLK synchronous communications (no start-bit/stop-bit)
can be used.
• Supports multi-processor mode
• Built-in dedicated baud rate generator
•
•
•
•
•
28
Asynchronous
: 120192/60096/30048/15024/781.25 K/390.625 Kbps
CLK synchronous : 25 M/12.5 M/6.25 M/3.125 M/1.5627 M/781.25 Kbps
Variable baud rate can be set by an external clock.
7-bits data length (only asynchronous normal mode) /8-bits length
Master/slave type communication function (at multiprocessor mode) : The communication between one (master) to n (slave) can be operating.
Error detection functions(parity, framing, overrun)
Transmission signal format is NRZ
MB90800 Series
(1) Register list
8 7
15
0
CDCR
SCR
SMR
SSR
SIDR (R)/SODR (W)
8 bit
8 bit
Serial mode register (SMR)
000020H
Address :
000028H
7
6
5
4
3
2
1
0
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
()
()
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
PEN
P
SBL
CL
A/D
REC
RXE
TXE
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
Initial Value
Serial control register(SCR)
000021H
Address :
000029H
Initial Value
Serial input/output register (SIDR/SODR)
000022H
Address :
00002AH
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Initial Value
Serial Data Register (SSR)
000023H
Address :
00002BH
Initial Value
Communication prescaler control register (CDCR)
000025H
Address :
00002DH
15
14
13
12
11
10
9
8
MD
URST
Reserved
DIV2
DIV1
DIV0
(R/W)
(0)
(R/W)
(0)
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Initial Value
29
MB90800 Series
(2) Block Diagram
Control signal
Special-purpose
baud-rate generator
16-bit reload timer 0
RX interrupt
(to CPU)
Clock
selection
circuit
Transmission clock
Reception clock
TX interrupt
(to CPU)
Pin
Pin
Reception control
circuit
Transmission
control circuit
Start bit
detection circuit
Transmission
start circuit
Reception bit
counter
Transmission bit
counter
Reception
parity counter
Transmission
parity counter
Pin
Receive status
decision circuit
Reception error
occurrence signal
for EI2OS (to CPU)
RX shifter
TX shifter
Reception
control
circuit
Start
transmission
SIDR
SODR
F2MC-16LX BUS
SMR
Register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
Register
PEN
P
SBL
CL
A/D
REC
REX
TXE
SSR
Register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
30
MB90800 Series
3. I2C Interface
I2C interface is the serial input/output port that support Inter IC BUS and functions as the master/slave device
on the I2C bus. MB90800 series have 1 channel of the built-in I2C interface.
It has the features of I2C interface below.
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address and general call address detection function
• Detecting transmitting direction function
• Repeat generating and detecting function of the start conditions
• Bus error detection function
• The forwarding rate can be supported to 100 Kbps.
(1) Register list
I2C status register (IBSR)
Address :00006AH
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
R
R
R
R
R
R
R
R
Initial Value
00000000B
I2C control register (IBCR)
Address :00006BH
15
14
13
12
11
10
9
8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
EN
CS4
CS3
CS2
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
I2C clock control register (ICCR)
Address :00006CH
XX0XXXXXB
I2C data register(IDAR)
Address :00006EH
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
A6
A5
A4
A3
A2
A1
A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
I2C address register (IADR)
Address :00006DH
XXXXXXXXB
31
MB90800 Series
(2) Block Diagram
ICCR
EN
I2C Enable
Machine clock
Clock divide 1
ICCR
6
5
7
8
CS4
Clock selector 1
CS3
Clock divide 2
CS2
Internal data bus
CS1
2 4 8
CS0
16
32
64
128 256
RSC
LRB
TRX
Generating shift clock
Clock selector 2
Change timing of
shift clock edge
IBSR
BB
Sync
Bus busy
Repeat start
Last Bit
Start stop Condition detection
Transfer/
reception
Error
First Byte
FBT
AL
Arbitration lost detection
IBCR
BER
SCL
BEIE
Interrupt request
INTE
IRQ
INT
End
IBCR
SCC
MSS
ACK
GCAA
Start
Master
Start stop Condition detection
ACK enable
GC-ACK enable
IDAR
IBSR
AAS
Slave
GCA
Global call
Slave address
compare
IADR
32
SDA
MB90800 Series
4. Extended I/O serial interface
The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8 bit ×
2 channel configured clock synchronization scheme. The extended I/O serial interface also has two alternatives
in data transfer called LSB first and MSB sirst.
The serial I/O interface operates in two modes:
• Internal shift clock mode : Transfer data in sync with the internal clock.
• External shift clock mode : Transfers data in sync with the clock input through an external pin (SCK) . In this
mode, transfer operation performed by the CPU instruction is also available by
operating the general-use port sharing an external pin (SCK) .
(1) Register list
Serial mode control status register(SMCS)
000060H
Address :
000064H
000061H
Address :
000065H
15
14
13
12
11
10
9
8
Initial Value
SMD2
SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
00000010B
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
7
6
5
4
3
2
1
0
MODE
BDS
SOE
SCOE
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
----0000B
Serial Data Register (SDR)
000062H
Address :
000066H
XXXXXXXX
Communication Prescaler control register (SDCR0, SDCR1)
Address :
000063H
000067H
15
14
13
12
11
10
9
8
MD
Reserved
DIV2
DIV1
DIV0
R/W
R/W
R/W
R/W
R/W
0---0000
33
MB90800 Series
(2) Block Diagram
Internal data bus
Initial Value
(LSB fast) D7 to D0
Transfer direction selection
(MSB fast) D0 to D7
SI2, SI3
Read
Write
SDR (Serial Data Register)
SO2, SO3
SC2, SC3
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
34
SOE SCOE
MB90800 Series
5. 8/10-bit A/D converter
A/D converter converts an analog input voltage into digital value. The feature of A/D converter is shown as follows.
• conversion time : 3.1 µs minimum per 1 channel
(78 machine cycle/at machine clock 25 MHz/including the sampling time)
• Sampling time : 2.0 µs minimum per 1channel
(50 machine cycle/at machine clock 25 MHz)
• Uses RC-type successive approximation conversion method with a sample & hold circuit
• 8-bit resolution or 10-bit resolution can be select.
• 12 channel program-selectable analog inputs.
Single conversion mode
: Convert 1 specified channel
Scan conversion mode
: Continuous plural channels (maximum 12 channels can be programmed) are
converted.
Continuous conversion mode : Selected channel converted continuously.
Stop conversion time
: Perform conversion for one channel, then wait for the next activation trigger
(synchronizes the conversion start timing)
2
• EI OS can be activated by outputting the interrupt request when the A/D conversion completes.
• If the A/D conversion is performed under the condition of the interrupt enable, the converting data will be
protected.
• Selectable conversion activation trigger : Software, or reload timer (rising edge)
(1) Register list
ADCS1, ADCS0 (Control status register)
ADCS0
7
6
5
Address : 000034H MD1
MD0
4
3
2
1
0
ADCS1
bit
Address : 000035H
0
R/W
0
R/W
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
15
14
13
12
11
10
9
8
S10
ST1
ST0
CT1
CT0
D9
D8
0
W
0
W
1
W
0
W
1
W
X
R
X
R
ADCR1, ADCR0 (data register)
ADCR0
bit
7
Address : 000036H
D7
ADCR1
bit
Address : 000037H
←Initial Value
←bit
←Initial Value
←bit
←Initial Value
←bit
←Initial Value
←bit
35
MB90800 Series
(2) Block Diagram
AVCC
AVR
MP
AVSS
D/A converter
Input
circuit
Sequential compare
register
Comparator
Data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Sample & hold circuit
Data register
Decoder
ADCR0, ADCR1
A/D channel set register
A/D Control register 0
A/D Control register 1
ADCS0, ADCS1,
ADMR
Timer start-up
16-Bit Reload Timer
Operation clock
φ
36
Prescaler
MB90800 Series
6. 16 bits PPG
The PPG timer consists of the prescaler, one 16-bit down-counter, one 16-bit data register with a cycle setting
buffer, a 16-bit compare register with a duty setting buffer, and the pin control unit.
The PPG timer can output pulses synchronized to the software trigger.
The period and duty of the output pulse can be changed freely by updating two 16-bit register values.
• PWM function
The PPG timer can output pulses programmably by updating the values of the registers described above in
synchronization to the trigger.
Can also be used as a D/A converter by an external circuit.
• Single shot function
By detecting an edge of the trigger input, a single pulse can be output.
• 16-bit down counter
The counter operation clock comes from eight kinds optional. There are eight kinds of internal clocks.
(φ, φ2, φ4, φ8, φ16, φ32, φ64, φ128) φ : machine clock
The counter is initialized to " FFFFH " at a reset or counter borrow.
• Interrupt request
The PPG timer generates an interrupt request when :
Timer start-up/counter borrow occurs (cycle match) /duty match occurs/counter borrow occurs (cycle match) ,
or duty match occurs.
37
MB90800 Series
(1) Register list
PCNTH (PCNTH0/1 Control Status register)
000077H
00007FH
15
14
13
12
11
10
9
8
CNTE
STGR
MDSE
RTRG
CSK2
CSK1
CSK0
PGMS
(R/W)
(0)
( R/W )
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
( R/W )
(0)
( R/W )
(0)
( R/W )
(X)
Read/Write
Initial Value
PCNTL (PCNTL0/1 Control Status register)
000076H
00007EH
7
6
5
4
3
2
1
0
IREN
IRQF
IRS1
IRS0
POEN
OSEL
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/Write
Initial Value
PDCRH (PDCRH0/1 PPG Down Counter Register)
000071H
000079H
15
14
13
12
11
10
9
8
DC15
DC14
DC13
DC12
DC11
DC10
DC09
DC08
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
Read/Write
Initial Value
PDCRL (PDCRL0/1 PPG Down Counter Register)
000070H
000078H
7
6
5
4
3
2
1
0
DC07
DC06
DC05
DC04
DC03
DC02
DC01
DC00
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
Read/Write
Initial Value
Read/Write
Initial Value
PCSRH (PCSRH0/1 PPG cycle set register)
000073H
00007BH
15
14
13
12
11
10
9
8
CS15
CS14
CS13
CS12
CS11
CS10
CS09
CS08
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
PCSRL (PCSRH0/1 PPG cycle set register)
000072H
00007AH
7
6
5
4
3
2
1
0
CS07
CS06
CS05
CS04
CS03
CS02
CS01
CS00
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
Read/Write
Initial Value
PDUTH (PDUTH0/1 PPG duty set register)
000075H
00007DH
15
14
13
12
11
10
9
8
DU15
DU14
DU13
DU12
DU11
DU10
DU09
DU08
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
Read/Write
Initial Value
PDUTL (PDUTL0/1 PPG duty set register)
000074H
00007CH
38
7
6
5
4
3
2
1
0
DU07
DU06
DU05
DU04
DU03
DU02
DU01
DU00
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
Read/Write
Initial Value
MB90800 Series
(2) Block Diagram
・16-bit G ch0/1 block diagram
Prescaler
1/1
PCSR
1/2
PDUT
1/4
1/8
1/16
CK
1/32
Load
CMP
PCNT
16-bit down counter
1/64
1/128
Start
Borrow
PPG mask
Machine clock φ
S
PPG output
Q
R
Reverse bit
Enable
Interrupt
select
Interrupt
Soft trigger
39
MB90800 Series
7. Delay interrupt generator module
The delayed interrupt generation module outputs an interrupt request for task swiching. When the delayed
interrupt generation module is used, software is allowed to output and clear task switching interrupts for the
MB90800 Series CPU.
(1) Register list
Delayed Interrupt/release register(DIRR)
DIRR
15
14
Address : 00009FH
13
12
11
10
9
8
R0
R/W
(2) Block diagram
F2MC-16LX bus
Delay interruption factor generation/
release decoder
Factor latch
40
Initial Value
- - - - - - - 0B
MB90800 Series
8. DTP/External interrupt
DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external
interrupt input terminal, and outputs the interrupt request.
(1) Register list
Interrupt/DTP enable register (ENIR : Enable Interrupt Request Register)
ENIR
7
6
5
4
3
2
1
Address : 000030H
EN3
EN2
EN1
R/W
R/W
R/W
EN0
R/W
Interrupt/DTP source register (EIRR : External Interrupt Request Register)
EIRR
15
14
13
12
11
10
9
Address : 000031H
ER3
ER2
ER1
0
Initial Value
- - - - 0000B
R/W
8
ER0
R/W
R/W
R/W
Initial Value
- - - - XXXXB
Request level setting register (ELVR : External Level Register)
Address : 000032H
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
00000000B
(2) Block diagram
F2MC-16LX bus
4
4
4
8
Interrupt/DTP enable register
Gate
Source F/F
Edge detection circuit
4
Request input
Interrupt/DTP source register
Request level setting register
41
MB90800 Series
9. 16-bit input/output timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare and two input capture modules.
This function enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse
widths and external clock frequencies to be measured.
・Register list
・16-bit free-run timer
15
0
00003B/3AH
CPCLR
00003D/3CH
TCDT
00003F/3EH
TCCS
Compare clear register
Timer counter data register
Timer counter
control status register
・16-bit Output Compare
15
0
00004AH/00004BH/
00004CH/00004DH
Compare register
OCCP0 ∼ OCCP1
00004FH/00004EH
OCSH
Control status register
OCSL
・16-bit Input Capture
15
000044H/000045H/
000046H/000047H
000048H
42
0
Data register
IPCP0, IPCP1
ICS01
Control status register
MB90800 Series
・Block diagram
Control logic
Interrupt
16-bit free-run timer
To each
block
16-bit timer
Bus
Clear
Output
compare 0
Compare register 0
TQ
OTE0
Output
compare 1
Compare register 1
TQ
OTE1
Input capture 0
Capture register 0
Edge select
IC0
Capture register 1
Edge select
IC1
Input capture 1
43
MB90800 Series
(1) 16-bit free-run timer
The 16-bit free-run timer consists of a 16-bit up-down counter and control status register.
Counter value of 16-bit free-run timer is available as base timer for input capture and output compare.
• Clock for the counter operation can be selected from eight types.
• The counter overflow interruption can be generated.
• Setting the mode enables initialization of the counter through compare-match operation with the value of the
compare clear register in the output compare.
・Register list
Compare clear register (CPCLR)
00003BH
00003AH
15
14
13
12
11
10
9
8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Timer counter data register (TCDT)
00003DH
00003CH
15
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T09
T08
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
12
11
10
9
8
Initial Value
00000000B
Initial Value
00000000B
Timer counter control/status register (TCCS)
15
00003FH
00003EH
44
14
13
ECKE
MSI2
MSI1
MSI0
ICLR
ICRE
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
CLK0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial Value
0--00000B
Initial Value
00000000B
MB90800 Series
・Block diagram
φ
Interrupt request
IVF
Divider
IVFE STOP MODE SCLR CLK2 CLK1 CLK0
Bus
Clock
16-bit free-run timer
Count value output T15 to T00
16-bit compare clear register
Compare cir-
MSI2 ∼ MSI0
ICLR
ICRE
Interrupt request
45
MB90800 Series
(2) Output compare
The output compare consists of 16-bit compare registers, compare output pin part and a control register. It can
reverse the output level for the pin and at the same time, generate an interrupt when the 16-bit free-run timer
value matches a value set in one of the 16-bit compare registers of this module.
• It has a total of six compare registers that can operate independently. In addition, the output can be set to be
controlled by using two compare registers.
• An interrupt can be set by a comparing match.
・Register list
Compare register (OCCP0, OCCP1)
00004BH
00004DH
00004AH
00004CH
15
14
13
12
11
10
9
8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
C00
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
15
14
13
12
11
10
9
8
CMOD
OTE1
OTE0
OTD1
OTD0
()
()
()
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
7
6
5
4
3
2
1
0
IOP1
IOP0
IOE1
IOE0
CST1
CST0
(R/W)
(R/W)
(R/W)
(R/W)
()
()
(R/W)
(R/W)
Initial Value
00000000B
Initial Value
00000000B
Control register (OCSH)
00004FH
Initial Value
---00000B
Control register (OCSL)
00004EH
46
Initial Value
0000--00B
MB90800 Series
・Block diagram
16-bit timer counter value (T15 to T00)
Compare control
TQ
OTE0
Compare register 0
CMOD
Bus
16-bit timer counter value (T15 to T00)
Compare control
TQ
OTE1
Compare register 1
ICP1
Control logic
Each control blocks
ICP0
ICE0
ICE0
Interrupt
#29
#29
47
MB90800 Series
(3) Input capture
This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.
The input capture consists of input capture and control registers. Each input capture has its corresponding
external input pin.
• The detection edge of an external input can be selected from among three types. Rising edge/falling edge/
both edges.
• It can generate an interrupt when it detects the valid edge of the external input.
・Register list
Input capture data register (IPCP0, IPCP1)
000045H
000047H
000044H
000046H
15
14
13
12
11
10
9
8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial Value
XXXXXXXXB
Initial Value
XXXXXXXXB
Control status register (ICS01)
000048H
48
Initial Value
00000000B
MB90800 Series
・Block diagram
Capture data register 0
Edge detection
16-bit timer counter value (T15 to T00)
IC0
Bus
EG11 EG10 EG01 EG00
Capture data register 1
ICP1
Edge detection
ICP0
ICE1
IC1
ICE0
Interrupt #25
Interrupt #25
49
MB90800 Series
10. 16-bit reload timer
The 16-bit reload timer provides two functions either one which can be selected, the internal clock the performs
the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count
down by detecting the arbitration. This timer defines an underflow as a transition of the count value from 0000H
to FFFFH. Therefore, when the equation (counted value = reload register setting value+1) holds, an underflow
occurs. Either mode can be selected for the count operation from the reload mode which repeats the count by
reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at
the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.
(1) Register list
• TMCSRTimer control status register
Timer control status register (upper) (TMCSR)
000051H
000055H
000059H
15
14
13
12
11
10
9
8
CSL1
CSL0
MOD2
MOD1
()
()
()
()
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/Write
Initial Value
Timer control status register (lower) (TMCSR)
000050H
000054H
000058H
7
6
5
4
3
2
1
0
MOD0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/Write
Initial Value
• 16-bit timer register/16-bit reload register TMR/TMRLR (upper)
000053H
000057H
00005BH
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Read/Write
Initial Value
TMR/TMRLR (low)
000052H
000056H
00005AH
50
Read/Write
Initial Value
MB90800 Series
(2) Block diagram
Internal data bus
TMRLR
16-bit reload register
Reload signal
TMR
16-bit timer register
(down counter)
Reload control
circuit
UF
CLK
Count clock generation circuit
Machine
clock φ
3
Prescaler
Gate
input
Valid clock
identification circuit
Clear
Wait signal
CLK
Output signal
generation circuit
Pin
Input control
circuit
Clock
selector
Reverse
Output signal
generation circuit
EN
External clock
OUTL
Select
function
3
Select signal
Pin
2
RELD
Operation
control circuit
OUTE
Timer control status register (TMCSR)
51
MB90800 Series
11. Watch timer
The watch timer is a 15-bit timer using the subclock. It can generate interval interrupts. The watch timer can also
be used as the clock source of the watchdog timer by setting so.
(1) Register list
Watch timer control register (WTC)
0000AAH
7
6
5
4
3
2
1
0
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
(R/W)
(1)
(R)
(X)
(R/W)
(0)
(R/W)
(1)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Initial Value
(2) Block diagram
Watch timer control register (WTC)
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
Clear
28
29
Sub clock
Watch counter
210
211
Interval
selector
Interrupt
generation
circuit
Watch timer
interrupt
212
213
210 213 214 215
214
To watchdog timer
52
MB90800 Series
12. Watchdog timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer or watch timer and resets
the CPU when the counter is not cleared for a preset period of time.
(1) Register list
Watchdog timer control register (WDTC)
0000A8H
7
6
5
4
3
2
1
0
PONR
WRST
ERST
SRST
WTE
WT1
WT0
(R)
(X)
()
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
(W)
(1)
Initial Value
(2) Block diagram
Watchdog timer control register (WDTC)
PONR
―
WRST ERST SRST WTE
WT1
WT0
WDCS bit of watch timer
control register (WTO)
SCM bit of clock selection
register (CKSCR)
2
Watch mode start
Timebase timer mode start
Sleep mode start
Hold status start Watchdog timer
CLR and start-up
Counter
clear control
circuit
Count
clock
selector
Stop mode start
2-bit
counter
CLR
Watchdog reset
generation
circuit
CLR
Internal
reset
generation
circuit
4
4
Clear
Time base counter
Dividing HCLK by 2
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
SCLK
× 21 × 2 2
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK: Oscillation clock
SCLK: Sub clock
53
MB90800 Series
13. Time-base timer
The time-base timer has a function that enables a selection of four interval times using 18-bit free-run counter
(time-base counter) with synchronizing to the internal count clock (two division of original oscillation). Furthermore, the function of timer output of oscillation stabilization wait or function supplying operation clocks for
watchdog timer are provided.
(1) Register list
Timer base timer control register (TBTC)
0000A9H
15
14
13
12
11
10
9
8
Reserved
TBIE
TBOF
TBR
TBC1
TBC0
(R/W)
(1)
()
()
()
()
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
(2) Block diagram
To PPG timer
To watchdog timer
Time-base timer counter
Dividing HCLK by 2
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
Power-on reset
Stop mode start
Hold status start
CKSCR : MCS = 0*1
CKSCR : SCS = 0→1*2
Counter
clear
control
circuit
OF
OF
OF
OF
To clock controller
Oscillation stabilizing
Wait time selector
Interval timer selector
TBOF set
TBOF clear
Time-base timer control register (TBTC) RESV
TBIE TBOF TBR TBC1 TBC0
Time-base timer interrupt signal
OF
HCLK
*1
*2
54
: Unused
: Overflow
: Oscillation clock
: The machine clock is switched from main/sub clock to PLL clock.
: The machine clock is switched from sub clock to main clock.
MB90800 Series
14. Clock
The clock generator controls operation of the internal clock which is the operation clock for the CPU and peripheral
devices. This internal clock is referred to as machine clock and its one cycle as machine cycle. In addition, the
clock generated by original oscillation is referred to as oscillation clock and that by internal PLL oscillation as
PLL clock.
(1) Register list
Clock selection register (CKSCR)
0000A1H
15
14
13
12
11
10
9
8
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
(R)
(1)
(R)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(0)
( R/W )
(0)
Initial Value
55
MB90800 Series
(2) Block diagram
Standby control circuit
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 Reserved
Pin High-Z
control circuit
RST
Pin
Pin High-Z control
Internal reset
generation circuit
CPU intermittent
operation selector
Intermittent cycle selection
CPU clock
CPU clock
control circuit
Stop, sleep signal
Standby control
circuit
Release
interrupting
Stop signal
Peripheral clock
control circuit
Machine clock
Clock
selector
Oscillation
stabilization
wait time
selector
2
Dividing SCLK
by 4
2
PLL multiplying
circuit
Sub clock
generation
circuit
Pin
X1A
Pin
Peripheral clock
Oscillation stabilization wait
Clock generation block
X0A
Internal reset
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
System
clock
generation
circuit
Dividing
by 2
HCLK
X0
Pin
X1
Pin
Dividing
by
1024
Dividing
by 2
Dividing
by 4
Dividing
by 4
Dividing
by 4
MCLK
Time-base timer
To watchdog timer
HCLK : Oscillation clock
MCLK : Main clock
SCLK : Sub clock
56
Dividing
by 2
MB90800 Series
(3) Clock supply map
Clock generation circuit
Timer clock divider
X0
X1
Watch timer
Oscillation
circuit
Watchdog timer
Internal resources
X0A
X1A
Selector
Oscillation
circuit
Time-base timer
1
2
3
LCD controller
16-Bit Reload Timer
8/10-bit A/D converter
Serial I/O
Free-run timer
Input capture
4
PLL multiplying circuit
PCLK
CPU (F2MC-16LX)
2 division circuit
Selector
HCLK
MCLK
2 division circuit
HCLK
MCLK
PCLK
SCLK
ROM/RAM (memory)
SCLK
: Oscillation clock frequency
: Main clock frequency
: PLL clock frequency
: Sub clock frequency
57
MB90800 Series
15. Low power consumption mode
The MB90800 Series have the following CPU operation modes by selecting the operation clock and operating
the control of the clock.
• Clock mode
(PLL clock mode, main clock mode and sub clock mode)
• CPU intermittent operation mode
(PLL clock intermittent operation mode, main clock intermittent operation mode and subclock intermittent
operation mode)
• Standby mode
(Sleep mode, time base timer mode, stop mode and watch mode)
(1) Register list
Low power consumption mode control register (LPMCR)
0000A0H
58
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
Reserved
(W)
(0)
(W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Initial Value
MB90800 Series
(2) Block diagram
Standby control circuit
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 Reserved
Pin High-Z
control circuit
RST
Pin High-Z control
Internal reset
generation
circuit
Pin
CPU intermittent
operation selector
Internal reset
Intermittent cycle selection
CPU clock
control circuit
Standby control
circuit
Release of
interrupt
CPU clock
Stop, sleep signal
Stop signal
Peripheral
clock control
Machine clock
Release of oscillation stabilization wait
Clock generation block
Clock
selector
Oscillation
stabilization
wait time
selector
2
Dividing
by 4
SCLK
X0A
Pin
X1A
Pin
2
PLL multiplying
circuit
Sub
clock
generation
circuit
Peripheral clock
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
System
clock
generation
circuit
Dividing
by 2
HCLK
X0
Pin
X1
Pin
Dividing
by 1024
Dividing
by 2
Dividing
by 4
Dividing
by 4
Dividing
by 4
Dividing
by 2
MCLK
Time-base timer
To watchdog timer
HCLK
MCLK
SCLK
: Oscillation clock
: Main clock
: Sub clock
59
MB90800 Series
(3) Figure of status transition
External reset, watchdog timer reset, software reset,
Power supply
Reset
SCS = 0
Power-on reset
End of oscillation
stabilization wait
SCS = 1
MCS = 0
Main clock mode
SLP = 1
Interrupt
Interrupt
Timebase
timer mode
STP = 1
End of oscillation
stabilization wait
Main clock Oscillation
stabilization wait
60
SLP = 1
Interrupt
PLL sleep mode
TMD = 0
Interrupt
Timebase
timer mode
STP = 1
Main stop mode
Interrupt
SCS = 0
SCS = 1
MCS = 1
Main sleep mode
TMD = 0
PLL clock mode
SLP = 1
Interrupt
Sub sleep mode
TMD = 0
Interrupt
Watch mode
STP = 1
PLL stop mode
Interrupt
Sub clock mode
End of oscillation
stabilization wait
Main clock Oscillation
stabilization wait
Sub stop mode
Interrupt
End of oscillation
stabilization wait
Sub clock Oscillation
stabilization wait
MB90800 Series
16. Timer clock output
The timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the
set division clock. Selectable from 32/64/128/256 division of the oscillation clock.
The timer clock output circuit is inactive in reset or stop mode. Normally, it is active in run, sleep, or pseudotimer mode.
PLL_Run
Main_Run
Pseudo
clock
Sleep
Operation status
STOP
Reset
×
×
Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output.
For detail of the timebase timer’s clear condition, see the section of timebase timer in Hardware Manual.
(1) Register list
bit
Address : 0000AFH
15
14
13
12
11
10
9
8
TEN
TS1
TS0
R/W
R/W
R/W
Initial Value
XXXXX000B
- : Unused
(2) Block diagram
Timer clock selection circuit
X0
X1
Oscillation
circuit
Selector
Timer clock output
Time-base timer
Dividing by 2
61
MB90800 Series
17. ROM mirrorring function selection module
ROM mirrorring function selection module can select that FF bank where ROM is located look into 00 bank
among the settings of the register.
(1) Register list
bit
Address : 00006FH
15
14
13
12
11
10
9
8
―
MI
Initial Value
XXXXXXX1B
R/W
- : Unused
(2) Block diagram
F2MC-16LX bus
ROM mirroring function selection
Address area
Address
Data
FF bank
00 bank
ROM
Note : Do not access to this register in the middle of the operation of the address 008000H to 00FFFFH.
62
MB90800 Series
18. Interrupt controller
Interrupt control register is in the interrupt controller. The register corresponds to all I/O of interrupt function. The
register has following functions;
• Setting of Interrupt level at correspondent peripheral circuit.
(1) Register list (at writing)
Interrupt control register
Address :
ICR01
ICR03
ICR05
ICR07
ICR09
ICR11
ICR13
ICR15
0000B1H
0000B3H
0000B5H
0000B7H
0000B9H
0000BBH
0000BDH
0000BFH
Read/Write →
Initial Value →
Bit 15
14
13
12
ICS3
ICS2
ICS1
ICS0
W
(0)
W
(0)
W
(0)
W
(0)
11
10
9
8
ISE
IL2
IL1
IL0
R/W
(0)
R/W
(1)
R/W
(1)
R/W
(1)
ICR01, 03,
05, 07, 09, 11,
13, 15
Interrupt control register
Address :
ICR00
ICR02
ICR04
ICR06
ICR08
ICR10
ICR12
ICR14
0000B0H
0000B2H
0000B4H
0000B6H
0000B8H
0000BAH
0000BCH
0000BEH
Read/Write →
Initial Value →
Bit
7
6
5
4
3
2
1
0
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
W
(0)
W
(0)
W
(0)
W
(0)
R/W
(0)
R/W
(1)
R/W
(1)
R/W
(1)
ICR00, 02,
04, 06, 08,
10, 12, 14
63
MB90800 Series
(2)Register list (at reading)
Interrupt control register
Address :
ICR01
ICR03
ICR05
ICR07
ICR09
ICR11
ICR13
ICR15
0000B1H
0000B3H
Bit 15
0000B5H
0000B7H
0000B9H
0000BBH
0000BDH
0000BFH
Read/Write →
()
Initial Value →
14
13
12
11
10
9
ICR01,
03, 05, 07,
09, 11, 13,
15
8
S1
S0
ISE
IL2
IL1
IL0
()
R
(0)
R
(0)
R/W
(0)
R/W
(1)
R/W
(1)
R/W
(1)
Interrupt control register
Address :
ICR00
ICR02
ICR04
ICR06
ICR08
ICR10
ICR12
ICR14
0000B0H
0000B2H
0000B4H
0000B6H
0000B8H
0000BAH
0000BCH
0000BEH
Read/Write →
Initial Value →
Bit
7
6
5
4
3
2
1
0
S1
S0
ISE
IL2
IL1
IL0
()
()
R
(0)
R
(0)
R/W
(0)
R/W
(1)
R/W
(1)
R/W
(1)
Note : Do not access using the read modify write instruction because it causes a malfunction.
64
ICR00,
02, 04, 06,
08, 10, 12,
14
MB90800 Series
(3) Block diagram
F2MC-16LX bus
3
IL2
IL1
IL0
Interrupt request
(Peripheral resources)
3
32
Judging the priority
of interrupt
3
(CPU)
Interrupt level
65
MB90800 Series
19. LCD controller/driver
The LCD controller/driver contains 24 × 8-bit display data memory and controls the LCD display with four common
output lines and 48 segment output lines. Three duty outputs can be selected to directly drive the LCD panel
(liquid crystal display).
• Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be connected.
• A maximum of four common output lines (COM0 to COM3) and 48 segment output lines (SEG0 to SEG47)
are available.
• Contains 24-byte display data memory (display RAM).
• For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).
• The LCD can directly be driven.
Bias
1/2 duty
1/3 duty
1/4 duty
×
×
1/2 bias
×
1/3 bias
：Recommended mode
× ：Disable
(1) Register list
・LCR (LCD control register)
LCD control register (higher) (LCRH)
00005DH
15
14
13
12
11
10
9
8
SS4
VS0
CS1
CS0
SS3
SS2
SS1
SS0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/Write
Initial Value
LCD control register (lower) (LCRL)
00005CH
7
6
5
4
3
2
1
0
CSS
LCEN
VSEL
BK
MS1
MS0
FP1
FP0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/Write
Initial Value
・LCDC range register (LCRR)
7
6
Reserved Reserved
00005EH
66
(R/W)
(0)
(R/W)
(0)
5
4
3
2
1
0
SE4
SE3
SE2
SE1
SE0
LCR
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/Write
Initial Value
MB90800 Series
(2) Block diagram
LCDC range register
(LCRR)
V0
LCD Control register
(LCRL)
Main
Clock
V2
V3
Division resistor
4
Prescaler
Internal data bus
V1
Timing
controller
Common
driver
Sub clock
(32 kHz)
Circuit
of
making
to
exchange
48
Segment
driver
Display RAM
24 × 8 bit
COM0
COM1
COM2
COM3
SEG00
SEG01
SEG02
SEG03
SEG04
∼
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
LCD Control register
(LCRH)
Controller
Driver
67
MB90800 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
AVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ AVCC*1
VSS − 0.3
VSS + 4.0
V
*2
VSS − 0.3
VSS + 6.0
V
N-ch O.D
(5 V withstand voltageI/O)
*2
Input voltage
VI
Output voltage
VO
VSS − 0.3
VSS + 4.0
V
IOL11
10
mA
Other than P74, P75,
P40 to P47*3
IOL12
30
mA
P74, P75, P40 to P47
(Heavy-current output port) *3
IOLAV1
3
mA
Other than P74, P75,
P40 to P47*4
IOLAV2
15
mA
P74, P75, P40 to P47
(Heavy-current output port) *4
“L” level maximum total output current
ΣIOL
120
mA
“L” level average total output current
ΣIOLAV
60
mA
*5
IOH11
− 10
mA
Other than P74, P75,
P40 to P47*3
IOH12
− 12
mA
P40 to P47
(Heavy-current output port) *3
“H” level average output current
IOHAV
−3
mA
*4
“H” level maximum total output
current
ΣIOH
− 120
mA
ΣIOHAV
− 60
mA
Power consumption
Pd
351
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“L” level maximum output current
“L” level average output current
“H” level maximum output current
“H” level average total output current
Storage temperature
*5
The Absolute Maximum Ratings is based on VSS = AVSS = 0.0 V.
*1 : AVCC should not be exceeding VCC at power-on etc.
*2 : VI, VO, should not exceed Vcc + 0.3 V.
*3 : A peak value of an applicable one pin is specified as a maximum output current.
*4 : An average current value of an applicable one pin within 100 ms is specified as an average output current.
(Average value is found by multiplying operating current by operating rate.)
*5 : An average current value of all pins within 100 ms is specified as an average total output current.
(Average value is found by multiplying operating current by operating rate.)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
68
MB90800 Series
2. Recommended Operating Conditions
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min
Max
2.7
3.6
V
At normal operating
1.8
3.6
V
Stop operation state maintenance
VIH
0.7 VCC
VCC + 0.3
V
CMOS input pin
VIHS
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input pin
(Resisting pressure of 5 V is VCC = 5.0 V)
VIHM
VCC − 0.3
VCC + 0.3
V
MD pin input
VIL
VSS − 0.3
0.3 VCC
V
CMOS input pin
VILS
VSS − 0.3
0.2 VCC
V
CMOS hysteresis input pin
VILM
VSS − 0.3
VSS + 0.3
V
MD pin input
TA
− 40
+ 85
°C
VCC
The Recommended Operating Conditions is based on VSS = AVSS = 0.0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
69
MB90800 Series
3. DC Characteristics
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C)
Symbol
Pin name
Conditions
VOH
Output pins
other than
P40 to P47,
P74, P75
VOH1
Value
Unit
Remarks
Min
Typ
Max
IOH = − 4.0 mA
VCC − 0.5
Vcc
V
P40 to P47
IOH = − 8.0 mA
VCC − 0.5
Vcc
V
VOL
Output pins
other than
P40 to P47,
P74, P75
IOL = 4.0 mA
Vss
Vss + 0.4
V
VOL1
P40 to P47
IOL = 15.0 mA
Vss
Vss + 0.6
V
Heavy-current
output port
VOL2
P74, P75
IOL = 15.0 mA
0.5
Vss + 0.8
V
Open-drain pin
Open-drain output
application voltage
VD1
P74, P75
Vss − 0.3
Vss + 5.5
V
Input leak current
IIL
All output
pin
VCC = 3.3 V,
VSS < VI < VCC
− 10
10
µA
RST
Vcc = 3.3 V,
TA = + 25 °C
25
50
100
kΩ
RDOWN MD2
Vcc = 3.3 V,
TA = + 25 °C
25
50
100
kΩ
0.1
10
µA
“H” level output
voltage
“L” level output
voltage
Pull-up resistor
Pull-down resistor
Open drain output
current
RUP
Ileak
P74, P75
Heavy-current
output port
Except FLASH
products
The DC Characteristics is based on VSS = AVSS = 0.0 V.
(Continued)
70
MB90800 Series
(VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C)
Parameter
Symbol
Pin name
Unit
Remarks
Typ
Max
VCC = 3.3 V,
Internal frequency 25 MHz
At normal operating
48
60
mA
VCC = 3.3 V,
Internal frequency 25 MHz
At Flash writing
60
75
mA
FLASH
products
VCC = 3.3 V,
Internal frequency 25 MHz
At Flash erasing
60
75
mA
FLASH
products
ICCS
VCC = 3.3 V,
Internal frequency 25 MHz
at sleep mode
22.5
30
mA
ICCTS
VCC = 3.3 V,
Internal frequency 3 MHz
at timer mode
0.75
7
mA
15
140
µA
MASK
products
0.5
0.9
mA
FLASH
products
ICCLS
VCC = 3.3 V,
Internal frequency 8 kHz
at subclock sleep operation,
(TA = + 25 °C)
23
40
µA
ICCT
VCC = 3.3 V,
Internal frequency 8 kHz
at watch mode
(TA = + 25 °C)
1.8
40
µA
ICCH
At Stop mode,
(TA = + 25 °C)
0.8
40
µA
VCC − V3
At LCR = 0 setting
100
200
400
VCC − V3
At LCR = 1 setting
12.5
25
50
V0 − V1,
V1 − V2,
V2 − V3
At LCR = 0 setting
50
100
200
V0 − V1,
V1 − V2,
V2 − V3
At LCR = 1 setting
6.25
12.5
25
2.5
kΩ
15
kΩ
VCC
VCC = 3.3 V,
Internal frequency 8 kHz
at subclock operation,
(TA = + 25 °C)
ICCL
LCD division
resistance
Value
Min
ICC
Power
supply
current
Conditions
RLCD
COM0 to
COM0 to COM3
RVCOM
COM3
output impedance
SEG00 to SEG47
SEG00 to
RVSEG
output impedance
SEG47
kΩ
*
V1 to V3 = 3.3 V
The DC Characteristics is based on VSS = AVSS = 0.0 V.
(Continued)
71
MB90800 Series
(Continued)
(VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C)
Parameter
Symbol
Pin name
Conditions
V0 to V3,
LCD leak current ILCDC COM0 to COM3,
SEG00 to SEG47
Value
Min
Typ
Max
−5
5
Unit
Remarks
µA
The DC Characteristics is based on VSS = AVSS = 0.0 V.
* : LCD internal diveded resistor can be select two type resistor by LCR (internal diveded resistor selecting bit) of
LCRR (LCDC range register) .
72
MB90800 Series
4. AC Characteristics
(1) Clock timing
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Sym
CondiPin name
bol
tions
fCH
Clock frequency
Clock cycle time
fCH
X0, X1
X0, X1
Value
Unit
Remarks
Min
Typ
Max
3
16
3
25
At external clock*
4.5
25
Multiply by 1
4
12.5
MHz Multiply by 2
4
8.33
Multiply by 3
4
6.25
Multiply by 4
32.768
MHz
External crystal
oscillation
fCL
X0A, X1A
tHCYL
X0, X1
40
333
ns
30.5
µs
5
ns
Set Duty ratio 50% ± 3%
tLCYL X0A, X1A
kHz
PWH
PWL
X0
PWLH
PWLL
X0A
15.2
µs
Set duty ratio at 30% to
70% as a guideline.
Input clock rise time and
fall time
tcr
tcf
X0
5
ns
At external clock
Internal operating clock
frequency
fCP
1.5
25
MHz
fCP1
8.192
kHz When sub clock is used
tCP
40
666
ns
When main clock is
used
tCP1
122.1
µs
When sub clock is used
Input clock pulse width
Internal operating clock
cycle time
When main clock is
used
The Clock timing is based on VSS = AVSS = 0.0 V.
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned
in “Base oscillator frequency vs. Internal operating clock frequency”.
• X0, X1 clock timing
tC
0.8 VCC
0.2 VCC
PWH
PWL
tcr
tcf
• X0A, X1A clock timing
tCL
0.8 VCC
0.2 VCC
PWLH
PWLL
tcf
tcr
73
MB90800 Series
PLL operation guarantee range
Relation between internal operation clock frequency and power supply voltage
PLL operation guarantee range
Power voltage V CC (V)
3.6
3.0
2.7
Normal operation
assurance range
1.5
4.5
16
25
Internal clock fCP (MHz)
Relation between oscillation frequency and internal operating clock frequency
Multiply by 4 Multiply by 3
Internal clock fCP (MHz)
25
Multiply by 1
Multiply by 2
16
12
External clock
8
6
4.5
4
3
4.5
4
6
8
12
16
25
Original oscillation clock fCH (MHz)
Rating values of alternating current is defined by the measurement reference voltage values shown below :
74
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
MB90800 Series
(2) Reset input timing
Parameter
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Pin name
Value
Conditions
Min
500
Reset input time
tRSTL
RST
Max
Unit
ns
At normal operating,
at time base timer mode,
at main leep mode,
at PLL sleep mode
µs
At stop mode,
at sub clock mode,
at sub sleep mode,
at watch mode
Oscillation time
of oscillator*+
500 ns
Remarks
The Reset input timing is based on VSS = AVSS = 0.0 V.
* : Oscillation time of oscillator is time until oscillation reaches 90% of amplitude. It takes several milliseconds to
several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds
on a FAR/ceramic oscillator, and 0 milliseconds on an external clock.
• In normal operating, time base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, sub clock mode, sub sleep mode and watch mode
tRSTL
RST
0.2 VCC
X0
Internal operating
clock
0.2 VCC
90% of
amplitude
Oscillation time
of oscillator
500 ns
Wait time for stabilization oscillator
Execute instruction
Internal reset
75
MB90800 Series
(3) Power-on reset
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Symbol Pin name
Power supply rising time
tR
VCC
Power supply shutdown
time
tOFF
VCC
Value
Conditions
Unit
Remarks
Min
Max
30
ms
At normal operating
1
ms
For repeated operation
The Power-on reset is based on VSS = AVSS = 0.0 V.
Notes : • VCC should be set under 0.2 V before power-on rising up.
• These value are for power-on reset.
• In the device, there are internal registers which is initialized only by a power-on reset. If these initialization
is executing, power-on prosedure must be obeyed by these value.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Sudden change of power supply voltage may activate the power-on reset function. When changing
power supply voltages during operation, raise the power smoothly by suppressing variation of
voltages as shown below. When raising the power, do not use PLL clock. However, if voltage drop is
1mV/s or less, use of PLL clock is allowed during operation.
VCC
Limiting the slope of rising within
50 mV/ms is recommended.
2.7 ± 0.3 V
VSS
76
RAM data hold
MB90800 Series
(4) Serial I/O
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Sym
bol
Parameter
Pin name
Value
Conditions
Serial clock cycle time
tSCYC SC0 to SC3
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → Valid
SIN hold time
tSHIX
Serial clock H pulse width
tSHSL
Serial clock L pulse width
tSLSH
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid
SIN hold time
tSHIX
SC0 to SC3
SO0 to SO3 Internal shift clock
mode output pin :
C
L = 80 pF + 1TTL
SC0 to SC3
SI0 to SI3
SC0 to SC3
SC0 to SC3 External shift clock
SO0 to SO3 mode output pin :
CL = 80 pF + 1TTL
SC0 to SC3
SI0 to SI3
Unit Remarks
Min
Max
8 tCP
ns
−80
80
ns
100
ns
60
ns
4 tCP
ns
4 tCP
ns
150
ns
60
ns
60
ns
The Serial I/O is based on VSS = AVSS = 0.0 V.
Notes : • AC rating in CLK synchronous mode.
• C L is a load capacitance value on pins for testing.
• tCP is machine cycle frequency (ns) .
• Internal shift clock mode
tSCYC
2.4 V
SC
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SC
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
77
MB90800 Series
(5) Timer input timing
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIN0 to TIN2
IC0 to IC1
Input pulse width
Value
Min
Max
4 tCP
Unit
Remarks
ns
The Timer input timing is based on VSS = AVSS = 0.0 V.
• Timer Input Timing
0.8 VCC
0.8 VCC
TINx
ICx
0.2 VCC
tTIWH
0.2 VCC
tTIWL
(6) Timer output timing
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Min
Max
CLK ↑ → TOUT change time
tTO
TOT0 to TOT2,
PPG0 to PPG1,
OCU0 to OCU1
30
Unit
Remarks
ns
The Timer output timing is based on VSS = AVSS = 0.0 V.
• Timer Output Timing
2.4 V
CLK
tTO
TOTx
PPGx
OCUx
2.4 V
0.8 V
(7) Trigger Input Timing
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Symbol
Pin name
Conditions
tTRGH
tTRGL
INT0 to INT3
Input pulse width
Value
Unit
Max
5 tCP
ns
At normal operating
1
µs
In Stop mode
The Trigger Input Timing is based on VSS = AVSS = 0.0 V.
• Trigger Input Timing
0.8 VCC
0.8 VCC
INTx
0.2 VCC
tTRGH
78
Remarks
Min
0.2 VCC
tTRGL
MB90800 Series
(8) I2C Timing
(AVCC = VCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Parameter
Symbol
SCL clock frequency
Standardmode
Unit
Min Max
Conditions
fSCL
Hold time (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
“L” width of the SCL clock
tLOW
“H” width of the SCL clock
tHIGH
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data set-up time
SDA ↓ ↑ → SCL ↑
tSUDAT
Set-up time for STOP condition
SCL ↑ → SDA ↑
tSUSTO
Bus free time between a STOP and START
condition
tBUS
0
100
kHz
4.0
µs
4.7
µs
4.0
µs
4.7
µs
0
3.45
*3
µs
When power supply voltage of external
pull-up resistor is 5.0 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
250
When power supply voltage of external
pull-up resistor is 3.6 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
ns
When power supply voltage of external
pull-up resistor is 5.0 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
200
When power supply voltage of external
pull-up resistor is 3.6 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
ns
4.0
µs
4.7
µs
When power supply voltage of external
pull-up resistor is 5.0 V
R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 5.0 V
R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
R = 1.0 kΩ, C = 50 pF*2
The I2C trriger is based on AVSS = VSS = 0.0 V.
*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock timing”.
*2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
SDA
tSUDAT
tLOW
tBUS
tHDSTA
SCL
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
79
MB90800 Series
5. Electrical Characteristics for the A/D Converter
Symbol
Pin name
Resolution
Total error
Nonlinear error
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)
Value
Unit
Min
Typ
Max
10
bit
± 3.0
LSB
± 2.5
LSB
Differential linear error
± 1.9
LSB
Zero transition voltage
VOT
AN0 to AN11
AVSS − 1.5 AVss + 0.5 AVSS + 2.5
LSB
LSB
LSB
mV
VFST
AVcc − 3.5 AVcc − 1.5 AVcc + 0.5
AN0 to AN11
LSB
LSB
LSB
mV
Full-scale transition
voltage
1 LSB = AVcc/1024
Conversion time
8.64*1
µs
Sampling time
2
µs
Analog port input current
IAIN
AN0 to AN11
10
µA
Analog input voltage
VAIN
AN0 to AN11
0
AVcc
V
AVcc
3.0
AVcc
V
IA
AVcc
1.4
3.5
mA
IAH
AVcc
2
5*
µA
IR
AVcc
94
150
µA
Reference voltage
Power supply current
Reference voltage
supplying current
IRH
AVcc
5*
µA
Interchannel disparity
AN0 to AN11
4
LSB
2
Remarks
The Electrical characteristics for the A/D converter is based on VSS = AVSS = 0.0 V.
*1 : At operating, main clock 25 MHz.
*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (at Vcc − CPU = AVcc = 3.3 V)
80
MB90800 Series
<About the external impedance of analog input and its sampling time>
• A/D converter with sample and hold circuit. If the extrernal impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
Note : The values are reference values.
R
C
MB90803
1.9 kΩ (Max)
32.3 pF (Max)
MB90F804
1.9 kΩ (Max)
25.0 pF (Max)
MB90V800
1.9 kΩ (Max)
32.3 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
[External impedance = 0 kΩ to 20 kΩ]
MB90803/
MB90V800
100
MB90F804
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
MB90803/
MB90V800
20
→ External impedance [kΩ]
→ External impedance [kΩ]
[External impedance = 0 kΩ to 100 kΩ]
35
MB90F804
18
16
14
12
10
8
6
4
2
0
0
→ Minimum sampling time [µs]
1
2
3
4
5
6
7
8
→ Minimum sampling time [µs]
The relationship between external impedance and minimum sampling time
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
<About errors>
• As | AVCC | becomes smaller, values of relative errors grow larger.
81
MB90800 Series
6. Definition of A/D Converter Terms
Resolution
Analog variation that is recognized by an A/D converter.
The 10-bit can resolve analog voltage into 210 = 1024.
Total error
This shows the difference between the actual voltage and the ideal value and means a total of error because of
offset error, gain error, non-linearity error and noise.
Linearity error
Deviation between a line across zero-transition line (00 0000 0000↔00 0000 0001) and full-scale transition line
(11 1111 1110↔11 1111 1111) and actual conversion characteristics.
Differential linear error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Total error
3FF
3FE
0.5 LSB
Actual conversion
characteristic
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(measurement value)
003
Actual conversion
characteristics
002
Ideal characteristics
001
0.5 LSB
AVSS
(AVRL)
Total error of digital output N =
Analog input
AVCC
(AVRH)
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
1 LSB
1LSB(Ideal value) = AVCC − AVSS [V]
1024
VOT(Ideal value) = AVSS + 0.5 LSB [V]
VFST(Ideal value) = AVCC − 1.5 LSB [V]
VNT: A voltage at which digital output transitions from (N-1) to N.
(Continued)
82
MB90800 Series
(Continued)
Linearity error
3FE
Actual conversion characteristic
Actual conversion
characteristics
{1 LSB ´ (N - 1) + VOT}
N+1
Digital output
Ideal characteristics
VFST
3FD
(measurement value)
Digital output
3FF
Differential linear error
VNT
(measurement value)
004
Actual conversion
characteristics
003
N
V(N + 1)T
(measurement value)
N−1
VNT
002
(measurement value)
Ideal characteristics
001
Actual conversion
characteristics
N−2
VOT (actual measurement value)
AVCC
(AVRH)
AVSS
(AVRL)
AVSS
(AVRL)
AVCC
(AVRH)
Analog input
Analog input
Linear error in digital output N =
Differential linear error in digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
[LSB]
V (N + 1) T − VNT}
1 LSB
[LSB]
VFST − VOT
1022
− 1LSB
[V]
VOT : Voltage at which digital output transits from 000H to 001H.
VFST : Voltage at which digital output transits from 3FEH to 3FFH.
83
MB90800 Series
7. FLASH MEMORY
Parameter
Conditions
Sector erase time
Chip erase time
TA = + 25 °C
Vcc = 3.0 V
Word (16 bit width)
programming time
Value
Unit
Remarks
Min
Typ
Max
1
15
s
Excludes 00 H programming
prior to erasure.
9
µs
Excludes 00 H programming
prior to erasure.
16
3,600
s
Except for the over head time
of the system.
cycle
Program/erase cycle
10,000
Flash data retension
time
Average
TA = + 85 °C
20
Yearss *
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measuremunts into normalized value at + 85 °C).
84
MB90800 Series
■ ORDERING INFORMATION
Part number
MB90F804-101PF-G
MB90F804-201PF-G
MB90803PF
MB90803SPF
Package
Remarks
100-pin plastic QFP
(FPT-100P-M06)
85
MB90800 Series
■ PACKAGE DIMENSION
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
86
MB90800 Series
MEMO
87
MB90800 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
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Tel: +81-3-5322-3353
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http://edevice.fujitsu.com/
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Fax: +1-408-737-5999
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Korea
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http://www.fmk.fujitsu.com/
Preliminary 2004.07.22
FUJITSU LIMITED Printed in Japan
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