FUJITSU MB90F378

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16505-2Ea
Proprietary 32-bit Microcontroller
CMOS
FR60 MB91310 Series
MB91F312A/FV310A
■ DESCRIPTION
The FR families are lines of single-chip microcontrollers based on a 32-bit high-performance RISC CPU, incorporating a variety of I/O resources for embedded control applications which require high CPU performance for
high-speed processing.
The FR families are best suited for embedded applications which require high-performance CPU power for
processing, such as TV and POP control.
Based on the FR30/FR40 family CPU, this FR60 family is enhanced in bus access for use in faster applications.
■ FEATURE
• FR CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Operating frequency: 40 MHz (using PLL at an oscillation frequency of 10 MHz)
• 16 - bit fixed length instructions (basic instructions), 1 instruction per cycle
• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
(Continued)
■ PACKAGE
144-pin plastic LQFP
(FTP-144P-M08)
Copyright©2003-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2003.11
MB91310 Series
• Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store instructions
• Register interlock functions: Facilitating coding in assemblers
• On-chip multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC, PS save): 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction prefetch function implemented by a four-word queue in the CPU
• Instruction compatible with FR family
• Bus interface
This bus interface is used for macro connection. (USB, MS-IF, OSDC)
• Operating frequency Max 20 MHz
• 16-bit data input/output (Interface to the USB, MS-IF, and OSDC)
• Chip-select signals can be output for completely independent eight areas allocatable in a minimum of 64 KB.
The CS1, CS2, and CS3 areas are reserved as follows. CS0, CS4, to CS3 are Mnusable.
CS1 area : USB host
CS2 area : USB function
CS3 area : MS-IF, OSDC
• Basic bus cycle : 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
CS1, CS2 and CS3 are reserved; their settings are fixed.
• Built-in RAM
• 16 KB built RAM capacity
• This RAM can be used as instruction RAM by writing instruction code as well as data.
• DMAC (DMA Controller)
• Connected to five channels (ch0, ch1 → USB function; ch2 → MS-IF).
• 3 forwarding factors (internal peripheral/software)
• Addressing using 32 - bit full addressing mode (increment, decrement, fixed)
• Demand transfer, burst transfer, step transfer, or block transfer
• Selectable transfer data size: 8-bit, 16-bit, or 32-bit
• Bit search module (for REALOS)
• Search for the position of the bit 1/0-changed first in one word from the MSB
• Reload timer (including 1 channel for REALOS)
• 16-bit PPG timer ch3
• The internal clock is optional from 2/8/32 en surroundings.
(Continued)
2
MB91310 Series
• UART
• Full duplex double buffer
• UART : 5 channels
• With parity / no parity selection
• Asynchronous (start - stop synchronized) or CLK - synchronous communications selectable
• Internal timer for dedicated baud rate
• External clock can be used as transfer clock
• Assorted error detection functions (for parity, frame, and overrun errors)
• I2C Interface
• Four channels are incorporated. (ch3 can be used as two ports.)
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address and general call address detection function
• Detecting transmitting direction function
• Start condition repeat generation and detection function
• Bus error detection function
• 10 bit/7 bit slave address
• Standard mode (Max 100 Kbps)/High speed mode (Max 400 Kbps) supported
• Interrupt controller
• A total of five external interrupt lines are provided (1 nonmaskable interrupt pin (NMI) and 4 normal interrupt
pins (INT3 to INT0).
• Interrupt from internal peripheral devices.
• Programmable priorities (16 levels) for all interrupts except the non - maskable interrupt
• Available for wakeup from STOP mode
• A/D converter
• 10-bit resolution. 10 channels
• Successive comparator type, conversion time : approx. 10 μs
• Conversion modes (Single conversion mode, Scan conversion mode)
• Startup sources (software and external triggers)
• PPG
• 4 channels
• Six-bit down-counter, 16-bit data register with cycle setting buffer
• The internal clock is optional from 1/4/16/64 en surroundings.
• PWC
• One channel (input) incorporated
• 16 bits up counter
• Simple LFP digital filter incorporated
• Timer
• Lowpass filter eliminating noise below the clock setting
• Capable of pulse width measurement according to fine settings using seven types of clock signals
• Event count function based on pin input
• Interval timer function using seven different clocks and one external input clock
(Continued)
3
MB91310 Series
(Continued)
• USB host function
• U.S.B 1.0 Specification
• 8 KB of internal RAM for parameters
• USB function
• USB 1.1 compliant full-speed double buffering
• CONTROL IN/OUT, BULK IN/OUT, INTERRUPT IN
• OSDC function
• High-quality OSDC integrated
• Analog RGB interface (with internal DAC)
• Digital RGB I/F
• Internal dot clock generator PLL
• Other internal times
• 16-bit PPG timer ch3(u-timer)
• Watch dog timer
• I/O port
• Max 72 ports
• Other features
• Internal oscillator circuit as clock source
• INIT is prepared as a reset terminal.
• Watchdog timer reset. Software reset.
• Low power consumption modes supported: Stop mode and Sleep mode
• Gear function
• Built-in time base timer
• Package : LQFP-144, 0.5 mm pitch, 20 mm × 20 mm
• CMOS technology (0.25 µm)
• Supply voltage: Dual power supplies at 3.3 V ± 0.3 V, 2.5 V ± 0.2 V
THE I2C LICENSE : “Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights
to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification
as defined by Philips.”
4
MB91310 Series
(TOP VIEW)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IBREAK
ICLK
TRST
VSS
VDDI
VDDE
NMI
P65/INT3
P64/INT2
P63/INT1
P62/INT0
P61
P60/ATRG
P57/TRG3
P56/TRG2
P55/TRG1
P54/TRG0
P53/TMI3
P52/TMI2
P51/TMI1
P50/TMI0
MD3
MD2
MD1
MD0
P47/PPG3
P46/PPG2
P45/PPG1
P44/PPG0
X1A
VSS
X0A
VDDI
VDDE
P43/TMO3
P42/TMO2
P01/SDA0
P02/SCL1
P03/SDA1
VDDE
VDDI(PLL)
X0
VSS
X1
INIT
P04/SCL2
P05/SDA2
P06/SCL3
P07/SCL4
P10/SDA3
P11/SDA4
P12/SI0
P13/SO0
P14/SCK0
P15/SI1
P16/SO1
P17/SCK1
P20/SI2
P21/SO2
P22/SCK2
P23/SI3
P24/SO3
P25/SCK3
P30/SI4/TIN0
P31/SO4/TIN1
P32/SCK4/TIN2
P33/TO0
P34/TO1
P35/TO2
P36/RIN
P40/TMO0
P41/TMO1
DOCKI
FH
VSYNC
HSYNC
VGS
CPO
VSS
VDDI (PLL)
VDDR (2.5 V)
VREF (1.1 V)
VRO (2.7 kΩ)
RCOMP (0.1 μF)
ROUT
VSSR
VDDG (2.5 V)
GCOMP (0.1 μF)
GOUT
VSSG
VDDB (2.5 V)
BCOMP (0.1 μF)
BOUT
VSSB
AVCC
AVRH
AVSS/AVRL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
P00/SCL0
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
DCKO
VOB1
VOB2
VDDE
VDDI
VSS
R2
R1
R0
G2
G1
G0
B2
B1
B0
UHP
UHM
UDP
UDM
VDDE
VDDI
X1B
VSS
X0B
P74
P73
P72
P71
P70
ICD3
ICD2
ICD1
ICD0
ICS2
ICS1
ICS0
■ PIN ASSIGNMENT
5
MB91310 Series
■ PIN DESCRIPTION
Pin no.
Pin name
Circuit type
Description
1
DOCKI
D
Dot clock input
2
FH
D
Vertical synchronous output
3
VSYNC
D
Horizontal synchronous input
4
HSYNC
D
Vertical synchronous input
5
VGS
⎯
Device Ground
6
CPO
K
Charge pump output
7
VSS
⎯
Dot clock PLL ground
8
VDDI (PLL)
⎯
Dot clock PLL power supply
9
VDDR (2.5 V)
⎯
D/A power supply for R
10
VREF (1.1 V)
K
Voltage reference input
11
VRO (2.7 kΩ)
K
Resistor connection pin
12
RCOMP (0.1 μF)
K
Capacitor connection pin
13
ROUT
K
R output (Analog)
14
VSSR
⎯
D/A Ground for R
15
VDDG (2.5 V)
⎯
D/A power supply for G
16
GCOMP (0.1 μF)
K
Capacitor connection pin
17
GOUT
K
G output (Analog)
18
VSSG
⎯
Device Ground for G
19
VDDB (2.5 V)
⎯
D/A power supply for B
20
BCOMP (0.1 μF)
K
Capacitor connection pin
21
BOUT
K
B output (Analog)
22
VSSB
⎯
D/A Ground for B
23
AVCC
⎯
A/D Power Supply
24
AVRH
⎯
A/D referense power supply
25
AVSS/AVRL
⎯
A/D Ground
26
AN0
E
Analog input
27
AN1
E
Analog input
28
AN2
E
Analog input
29
AN3
E
Analog input
30
AN4
E
Analog input
31
AN5
E
Analog input
32
AN6
E
Analog input
33
AN7
E
Analog input
34
AN8
E
Analog input
35
AN9
E
Analog input
(Continued)
6
MB91310 Series
Pin no.
36
37
38
39
Pin name
P00
SCL0
P01
SDA0
P02
SCL1
P03
SDA1
Circuit type
C
C
C
C
Description
General-purpose port
I2C clock pin
General-purpose port
I2C Data pin
General-purpose port
I2C Clock
General-purpose port
I2C Data pin
40
VDDE
⎯
3.3 V Power Supply
41
VDDI (PLL)
⎯
2.5 V Power Supply
42
X0
A
10-MHz oscillation pin
43
VSS
⎯
Ground
44
X1
A
10-MHz oscillation pin
45
INIT
B
Initial (reset) pin
46
47
48
49
50
51
52
53
54
55
56
P04
SCL2
P05
SDA2
C
C
P06
SCL3
P07
N
SI0
P13
SO0
P14
SCK0
P15
SI1
P16
SO1
I2C Data pin
I2C clock
General-purpose pors
General-purpose port
N
I2C data pin
General-purpose port
I2C data pin
SDA4
P12
General-purpose port
I2C clock
P10
P11
I2C clock
General-purpose port
SCL4
SDA3
General-purpose port
C
C
C
C
C
General-purpose port
UART0 serial input
General-purpose port
UART0 serial output
General-purpose port
UART0 clock input/output
General-purpose port
UART1 serial input
General-purpose port
UART1 serial output
(Continued)
7
MB91310 Series
Pin no.
57
58
59
60
61
62
63
Pin name
P17
SCK1
P20
SI2
P21
SO2
P22
SCK2
P23
SI3
P24
SO3
P25
SCK3
Circuit type
C
C
C
C
C
C
C
P30
64
65
66
SI4
68
69
70
71
72
General-purpose port
UART1 clock input/output
General-purpose port
UART2 serial input
General-purpose port
UART2 serial output
General-purpose port
UART2 clock input/output
General-purpose port
UART3 serial input
General-purpose port
UART3 serial output
General-purpose port
UART3 clock input/output
General-purpose port
C
UART4 serial input
TIN0
Reload timer 0 trigger input
P31
General-purpose port
SO4
C
UART4 serial output
TIN1
Reload timer 1 trigger input
P32
General-purpose port
SCK4
C
TIN2
67
Description
P33
TO0
P34
TO1
P35
TO2
P36
RIN
P40
TMO0
P41
TMO1
UART4 clock input/output
Reload timer 2 trigger input
C
C
C
C
C
C
General-purpose port
Reload timer 0 output
General-purpose port
Reload timer 1 output
General-purpose port
Reload timer 2 output
General-purpose port
PWC input
General-purpose port
Multi-function timer 0 output
General-purpose port
Multi-function timer 1 output
(Continued)
8
MB91310 Series
Pin no.
73
74
Pin name
P42
TMO2
P43
TMO3
Circuit type
C
C
Description
General-purpose port
Multi-function timer 2 output
General-purpose port
Multi-function timer 3 output
75
VDDE
⎯
3.3 V power supply
76
VDDI
⎯
2.5 V power supply
77
X0A
A
32 kHz oscillation pin
78
VSS
⎯
Ground
79
X1A
A
32 kHz oscillation pin
80
81
82
83
P44
PPG0
P45
PPG1
P46
PPG2
P47
PPG3
C
C
C
C
General-purpose port
PPG0 output
General-purpose port
PPG1 output
General-purpose port
PPG2 output
General-purpose port
PPG3 output
84
MD0
F
Mode Pins
85
MD1
F
Mode Pins
86
MD2
F
Mode Pins
87
MD3
F
Mode Pins (ground)
88
89
90
91
92
93
94
P50
TMI0
P51
TMI1
P52
TMI2
P53
TMI3
P54
TRG0
P55
TRG1
P56
TRG2
C
C
C
C
⎯
⎯
⎯
General-purpose port
Multi-function timer 0 input
General-purpose port
Multi-function timer 1 input
General-purpose port
Multi-function timer 2 input
General-purpose port
Multi-function timer 3 input
General-purpose port
PPG0 trigger input
General-purpose port
PPG1 trigger input
General-purpose port
PPG2 trigger input
(Continued)
9
MB91310 Series
Pin no.
95
96
97
98
99
100
101
Pin name
P57
TRG3
P60
ATRG
P61
P62
INT0
P63
INT1
P64
INT2
P65
INT3
Circuit type
C
C
C
O
O
O
O
Description
General-purpose port
PPG3 trigger input
General-purpose port
A/D conversion trigger input
General-purpose port
General-purpose port
External interrupt input 0
General-purpose port
External interrupt input 1
General-purpose port
External interrupt input 2
General-purpose port
External interrupt input 3
102
NMI
B
NMI input
103
VDDE
⎯
3.3 V power supply
104
VDDI
⎯
2.5 V power supply
105
VSS
⎯
Ground
106
TRST
B
DSU tool reset
107
ICLK
C
DSU clock
108
IBREAK
L
DSU break
109
ICS0
M
DSU status
110
ICS1
M
DSU status
111
ICS2
M
DSU status
112
ICD0
H
DSU data
113
ICD1
H
DSU data
114
ICD2
H
DSU data
115
ICD3
H
DSU data
116
P70
I
General-purpose port
117
P71
C
General-purpose port
118
P72
C
General-purpose port
119
P73
C
General-purpose port
120
P74
H
General-purpose port
121
X0B
A
48 MHz oscillation pin
122
VSS
⎯
Ground
(Continued)
10
MB91310 Series
(Continued)
Pin no.
Pin name
Circuit type
123
X1B
A
48 MHz oscillation pin
124
VDDI
⎯
2.5 V power supply
125
VDDE
⎯
3.3 V power supply
126
UDM
127
UDP
128
UHM
129
UHP
130
B0
D
RGB digital output
131
B1
D
RGB digital output
132
B2
D
RGB digital output
133
G0
D
RGB digital output
134
G1
D
RGB digital output
135
G2
D
RGB digital output
136
R0
D
RGB digital output
137
R1
D
RGB digital output
138
R2
D
RGB digital output
139
VSS
⎯
Ground
140
VDDI
⎯
2.5 V power supply
141
VDDE
⎯
3.3 V power supply
142
VOB2
D
Semi Transparent color periodoutput
143
VOB1
D
OSD display period output
144
DCKO
D
Dot clock output
USB
USB
Description
USB-Function
USB-Function
USB-Host
USB-Host
11
MB91310 Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
• Oscillation circuit
Clock input
X1
X0
A
STANDBY
CONTROL
• CMOS hysteresis input
With pull-up resistance
B
Digital input
Digital output
• CMOS level output.
CMOS level hysteresis input
With standby control
Digital output
C
Digital input
STANDBY CONTROL
2.5 V
Digital output
• 2.5 V CMOS level output.
CMOS level hysteresis input
With standby control
Digital output
D
Digital input
STANDBY CONTROL
(Continued)
12
MB91310 Series
Type
Circuit type
Remarks
• Analog input with switch
E
Analog input
Input control
• CMOS level input
Without standby control
F
Digital input
• CMOS level hysteresis input
Without standby control
G
Digital input
Digital output
• CMOS level output
Hysteresis input
Standby control provided
Pull-down resistor provided
Digital output
H
Digital input
STANDBY CONTROL
(Continued)
13
MB91310 Series
Type
Circuit type
Remarks
Digital output
• CMOS level output
Hysteresis input
Standby control provided
Pull-up resistor provided
Digital output
I
Digital input
STANDBY CONTROL
Open drain control
• Open drain output
CMOS level hysteresis input
With standby control
Digital output
J
Digital input
STANDBY CONTROL
• Analog pin
K
• CMOS hysteresis input
With pull-down resistance
L
Digital input
(Continued)
14
MB91310 Series
(Continued)
Type
Circuit type
Remarks
• CMOS level output
Open drain control
M
Digital output
Open drain control
• Two ports for I2C
CMOS hysteresis input
CMOS output
Stop control provided
Digital output
Digital input
N
Input control
Digital input
Open drain control
Digital output
• CMOS level output
CMOS hysteresis input
Digital output
O
Digital output
Digital input
15
MB91310 Series
■ HANDLING DEVICES
• Preventing Latchup
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output
pin or if an above-rating voltage is applied between VCC and VSS. A latchup,if it occurs, significantly increases
the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very
careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
• About Power Supply Pins
If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary
radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard
for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
The power pins should be connected to VCC and VSS of this device at the lowest possible impedance from the
current supply source.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1μF between VCC and VSS near
this device.
• About Crystal Oscillator Circuit
Noise near the X0 and X1 pin may cause the device to malfunction. When designing a PC board using the
device, place the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor leading to the
ground as close to one another as possible.
It is strongly recommended to design PC board so that X0 and X1 pins are surrounded by grounding area for
stable operation.
• About Mode Pins (MD0 to MD3)
These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test
mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or
V.0 is as short as possible and the connection impedance is low.
• About Tool Reset Pin (TRST)
This pin must input the same signal as that to INIT when the tool is not used. Apply the same treatment to massproduced products as well.
• Operation at Start-up
A setting initialization reset (INIT) must always be performed via the INIT pin immediately after the power supply
is turned on or recycled.
Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time
required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT
via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)
16
MB91310 Series
• Oscillation Input at Power-ON
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
• Notes on Power-ON/shut-down
Cautions to take when turning on/off VDDI (2.5-V internal power supply) and VDDE (3.3-V external-pin power
supply)
Do not apply VDDE (external) alone continuously (for over an indication of one minute) with VDDI (internal)
disconnected not to cause a reliability problem with the LSI.
When VDDE (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state,
for example, due to power supply noise.
When the power is turned on
VDDI (internal)→Analog→VDDE (external)→Signal
When the power is turned off
Signal→VDDE (external)→Analog→VDDI (internal)
• Undefined Output on Power-ON
When the power supply is turned on, the output pin may remain indeterminate until the internal power supply
becomes stable.
• About the attention when the external clock is used
When the external clock is used, in principle, supply a clock signal to the X0 (X0A, X0B) pin and an oppositephase clock signal to the X1 (X1A, X1B) pin at the same time. However, In this case. the stop mode must not
be used.(This is because, in STOP mode, the X1 (X1A, X1B) pin stops at “H” output.) At 12.5 MHz or less, the
device can be used with the clock signal supplied only to the X0 (X0A, X0B) pin.
An example of using the external clock is illustrated below.
X0, X0A, X0B
X1, X1A, X1B
MB91F312A/FV310A
[STOP mode (oscillation stop mode) cannot be used.]
External clock usage (normal)
X0, X1A, X1B
X1, X1A, X1B
OPEN
MB91F312A/FV310A
External clock usage (enabled at 12.5 MHz Max.)
Note : The X1 (X1A, X1B) pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0
(X0A, X0B) pin.
17
MB91310 Series
• Restrictions
Common in the MB91310 series
(1) Clock Control Block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
(2) Bit Search Module
The 0-detection data register (BSD0), 1-detection data register (BSD1), and transition-detection data register
(BSDC) are only word-accessible.
(3) I/O Port
Ports are accessed only in bytes.
(4) Low Power Consumption Mode
To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR,
or time-base counter control register) and be sure to use the following sequence:
(LDI #value_of_standby, R0)
(LDI #_STCR, R12)
STB R0, @R12
: Write to standby control register (STCR)
LDUB
@R12, R0
: STCR lead for synchronous standby
LDUB
@R12, R0
: Dummy re-lead of STCR
NOP
: NOP × 5 for timing adjustment
NOP
NOP
NOP
NOP
In addition, set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt
handler triggers the microcontroller to return from the standby mode.
Please do not do the following when the monitor debugger is used.
• Set a break point within the above array of instructions.
• Single-step the above instructions.
(5) Pre-fetch
When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only.
Byte or half-word access results in wrong data read.
(6) Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
1. The following operations are performed when (c) the instruction followed by a data event or a DIVOU/DIVOS
emulator menu instruction (a) receives a user interrupt or NMI or (b) breaks when single-stepped.
18
MB91310 Series
• The D0 and D1 flags are updated in advance.
• An EIT handling routine (user interrupt, NMI, or emulator) is executed.
• Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated
to the same values as in (1).
2. The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed.
• The PS register is updated in advance.
• An EIT handling routine (user interrupt or NMI) is executed.
• Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as in (1).
(7) Watchdog Timer
The watchdog timer built in this model monitors a program to check that it defers a reset within a certain period
of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function
from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps
on watching programs until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.Refer to the watchdog timer function description for the exceptional condition.
If the system runs out of control and develops the above condition, a watchdog reset may not be generated.
In that case, please reset (INIT) by external INIT terminal.
(8) Notes on using the A/D converter
The MB91310 series contains an A/D converter. Supply power to the AVCC at 3.3 V.
Unique to the evaluation chip MB91FV310A
(1) Simultaneous occurrences of a software break and a user interrupt/NMI
If a software break and a user interrupt/NMI occurs simultaneously, the emulator debugger may react as follows.
• The debugger stops pointing to a location other than the programmed break points.
• The halted program is not re - executed correctly.
If this symptom occurs, use a hardware break in place of a hardware break. If you use the monitor debugger,
do not set a break point within the relevant array of instructions.
(2) Single-stepping of the RETI instruction
If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
(3) About an Operand Break
Do not apply a data event break to access to the area containing the address of a stack pointer.
(4) Sample Batch File for Configuration
To debug a program downloaded to internal RAM, be sure to execute the following batch file after executing
RESET.
# Set MODR (0x7fd) = Enable In memory + 16-bit External Bus
set mem/byte 0x7fd = 0x5
19
MB91310 Series
■ BLOCK DIAGRAM
FR
CPU Core
32
32
Flash 512 KB
Bit search
Bus Converter
RAM 16 KB
32 16
Adapter
External
48 MHz
I/F
Clock
control
Font Flash
DMAC 5 ch
USB
function
USB
host
OSDC
Interrupt
controller
UART
5 ch
U-TIMER
5 ch
I2 C
4 ch
PWC
1 ch
PPG
4 ch
Reload
timer
3 ch
External
interrupt
Ports
20
A/D
10 ch
Timer
4 ch
MB91310 Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the length of the data being accessed as shown below.
→ byte data access
: 0-0FFH
→ half word data access
: 0-1FFH
→ word data access
: 0-3FFH
2. Memory Map
The figure below shows the memory space of the this item kind.
Single chip mode
internal ROM external
bus mode
0000 0000H
I/O
0000 0400H
I/O
Direct
Addressing area
Refer to I/O Map
0001 0000H
0003 C000H
0004 0000H
Access
disallowed
Built-in RAM
0005 0000H
USB-HOST (REG)
0005 8000H
USB-HOST (RAM)
0006 0000H
USB-FUNC
0007 0000H
MS
0007 8000H
OSDC
0008 0000H
Flash ROM1
512 KB
Program
Flash ROM2
512 KB
Font
0010 0000H
0018 0000H
0020 0000H
External area
FFFF FFFFH
21
MB91310 Series
■ I/O MAP
This shows the location of the various peripheral resource registers in the memory space.
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
Port Data
Register
Read/Write attribute
Initial value after a reset
Register name (First-column register at address 4n; second-column
register at address 4n + 2)
Location of left - most register (When using word access, the register
in column 1 is in the MSB side of the data.)
Note:Initial values of register bits are represented as follows:
“1”
“0”
“X”
“-”
22
: Initial Value: “1”
: Initial Value: “0”
: Initial Value: “X”
: No physical register at this location
MB91310 Series
Address
Register
+0
+1
+2
+3
000000H
to
00000FH
⎯
⎯
⎯
⎯
000010H
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
--XXXXXX
PDR3 [R/W]
-XXXXXXX
000014H
PDR4 [R/W]
XXXXXXXX
PDR5 [R/W]
XXXXXXXX
PDR6 [R/W]
--XXXXXX
PDR7 [R/W]
---XXXXX
000018H
⎯
⎯
⎯
⎯
00001CH
⎯
⎯
⎯
⎯
000020H
ADCTH [R/W]
XXXXXX00
ADCTL [R/W]
00000X00
Block
Reserved
R-bus
Port Data Register
ADCH [R/W]
00000000_00000000
000024H
ADAT0 [R]
XXXXXX00_00000000
ADAT1 [R]
XXXXXX00_00000000
000028H
ADAT2 [R]
XXXXXX00_00000000
ADAT3 [R]
XXXXXX00_00000000
00002CH
ADAT4 [R]
XXXXXX00_00000000
ADAT5 [R]
XXXXXX00_00000000
000030H
ADAT6 [R]
XXXXXX00_00000000
ADAT7 [R]
XXXXXX00_00000000
000034H
ADAT8 [R]
XXXXXX00_00000000
ADAT9 [R]
XXXXXX00_00000000
10 bit A/D converter
000038H
⎯
⎯
⎯
⎯
00003CH
⎯
⎯
⎯
⎯
000040H
EIRR [R/W]
00000000
ENIR [R/W]
00000000
ELVR [R/W]
00000000
Ext int
000044H
DICR [R/W]
-------0
HRCL [R/W]
0--11111
⎯
DLYI/I-unit
000048H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
TMR0 [R]
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R/W]
----0000 00000000
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
TMR1 [R]
XXXXXXXX XXXXXXXX
000054H
⎯
TMCSR1 [R/W]
----0000 00000000
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
TMR2 [R]
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R/W]
----0000 00000000
Reserved
Reload Timer 0
Reload Timer 1
Reload Timer 2
(Continued)
23
MB91310 Series
Address
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
00007CH
000080H
Register
+1
+2
+3
SSR [R/W]
00001-00
SIDR [R/W]
XXXXXXXX
SCR [R/W]
00000100
SMR [R/W]
00--0-0-
UART0
DRCL [W]
--------
UTIMC [R/W]
0--00001
U-TIMER 0
SCR [R/W]
00000100
SMR [R/W]
00--0-0-
UART1
DRCL [W]
--------
UTIMC [R/W]
0--00001
U-TIMER 1
SCR [R/W]
00000100
SMR [R/W]
00--0-0-
UART2
DRCL [W]
--------
UTIMC [R/W]
0--00001
U-TIMER 2
SCR [R/W]
00000100
SMR [R/W]
00--0-0-
UART3
DRCL [W]
--------
UTIMC [R/W]
0--00001
U-TIMER 3
SCR [R/W]
00000100
SMR [R/W]
00--0-0-
UART4
DRCL [W]
--------
UTIMC [R/W]
0--00001
U-TIMER 4
UTIM [R] (UTIMR [W])
00000000 00000000
SSR [R/W]
00001-00
SIDR [R/W]
XXXXXXXX
UTIM [R] (UTIMR [W])
00000000 00000000
SSR [R/W]
00001-00
SIDR [R/W]
XXXXXXXX
UTIM [R] (UTIMR [W])
00000000 00000000
SSR [R/W]
00001-00
SIDR [R/W]
XXXXXXXX
UTIM [R] (UTIMR [W])
00000000 00000000
SSR [R/W]
00001-00
SIDR [R/W]
XXXXXXXX
000084H
UTIM [R] (UTIMR [W])
00000000 00000000
000088H
⎯
⎯
00008CH
⎯
⎯
000090H
PWCC [R/W]
PWCD [R]
XXXXXXXX_XXXXXXXX
⎯
000098H
⎯
⎯
00009CH
⎯
⎯
0000A0H
⎯
⎯
0000A4H
⎯
⎯
0000A8H
⎯
⎯
0000ACH
⎯
⎯
0000B0H
⎯
⎯
0000B4H
IBCR [R/W]
00000000
IBSR [R/W]
00000000
ITMK [R/W]
00----11 11111111
Reserved
⎯
PWCC [R/W]
000094H
0000B8H
Block
+0
⎯
PWC
Reserved
⎯
ITBA [R/W]
------00 00000000
ISMK [R/W]
01111111
ISBA [R/W]
00000000
0000BCH
⎯
IDAR [R/W]
00000000
ICCR [R/W]
0-011111
IDBL [R/W]
-------0
0000C0H
⎯
⎯
⎯
⎯
I2C interface
ch0
Reserved
(Continued)
24
MB91310 Series
Address
0000C4H
0000C8H
Register
+0
+1
IBCR [R/W]
00000000
IBSR [R/W]
00000000
ITMK [R/W]
00----11 11111111
+2
+3
ITBA [R/W]
------00 00000000
ISMK [R/W]
01111111
ISBA [R/W]
00000000
0000CCH
⎯
IDAR [R/W]
00000000
ICCR [R/W]
0-011111
IDBL [R/W]
-------0
0000D0H
⎯
⎯
⎯
⎯
0000D4H
IBCR [R/W]
00000000
IBSR [R/W]
00000000
0000D8H
ITMK [R/W]
00----11 11111111
ISMK [R/W]
01111111
ISBA [R/W]
00000000
⎯
IDAR [R/W]
00000000
ICCR [R/W]
0-011111
IDBL [R/W]
-------0
0000E0H
⎯
⎯
⎯
⎯
0000E4H
IBCR [R/W]
00000000
IBSR [R/W]
00000000
ITMK [R/W]
00----11 11111111
ISMK [R/W]
01111111
ISBA [R/W]
00000000
⎯
IDAR [R/W]
00000000
ICCR [R/W]
0-011111
IDBL [R/W]
-------0
0000F0H
T0LPCR [R/W]
-----000
T0CCR [R/W]
0-010000
T0TCR [R/W]
00000000
T0R [R/W]
---00000
0000F8H
0000FCH
000100H
000104H
000108H
00010CH
T0DRR [R/W]
XXXXXXXX XXXXXXXX
T1LPCR [R/W]
-----000
T1CCR [R/W]
0-000000
T1DRR [R/W]
XXXXXXXX XXXXXXXX
T2LPCR [R/W]
-----000
T2CCR [R/W]
0-000000
T2DRR [R/W]
XXXXXXXX XXXXXXXX
T3LPCR [R/W]
-----000
T3CCR [R/W]
0-000000
T3DRR [R/W]
XXXXXXXX XXXXXXXX
000110H
⎯
⎯
000120H
PTMR0 [R]
11111111_11111111
000124H
PDUT0 [W]
XXXXXXXX_XXXXXXXX
Reserved
I2C interface
ch2
Reserved
ITBA [R/W]
------00 00000000
0000ECH
0000F4H
I2C interface
ch1
ITBA [R/W]
------00 00000000
0000DCH
0000E8H
Block
I2C interface
ch3
T0CRR [R/W]
XXXXXXXX XXXXXXXX
T1TCR [R/W]
00000000
T1R [R/W]
---00000
T1CRR [R/W]
XXXXXXXX XXXXXXXX
T2TCR [R/W]
00000000
T2R [R/W]
---00000
Multi-function
timer
T2CRR [R/W]
XXXXXXXX XXXXXXXX
T3TCR [R/W]
00000000
T3R [R/W]
---00000
T3CRR [R/W]
XXXXXXXX XXXXXXXX
⎯
⎯
PCSR0 [W]
XXXXXXXX_XXXXXXXX
PCNH0 [R/W]
00000000
PCNL0 [R/W]
00000000
Reserved
PPG0
(Continued)
25
MB91310 Series
Address
Register
+0
+1
000128H
PTMR1 [R]
11111111_11111111
00012CH
PDUT1 [W]
XXXXXXXX_XXXXXXXX
000130H
PTMR2 [R]
11111111_11111111
000134H
PDUT2 [W]
XXXXXXXX_XXXXXXXX
000138H
PTMR3 [R]
11111111_11111111
00013CH
PDUT3 [W]
XXXXXXXX_XXXXXXXX
+2
+3
PCSR1 [W]
XXXXXXXX_XXXXXXXX
PCNH1 [R/W]
00000000
PCNL1 [R/W]
00000000
PCSR2 [W]
XXXXXXXX_XXXXXXXX
PCNH2 [R/W]
00000000
PCNL2 [R/W]
00000000
PCSR3 [W]
XXXXXXXX_XXXXXXXX
PCNH3 [R/W]
00000000
PCNL3 [R/W]
00000000
000140H
⎯
⎯
⎯
⎯
000144H
⎯
⎯
⎯
⎯
000148H
⎯
⎯
⎯
⎯
00014CH
⎯
⎯
⎯
⎯
000150H
⎯
⎯
⎯
⎯
000154H
⎯
⎯
⎯
⎯
000158H
⎯
⎯
⎯
⎯
00015CH
⎯
⎯
⎯
⎯
000160H
to
0001FCH
⎯
⎯
⎯
⎯
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB4 [R/W]
00000000 00000000 00000000 00000000
Block
PPG1
PPG2
PPG3
Reserved
DMAC
(Continued)
26
MB91310 Series
Address
Register
+0
+1
+2
+3
Block
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000228H
⎯
00022CH
to
00023CH
⎯
Reserved
000240H
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
000244H
to
0002FCH
⎯
000300H
to
0003ECH
⎯
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
⎯
Bit Search Module
000400H
DDR0 [R/W]
00000000
DDR1 [R/W]
00000000
DDR2 [R/W]
--000000
DDR3 [R/W]
-0000000
000404H
DDR4 [R/W]
00000000
DDR5 [R/W]
00000000
DDR6 [R/W]
--000000
DDR7 [R/W]
---00000
000408H
⎯
⎯
⎯
⎯
00040CH
⎯
⎯
⎯
⎯
000410H
PFR0 [R/W]
0--00000
PFR1 [R/W]
00000000
PFR2 [R/W]
000---00
PFR3 [R/W]
00000000
000414H
PFR4 [R/W]
0-------
⎯
⎯
⎯
000418H
⎯
⎯
⎯
⎯
00041CH
⎯
⎯
⎯
⎯
000420H
to
00043CH
⎯
R-bus
Port Direction
Register
R-bus
Port Function
Register
Reserved
(Continued)
27
MB91310 Series
Address
Register
+0
+1
+2
+3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
to
00047CH
⎯
Block
Interrupt Control unit
Interrupt Control unit
⎯
000480H
RSRR [R/W]
10000000*2
STCR [R/W]
00110011*2
TBCR [R/W]
00XXXX00*1
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000*1
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011*1
DIVR1 [R/W]
00000000*1
000488H
⎯
⎯
OSCCR [R/W]
XXXXXXX0
⎯
⎯
00048CH
WPCR [R/W] B
00---000
⎯
⎯
⎯
Clock timer
000490H
OSCR [R/W] B
00---000
⎯
⎯
⎯
Oscillation
Stabilization Waiting
Clock Control unit
(Continued)
28
MB91310 Series
Address
Register
+0
+1
000494H
to
0005FCH
+2
+3
⎯
Reserved
000600H
⎯
⎯
⎯
⎯
000604H
⎯
⎯
⎯
⎯
000608H
⎯
⎯
⎯
⎯
00060CH
⎯
⎯
⎯
⎯
000610H
⎯
⎯
⎯
⎯
000614H
⎯
⎯
⎯
⎯
000618H
⎯
⎯
⎯
⎯
00061CH
⎯
⎯
⎯
⎯
000620H
⎯
000624H
⎯
000628H
to
00063FH
⎯
Block
T-unit
Port Direction
Register
T-unit
Port Function
Register
Reserved
000640H
ASR0 [R/W]
00000000 00000000*1
ACR0 [R/W]
1111XX00 00000000*1
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX*1
ACR1 [R/W]
XXXXXXXX XXXXXXXX*1
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX*1
ACR2 [R/W]
XXXXXXXX XXXXXXXX*1
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX*1
ACR3 [R/W]
XXXXXXXX XXXXXXXX*1
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX*1
ACR4 [R/W]
XXXXXXXX XXXXXXXX*1
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX*1
ACR5 [R/W]
XXXXXXXX XXXXXXXX*1
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX*1
ACR6 [R/W]
XXXXXXXX XXXXXXXX*1
00065CH
ASR7 [R/W]
XXXXXXXX XXXXXXXX*1
ACR7 [R/W]
XXXXXXXX XXXXXXXX*1
000660H
AWR0 [R/W]
011111111 11111111*1
AWR1 [R/W]
XXXXXXXX XXXXXXXX*1
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX*1
AWR3 [R/W]
XXXXXXXX XXXXXXXX*1
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX*1
AWR5 [R/W]
XXXXXXXX XXXXXXXX*1
T-unit
(Continued)
29
MB91310 Series
Address
00066CH
Register
+0
+1
+2
AWR6 [R/W]
XXXXXXXX XXXXXXXX*1
⎯
000674H
⎯
IOWR0 [R/W]
XXXXXXXX
IOWR1 [R/W]
XXXXXXXX
CSER [R/W]
000000001
CHER [R/W]
11111111
000684H
⎯
000684H
to
0007F8 H
⎯
0007FCH
IOWR2 [R/W]
XXXXXXXX
⎯
⎯
TCR [R/W]
00000000
T-unit
⎯
00067CH
000680H
Block
AWR7 [R/W]
XXXXXXXX XXXXXXXX*1
000670H
000678H
+3
MODR [W]
XXXXXXXX
⎯
000800H
to
000AFCH
Reserved
⎯
⎯
⎯
⎯
Reserved
000B00H
ESTS0 [R/W]
X0000000
ESTS1 [R/W]
XXXXXXXX
ESTS2 [R]
1XXXXXXX
⎯
000B04H
ECTL0 [R/W]
0X000000
ECTL1 [R/W]
00000000
ECTL2 [W]
000X0000
ECTL3 [R/W]
00X00X11
000B08H
ECNT0 [W]
XXXXXXXX
ECNT1 [W]
XXXXXXXX
EUSA [W]
XXX00000
EDTC [W]
0000XXXX
000B0CH
EWPT [R]
00000000 00000000
⎯
000B10H
EDTR0 [W]
XXXXXXXX XXXXXXXX
EDTR1 [W]
XXXXXXXX XXXXXXXX
000B14H
to
000B1CH
⎯
000B20H
EIA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DSU
(Continued)
30
MB91310 Series
Address
Register
+0
+1
+2
+3
000B34H
EIA5 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B48H
EOA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B4CH
EOA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B64H
EOAM1/EODM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B68H
EOD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B70H
to
000FFCH
⎯
001000H
DMASA0 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
Block
DSU
Reserved
DMAC
(Continued)
31
MB91310 Series
Address
Register
+0
+1
+2
+3
001010H
DMASA2 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001028H
to
006FFCH
⎯
Block
DMAC
Reserved
007000H
FLCR [R/W]
0110_X000
⎯
007004H
FLWC [R/W]
0001_0011
⎯
Program FLASH I/F
007008H
to
00707CH
⎯
Reserved
007080H
to
0070FCH
⎯
Reserved
007100H
FNCR [R/W]
0110_X000
⎯
007104H
FNWC [R/W]
0001_0011
⎯
FONT FLASH I/F
00050000H
HR (Hc Revision) [R]
00000000_00000000_00000001_00010000
00050004H
HC (Hc Control) [R/W]
00000000_00000000_00000000_00000000
00050008H
HCS (Hc Command Status) [R/W]
00000000_00000000_00000000_00000000
0005000CH
HIS (Hc Interrupt Status) [R/W]
00000000_00000000_00000000_00000000
00050010H
HIE (Hc Interrupt Enable) [R/W]
00000000_00000000_00000000_00000000
00050014H
HID (Hc Interrupt Disable) [R/W]
00000000_00000000_00000000_00000000
USB
Host
(Continued)
32
MB91310 Series
Address
Register
+0
+1
+2
00050018H
HHCCA (Hc HCCA) [R/W]
00000000_00000000_00000000_00000000
0005000CH
HPCED (Hc Period Current ED) [R/W]
00000000_00000000_00000000_00000000
00050020H
HCHED (Hc Control Head ED) [R/W]
00000000_00000000_00000000_00000000
00050024H
HCCED (Hc Control Current ED) [R/W]
00000000_00000000_00000000_00000000
00050028H
HBHED (Hc Bulk Head ED) [R/W]
00000000_00000000_00000000_00000000
0005002CH
HBCED (Hc Bulk Current ED) [R/W]
00000000_00000000_00000000_00000000
00050030H
HDH (Hc Done Head) [R/W]
00000000_00000000_00000000_00000000
00050034H
HFI (Hc Fm Interval) [R/W]
00000000_00000000_00101110_11011111
00050038H
HFR (Hc Fm Remaining) [R]
00000000_00000000_00000000_00000000
0005003CH
HFN (Hc Fm Number) [R]
00000000_00000000_00000000_00000000
00050040H
HPS (Hc Periodic Start) [R/W]
00000000_00000000_00000000_00000000
00050044H
HLST (Hc LS Threshold) [R/W]
00000000_00000000_00000110_00101000
00050048H
HRDA (Hc Rh Descriptor A) [R/W]
00000001_00000000_00000000_00000010
0005004CH
HRDB (Hc Rh Descriptor B) [R/W]
00000000_00000000_00000000_00000000
00050050H
HRS (Hc Rh Status) [R/W]
00000000_00000000_00000000_000000X0
00050054H
HRPS1 (Hc Rh Port Status[1]) [R/W]
00000000_00000000_00000000_00000X00
00050058H
HRPS2 (Hc Rh Port Status[2]) [R/W]
00000000_00000000_00000000_00000X00
0005005CH
to
00057FFFH
⎯
00058000H
to
00059FFFH
SRAM 8 KB
0005A000H
to
0005FFFFH
⎯
+3
Block
USB
Host
(Continued)
33
MB91310 Series
Address
Register
+0
+1
+2
+3
00060000H
FIFO0o [R]
XXXXXXXX_XXXXXXXX
FIFO0i [W]
XXXXXXXX_XXXXXXXX
00060004H
FIFO1 [R]
XXXXXXXX_XXXXXXXX
FIFO2 [W]
XXXXXXXX_XXXXXXXX
00060008H
FIFO3 [R]
XXXXXXXX_XXXXXXXX
⎯
0006000CH
to
0006001FH
⎯
00060020H
⎯
CONT1 [R/W]
XXXXX0XX_XXX00000
00060024H
CONT2 [R/W]
XXXXXXXX_XXX00000
CONT3 [R/W]
XXXXXXXX_XXX00000
00060028H
CONT4 [R/W]
XXXXXXXX_XXX00000
CONT5 [R/W]
XXXXXXXX_XXXX00XX
0006002CH
CONT6 [R/W]
XXXXXXXX_XXXX00XX
CONT7 [R/W]
XXXXXXXX_XXX00000
00060030H
CONT8 [R/W]
XXXXXXXX_XXX00000
CONT9 [R/W]
XXXX0000_X000000X
00060034H
CONT10 [R/W]
XXXXXXXX_0XXX0000
TTSIZE [R/W]
00010001_00010001
00060038H
TRSIZE [R/W]
00010001_00010001
⎯
USB
Function
⎯
0006003CH
00060040H
RSIZE0 [R]
XXXXXXXX_XXXX0000
⎯
00060044H
RSIZE1 [R]
XXXXXXXX_X0000000
⎯
00060048H
to
0006005FH
00060060H
Block
⎯
ST1 [R/W]
XXXXXX00_00000000
⎯
⎯
00060064H
00060068H
ST2 [R]
XXXXXXXX_XXX00000
ST3 [R/W]
XXXXXXXX_XXX00000
0006006CH
ST4 [R/W]
XXXXX000_00000000
ST5 [R/W]
XXXX0XXX_XX00000000
(Continued)
34
MB91310 Series
Address
Register
+0
+1
00060070H
to
0006007DH
0006007EH
+2
+3
⎯
RESET [R/W]
00000---_--------
00060080H
to
00077FFFH
Block
USB
Function
⎯
⎯
Reserved
00078000H
OSD_VADR [R/W]
XXXXXXXX_XXXXXXXX
OSD_CD1 [R/W]
XXXXXXXX_XXXXXXXX
00078004H
OSD_CD2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_RCD1 [R/W]
XXXXXXXX_XXXXXXXX
00078008H
OSD_RCD2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_SOC1 [R/W]
XXXXXXXX_0000XXXX
0007800CH
OSD_SOC2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_VDPC [R/W]
XXXXXXXX_XXXXXXXX
00078010H
OSD_HDPC [R/W]
XXXXXXXX_XXXXXXXX
OSD_CVSC [R/W]
XXXXXXXX_XXXXXXXX
00078014H
OSD_SBFCC [R/W]
XXXXXXXX_XXXXXXXX
OSD_THCC [R/W]
XXXXXXXX_XXXXXXXX
00078018H
OSD_GFCC [R/W]
XXXXXXXX_XXXXXXXX
OSD_SBCC1 [R/W]
XXXXXXXX_XXXXXXXX
0007801CH
OSD_SBCC2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_SPCC1 [R/W]
XXXXXXXX_XXXXXXXX
00078020H
OSD_SPCC2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_SPCC3 [R/W]
XXXXXXXX_XXXXXXXX
00078024H
OSD_SPCC4 [R/W]
XXXXXXXX_XXXXXXXX
OSD_SYNCC [R/W]
XXXXXXXX_XXXXXXXX
00078028H
OSD_DCLKC1 [R/W]
XXXXXXXX_XXXXXXXX
OSD_DCLKC2 [R/W]
XXXXXXXX_XXXXXXXX
0007802CH
OSD_DCLKC3 [R/W]
XXXXXXXX_XXXXXXXX
OSD_IOC1 [R/W]
XXXXXXXX_XXXXXX00
00078030H
OSD_IOC2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_DPC1 [R/W]
XXXXXXXX_XXXXXXXX
00078034H
OSD_DPC2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_DPC3 [R/W]
XXXXXXXX_XXXXXXXX
00078038H
OSD_DPC4 [R/W]
XXXXXXXX_XXXXXXXX
OSD_IRC [R/W]
XXXXXXXX_XXXXXXXX
OSDC
(Continued)
35
MB91310 Series
(Continued)
Address
Register
+0
+1
+2
+3
0007803CH
OSD_PLT0 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT1 [R/W]
XXXXXXXX_XXXXXXXX
00078040H
OSD_PLT2 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT3 [R/W]
XXXXXXXX_XXXXXXXX
00078044H
OSD_PLT4 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT5 [R/W]
XXXXXXXX_XXXXXXXX
00078048H
OSD_PLT6 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT7 [R/W]
XXXXXXXX_XXXXXXXX
0007804CH
OSD_PLT8 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT9 [R/W]
XXXXXXXX_XXXXXXXX
00078050H
OSD_PLT10 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT11 [R/W]
XXXXXXXX_XXXXXXXX
00078054H
OSD_PLT12 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT13 [R/W]
XXXXXXXX_XXXXXXXX
00078058H
OSD_PLT14 [R/W]
XXXXXXXX_XXXXXXXX
OSD_PLT15 [R/W]
XXXXXXXX_XXXXXXXX
0007805CH
OSD_ACT1 [R/W]
XXXXXXXX_XXXXXXXX
OSD_ACT2 [R/W]
XXXXXXXX_XXXXXXXX
00078060H
to
0007FFFFH
⎯
Block
OSDC
Reserved
*1 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level
reset.
*2 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level
reset by the INIT pin.
36
MB91310 Series
■ INTERRUPT SOURCE, INTERRUPT VECTOR AND INTERRUPT REGISTER ASSIGNMENT
Interrupt source
Interrupt
number
Interrupt
level
Offset
Address of TBR
default
RN
10
16
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
⎯
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
⎯
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
⎯
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
⎯
External interrupt 4 (USB-function)
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5 (USB-Host)
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6 (OSDC)
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
UART0(Reception completed)
27
1B
ICR11
390H
000FFF90H
0
UART1(Reception completed)
28
1C
ICR12
38CH
000FFF8CH
1
UART2(Reception completed)
29
1D
ICR13
388H
000FFF88H
2
UART0 (RX completed)
30
1E
ICR14
384H
000FFF84H
3
UART1 (RX completed)
31
1F
ICR15
380H
000FFF80H
4
UART2 (RX completed)
32
20
ICR16
37CH
000FFF7CH
5
(Continued)
37
MB91310 Series
Interrupt source
Interrupt
number
Interrupt
level
Offset
Address of TBR
default
RN
10
16
DMAC0 (end, error)
33
21
ICR17
378H
000FFF78H
⎯
DMAC1 (end, error)
34
22
ICR18
374H
000FFF74H
⎯
DMAC2 (end, error)
35
23
ICR19
370H
000FFF70H
⎯
DMAC3 (end, error)
36
24
ICR20
36CH
000FFF6CH
⎯
DMAC4 (end, error)
37
25
ICR21
368H
000FFF68H
⎯
A/D
38
26
ICR22
364H
000FFF64H
⎯
PPG0
39
27
ICR23
360H
000FFF60H
⎯
PPG1
40
28
ICR24
35CH
000FFF5CH
⎯
PPG2
41
29
ICR25
358H
000FFF58H
⎯
PPG3
42
2A
ICR26
354H
000FFF54H
⎯
PWC
43
2B
ICR27
350H
000FFF50H
⎯
System reserved
44
2C
ICR28
34CH
000FFF4CH
⎯
System reserved
45
2D
ICR29
348H
000FFF48H
⎯
Main oscillation stabilization
46
2E
ICR30
344H
000FFF44H
⎯
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
⎯
System reserved
48
30
ICR32
33CH
000FFF3CH
⎯
Clock timer
49
31
ICR33
338H
000FFF38H
⎯
I2C ch0
50
32
ICR34
334H
000FFF34H
⎯
I2C ch1
51
33
ICR35
330H
000FFF30H
⎯
2
52
34
ICR36
32CH
000FFF2CH
⎯
2
I C ch3
53
35
ICR37
328H
000FFF28H
⎯
UART3(Reception completed)
54
36
ICR38
324H
000FFF24H
⎯
UART4(Reception completed)
55
37
ICR39
320H
000FFF20H
⎯
UART3 (RX completed)
56
38
ICR40
31CH
000FFF1CH
⎯
UART4(Reception completed)
57
39
ICR41
318H
000FFF18H
⎯
timer0
58
3A
ICR42
314H
000FFF14H
⎯
timer1
59
3B
ICR43
310H
000FFF10H
⎯
timer2
60
3C
ICR44
30CH
000FFF0CH
⎯
timer3
61
3D
ICR45
308H
000FFF08H
⎯
System reserved
62
3E
ICR46
304H
000FFF04H
⎯
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
⎯
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
System reserved
66
42
⎯
2F4H
000FFEF4H
⎯
I C ch2
(Continued)
38
MB91310 Series
(Continued)
Interrupt source
Interrupt
number
Interrupt
level
Offset
Address of TBR
default
RN
10
16
System reserved
67
43
⎯
2F0H
000FFEF0H
⎯
System reserved
68
44
⎯
2ECH
000FFEECH
⎯
System reserved
69
45
⎯
2E8H
000FFEE8H
⎯
System reserved
70
46
⎯
2E4H
000FFEE4H
⎯
System reserved
71
47
⎯
2E0H
000FFEE0H
⎯
System reserved
72
48
⎯
2DCH
000FFEDCH
⎯
System reserved
73
49
⎯
2D8H
000FFED8H
⎯
System reserved
74
4A
⎯
2D4H
000FFED4H
⎯
System reserved
75
4B
⎯
2D0H
000FFED0H
⎯
System reserved
76
4C
⎯
2CCH
000FFECCH
⎯
System reserved
77
4D
⎯
2C8H
000FFEC8H
⎯
System reserved
78
4E
⎯
2C4H
000FFEC4H
⎯
System reserved
79
4F
⎯
2C0H
000FFEC0H
⎯
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
39
MB91310 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Min
Max
VDDE (3.3 V)
Vss − 0.5
Vss + 4.0
V
VDDI (2.5 V)
Vss − 0.5
Vss + 3.0
V
AVCC
Vss − 0.5
Vss + 4.0
V
Input voltage
VI
Vss − 0.5
Vcc + 0.5
V
Analog pin input voltage
VIA
Vss − 0.5
AVcc + 0.5
V
Output voltage
VO
Vss − 0.5
Vcc + 0.5
V
Tstg
− 40
+ 125
°C
Power supply voltage
Analog power supply voltage
Storage temperature
Remarks
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
Parameter
Operating temperature
Power supply voltage
Analog power supply voltage
Symbol
Value
Min
Max
Ta
− 10
+ 70
VDDE (3.3 V)
3.00
3.6
VDDI (2.5 V)
2.30
2.70
AVCC
3.00
3.60
Unit
Remarks
°C
V
V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
40
MB91310 Series
3. DC Characteristics
Parameter
Symbol
ICC
ICCS
ICCL
Power supply
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Conditions
ROM product during
normal operation
Ta = + 25 °C,
fcp = 40 MHz,
fcpp = 20 MHz
Main sleep mode
Ta = + 25 °C,
fcp = 40 MHz,
fcpp = 20 MHz
Value
Min
Main stop mode
Ta = + 25 °C, fclk = 0
⎯
Ta = + 70 °C, fclk = 0
⎯
ICCH
ICCT
H level input
voltage
VIH
L level input
voltage
VIL
H level output
voltage
VOH
L level output
voltage
VOL
Input leak
current
I2C bus switch
connection
resister
IIL
RBS
Clock mode
Ta = + 25 °C,
fclk = 32 kHz
200
250
220
270
MB91FV310A
Dot clock@90 MHz
150
180
MB91F312A
Dot clock PLL STOP
170
200
MB91FV310A
Dot clock PLL STOP
800
1500
MB91F312A
Dot clock PLL stop
USB clock stop
MB91F312A
Dot clock@90 MHz
mA
⎯
⎯
mA
μA
1300
2000
70
150
570
650
500
2000
1000
2500
600
1000
⎯
μA
μA
μA
1100
1500
VCC × 0.8
⎯
VCC
V
VSS
⎯
VCC × 0.2
V
VCC × 0.15
V
VDDE = 3.3 V,
IOH = − 4 mA, *2
VCC − 0.5
⎯
VCC
V
VDDE = 2.5 V,
IOH = − 4 mA, *3
VCC − 0.5
⎯
VCC
V
VDDE = 3.3 V,
IOL = 4 mA, *2, *3
VSS
⎯
0.4
V
Ta = + 70 °C
−5
⎯
+5
μA
⎯
⎯
130
Ω
*1
VCC = 3.3 V, *1
VCC = 2.5 V
⎯
Remarks
Max
⎯
Sub RUN mode
Ta = + 25 °C,
fclk = 32 kHz
Unit
Typ
MB91FV310A
Dot clock PLL stop
USB clock stop
MB91F312A
MB91FV310A
MB91F312A
MB91FV310A
MB91F312A
Dot clock PLL stop
USB clock stop
MB91FV310A
Dot clock PLL stop
USB clock stop
Between SCL3 and SCL4
Between SDA3 and SDA4
*1 : P0 to P7, DOCKI, HSYNC, YSYNC
*2 : P0 to P7
*3 : B0 to B2, G0 to B2, R0 to R2, VOB1, VOB2, DCK0, FH
41
MB91310 Series
4. USB
(1) DC Characteristics
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Symbol
Pin
H level output
voltage
VOH
⎯
IOH = − 100 μA
Output Level
Voltage
VOL
⎯
IOL = 100 μA
Parameter
H level output
current
IOH
⎯
Conditions
Value
Unit Remarks
Min
Typ
Max
VDDE − 0.2
⎯
VDDE
V
0
⎯
0.2
V
Full Speed
VOH = VDDE − 0.4 V
− 20
⎯
⎯
Low Speed
VOH = VDDE − 0.4 V
−6
⎯
⎯
Full Speed
VOL = 0.4 V
20
⎯
⎯
Low Speed
VOL = 0.4 V
6
⎯
⎯
mA
L level output
current
IOL
output short circuit
current
IOS
⎯
⎯
⎯
⎯
300
mA *1
Input leak current
ILZ
⎯
⎯
⎯
⎯
±5
μA
⎯
mA
*2
*1 : About the output short-circuit current IOS
The output short-circuit current IOS is the maximum current that flows when the output pin is connected to VDDE
or VSS (within the maximum rating).
Monitor the short-circuit current
H level
H output
Short-circuited at GND level
3-State Enable "L"
Short-circuited at VDDE level
L level
L output
Monitor the short-circuit current
3-State Enable "L"
About the output short-circuit current: This is the short-circuit current per differential output pin on one side.
As this USB I/O buffer is a differential output, consider both of the two pins.
42
MB91310 Series
*2 : About Z leakage current ILZ measurement
The input leakage current ILZ indicates the leakage current that flows when the VDDE or VSS voltage is applied
to the bidirectional pin with the USB I/O buffer in a high impedance state.
Monitor the leakage current
Z output
0 V, VDD level applied to output pin
3-State Enable "H"
43
MB91310 Series
(2) DC characteristics
Conforming to the USB Specification Revision 1.1.
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Value
Min
Max
Unit
Remarks
“H” level input voltage (driven)
VIH
2.0
⎯
V
*1
“L” level input voltage
VIL
⎯
0.8
V
*1
Diffential Input Sensitivity
VDI
0.2
⎯
V
*2
Differential Common Mode Range
VCM
0.8
2.5
V
*2
“H” level output voltage (driven)
VOH
2.8
3.6
V
*3
“L” level output voltage
VOL
0.0
0.3
V
*3
External Output Signal Crossover Voltage
VCRS
1.3
2.0
V
*4
Bus Pull-Up Resistor on Upstream Port
RPU
1.425
1.575
kΩ
1.5 kΩ ± 5%
Bus Pull-Down Resistor on Downstream Port
RPD
1.425
1.575
kΩ
1.5 kΩ ± 5%
Termination voltage for upstream port pull-up
VTERM
3.0
3.6
V
*5
*1 : About input voltages VIH and VIL
The Single-End-Receiver switching threshold voltage of the USB I/O buffer is set within the range of VIL (Max)
= 0.8 V and VIH (Min) = 2.0 V (TTL input standard).
Appropriate hysteresis is provided to reduce noise sensitivity.
Minimum differential input
sensitivity (V)
*2 : About input voltages VDI and VCM
The Differential-Receiver is used to receive USB differential data signals.
The Differential-Receiver has a differential input sensitivity of 200 mV when the differential data input remains
in the range of 0.8 to 2.5 V to the local ground reference level.
The above voltage range is referred to as the common mode input voltage range.
1.0 (V)
0.2 (V)
0.8 (V)
2.5 (V)
Common mode input voltage(V)
44
MB91310 Series
*3 : About output voltages VOL and VOH
The output drive capabilities of the driver are 0.3 V or less in Low-State (VOL) (when 1.5 kΩ is loaded at 3.6 V)
and 2.8 V or more in High-State (VOH) (when 15 kΩ is loaded at the ground).
*4 : About output voltages VCRS
The cross voltage of the external differential output signal (D+/D-) of the USB I/O buffer ranges from 1.3 V to
2.0 V.
D+
Max 2.0 (V)
VCRS standard range
Min 1.3 (V)
D−
*5 : About termination VTERM
VTERM represents the pull-up voltage at the upstream port.
45
MB91310 Series
5. AC Characteristics
(1) Clock Timing
Parameter
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Symbol
Pin
Conditions
Value
Min
Typ
Max
Unit
PLL system (Operation at a
maximum internal speed of
MHz 40.54 MHz by quadrupling
a self-oscillation frequency
of 10.135 MHz via PLL)
Clock frequency
fc
X0, X1
⎯
⎯
10.135
⎯
Internal operating
clock frequency
fcp
⎯
⎯
2.53
⎯
40.54
MHz
CPU
fcpp
⎯
⎯
2.53
⎯
20.27
MHz
Peripheral
(2) Reset
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
Value
Conditions
INIT input time
(other than at power - on)
tINTL
INIT
⎯
Max
*
⎯
ns
tCP × 5
⎯
ns
*
⎯
ns
INIT input time
(stop recovery time)
* : INIT input time (at power-on)
FAR, CERALOCK : φ × 215 or greater recommended
Crystal
: φ × 221 or greater recommended
φ : Power on → X0/X1 period × 2
tINTL
INIT
Unit
Min
INIT input time
(at power-on)
46
Remarks
0.2 VCC
Remarks
MB91310 Series
(3) UART timing
Parameter
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK↓ → SO delay time
tSLOV
Valid SI →SCK↑
tIVSH
SCK↑ → valid SI hold time
Conditions
Value
Unit Remarks
Min
Max
SCK0 to SCK4
8 tCYCP*
⎯
ns
SCK0 to SCK4
SO0 to SO4
− 80
+ 80
ns
internal shift
SCK0 to SCK4 lock mode
SI0 to SI4
100
⎯
ns
tSHIX
SCK0 to SCK4
SI0 to SI4
60
⎯
ns
Serial clock H pulse width
tSHSL
SCK0 to SCK4
4 tCYCP*
⎯
ns
Serial clock L pulse width
tSLSH
SCK0 to SCK4
4 tCYCP*
⎯
ns
SCK↓ → SO delay time
tSLOV
⎯
150
ns
Valid SI →SCK↑
tIVSH
60
⎯
ns
SCK↑ → valid SI hold time
tSHIX
60
⎯
ns
SCK0 to SCK4
SO0 to SO4 external shift
lock mode
SCK0 to SCK4
SI0 to SI4
SCK0 to SCK4
SI0 to SI4
* : tCYCP indicates the peripheral clock cycle time.
Note : AC characteristic in CLK synchronized mode.
47
MB91310 Series
• Internal shift clock mode
tSCYC
SCK0 to SCK4
VOH
VOL
VOL
tSLOV
VOH
VOL
SO0 το SO4
tIVSH
tSHIX
VOH
VOL
SI0 to SI4
VOH
VOL
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK4
VOL
VOL
VOL
tSLOV
SO0 to SO4
VOH
VOL
tIVSH
SI0 to SI4
48
VOH
VOL
tSHIX
VOH
VOL
MB91310 Series
(4) Reload timer clock, PPG timer input, and multi-function timer input timings
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
Conditions
tTIWH
tTIWL
TIN0 to TIN2
PPG0 to PPG3
TRG0 to TRG3
TI0 to TI3
⎯
Input pulse width
Value
Min
Max
2 tCYCP*
⎯
Unit
Remarks
ns
* : tCYCP indicates the peripheral clock cycle time.
tTIWL
tTIWH
(5) Trigger Input Timing
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
Conditions
A/D activation trigger input
time
tATRG
ATRG
⎯
Value
Min
Max
5 tCYCP*
⎯
Unit
Remarks
ns
* : tCYCP indicates the peripheral clock cycle time.
tATRG
ATRG
49
MB91310 Series
(6) USB interface
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
Conditions
Value
Min
Typ
Max
Unit
X0B, X1B
Input clock
⎯
48 *1
⎯
MHz
UHP/UHM
UDP/UDM
Full Speed
4
⎯
20
ns
*2
UHP/UHM
Low Speed
75
⎯
300
ns
*2
UHP/UHM
UDP/UDM
Full Speed
4
⎯
20
ns
*2
UHP/UHM
Low Speed
75
⎯
300
ns
*2
UHP/UHM
UDP/UDM
Full Speed
90
⎯
111.11
%
*2
UHP/UHM
Low Speed
80
⎯
125
%
*2
UDP
UDM
⎯
28
⎯
44
Ω
*3
X0B
tr
Fall Time
tf
Differential Rise and
Fall Timing Matching
Tfrfm
Driver Output
Resistance
Rzdrv
Fucyc
X0B
UHP
UDP
UHM
UDM
90%
90%
10%
10%
tr
tf
*1 : The AC characteristics of the USB interface conform to the USB Specification Revision 1.1.
*2 : About driver characteristics tr, tf, and Tfrfm
These represent the rise (tr) and fall (tf) time standards of the differential data signal.
These are defined as times between 10% and 90% of the output signal voltage.
For full-speed buffer, the tr/tf ratio is specified to fall within ± 10% to minimize RFI radiation.
50
Self-oscillation
at a precision
of 500 ppm *1
⎯
Fucyc
Rise Time
Remarks
External input
at a precision
of 500 ppm *1
MB91310 Series
*3 : About driver characteristic ZDRV
USB full-speed connection is made by the twisted pair cable shielded at a characteristic impedance (Z0) of
90 Ω ± 15%. The USB Specification stipulates that the USB driver output impedance be within the range of
28 Ω to 44 Ω. The USB Specification also stipulates that a discrete serial resistor (Rs) be added for balancing
purposes while satisfying the above standards.
The output impedance of the USB I/O buffer in this LSI is about 3 Ω to 19 Ω.
As the serial resistor Rs, therefore, a 25 Ω to 30 Ω type (27 Ω type recommended) should be added.
Rs
28 Ω to 44 Ω Equiv. Imped.
T×D+
Rs
T×D−
28 Ω to 44 Ω Equiv. Imped.
3-State
Driver output impedance 3 Ω to 19 Ω
Rs 25 Ω to 30 Ω (recommended value: 27 Ω)
51
MB91310 Series
(7) Analog RGB
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
Conditions
Analog RGB output
delay
tVAD
ROUT,
GOUT,
BOUT
Analog RGB output
settling time
tVAS
ROUT,
GOUT,
BOUT
VREF = 1.1 V,
VDDR = VDDG = VDDB
= 2.5 V,
VRO = 2.7 kΩ,
RCOMP = GCOMP
= BCOMP = 0.1 μF
• Display signal output timing
DOCKI
1 LSB
tVAD
1 LSB
ROUT
GOUT
BOUT
52
tVAS
Value
Unit
Remarks
⎯
ns
⎯
⎯
ns
⎯
Min
Typ
Max
⎯
5
⎯
10
MB91310 Series
(8) Digital RGB
Vertical sync, horizontal sync, and display output control signal input timings
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
Horizontal sync signal cycle time
tHCYC
HSYNC
Horizontal sync signal pulse width
tWH
HSYNC
Horizontal sync signal setup time
tDHST
Horizontal sync signal hold time
tDHHD
Vertical sync signal setup time
tHVST
Vertical sync signal hold time
tHVHD
Input sync signal rise/fall time
tDR
tDF
HSYNC
VSYNC
HSYNC
VSYNC
Value
Unit
Min
Max
100 + tWH
⎯
Dot clock
20
⎯
Dot clock
⎯
6
μs
4
⎯
ns
0
⎯
ns
5
1H*2 − 5
Dot clock
3
⎯
H*2
⎯
5
ns
Remarks
*1
*1 : During the horizontal sync signal pulse period, the device stops its internal OSDC operation, disabling writing
to the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle to ensure
that: horizontal sync signal pulse width < VRAM write cycle.
Precisely, adjust the command issuance interval not to issue command 2 or command 4 (VRAM write command)
more than once in the horizontal sync signal pulse with period.
If the above condition is not satisfied, the device may fail writing to VRAM.
*2 : 1H is assumed to be one horizontal sync signal period.
• Horizontal sync, and display output control signal input timings
0.8 VDD
DOCKI
0.2 VDD
tDHST
tDHHD
0.8 VDD
0.8 VDD
0.2 VDD
0.2 VDD
HSYNC
tDR, tDF
53
MB91310 Series
• Horizontal sync signal input
tHCYC
tDF
0.8 VDD
tWH
tDR
0.8 VDD
0.8 VDD
0.2 VDD
0.2 VDD
HSYNC
• Vertical sync signal input timing
• Leading edge of HSYNC
tDF
tWH
tDR
0.8 VDD
0.8 VDD
0.2 VDD
0.2 VDD
HSYNC
tDF
tHVST
tHVHD
tDR
0.8 VDD
0.8 VDD
0.2 VDD
0.2 VDD
VSYNC
•Trailing edge of HSYNC
tDF
tWH
0.8 VDD
HSYNC
tDR
0.8 VDD
0.2 VDD
tDF
tHVST
0.8 VDD
0.2 VDD
tHVHD
tDR
0.8 VDD
VSYNC
0.2 VDD
54
0.2 VDD
MB91310 Series
Display signal timing
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = 0 V)
Parameter
Symbol
Pin
tDIF
DOCKI
Dot clock input cycle time
tDIWH
Dot clock input pulse width
DOCKI
tDIWL
Dot clock output delay time 1
Unit
Remarks
90
MHz
*1
3.5
⎯
ns
3.5
⎯
ns
Min
Max
11
*1
tPDC
DCKO
3
8
ns
*2
tPDI1
R2 to R0,
B2 to B0,
G2 to G0,
VOB1, VOB2
2
8
ns
*2
tPDO1
R2 to R0,
B2 to B0,
G2 to G0,
VOB1, VOB2
−4
5
ns
*2
Display signal output delay time I1
Display signal output delay time O1
Value
*1 : Input a continuous dot clock signal without a break.
*2 : Output load of 16 pF
• Display signal output timing
tDIF
tDIWH
0.8 VDD
tDIWL
0.8 VDD
0.5 VDD
DOCKI
0.2 VDD
tPDC
tPDC
0.8 VDD
DCKO
tPDO1
0.2 VDD
tPDI1
R2 to R0
G2 to G0
B2 to B0
VOB1, VOB2
0.8 VDD
0.2 VDD
55
MB91310 Series
6. 0.25 μm Technology About the Power-on Sequence for Dual-power-supply Models
• The power supplies must be turned on in the VDDI→AVCC, AVRH→VDDE order and off in the VDDE→AVCC,
AVRH→VDDI order.
When VDDI is turned on earlier, the potential difference between VDDI and VDDE must be within 3.6 V.
• Turn on VDDE before turning on analog power supply AVCC and applying the analog signal.
7. Electrical Characteristics for the A/D Converter
(Ta = − 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 2.5 V ± 0.2 V, Vss = AVSS = 0 V, AVRH = 3.0 V to 3.6 V)
value
Parameter
Resolution
Total error*1
Unit
Min
Typ
Max
⎯
⎯
10
bit
− 5.5
⎯
+ 5.5
LSB
− 3.5
⎯
+ 3.5
LSB
1
− 2.0
⎯
+ 2.0
LSB
Zero transition voltage*1
− 4.0
⎯
+ 6.0
LSB
Full transition voltage*1
AVRH − 5.5
⎯
AVRH + 3.0
LSB
10 *2
⎯
⎯
μs
⎯
3.6
⎯
mA
⎯
⎯
5
μA
Stop converting
Nonlinear error*1
Differential linear error*
Conversion time
Power supply current
(analog + digital)
AVcc = 3.3 V,
AVRH = 3.3 V
(CPU in sleep mode)
Reference power supply current
(between AVRH and AVRL)
⎯
470
⎯
μA
AVRH = 3.0 V, AVRL = 0.0 V
⎯
⎯
10
μA
Stop converting
Analog input capacitance
⎯
40
⎯
pF
Interchannel disparity
⎯
⎯
4
LSB
*1 : Measured in the CPU sleep state
*2 : Depends on the clock cycle of the clock signal supplied to peripheral resources.
Comparator
AN0 to AN9
Analog input pin
RON1
RON2
C0
C1
RON1 = approx. 300 Ω
RON2 = approx. 60 Ω
C0 = approx. 40 pF
C1 = approx. 4 pF
56
Remarks
MB91310 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91F312APFV-1xx-BND-E1
144-pin plastic LQFP
(FPT-144P-M08)
Lead Free Package
MB91FV310APFV-ES
144-pin plastic LQFP
(FPT-144P-M08)
For development tools
57
MB91310 Series
■ PACKAGE DIMENSION
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25 (.010) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
144-pin plastic LQFP
(FPT-144P-M08)
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
58
MB91310 Series
MEMO
59
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
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does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
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nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
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Edited
Strategic Business Development Dept.