FUJITSU SEMICONDUCTOR DATA SHEET DS07-16706-1E 32-bit Microcontroller CMOS FR60 MB91313 Series MB91F313 ■ DESCRIPTION The FR family* is a line of microcontrollers based on a high-performance 32-bit RISC CPU that contains a variety of built-in I/O resources for embedded control applications which require high-performance, high-speed CPU processing. MB91313 series has multiple communication macro channels, suitable for embedded control applications such as TV control. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ FEATURES 1. FR CPU • 32-bit RISC load/store architecture with a five-stage pipeline • Operating frequency 33 MHz (oscillator frequency: 16.5 MHz; oscillator frequency multiplier: 2 (PLL clock multiplication method)) • 16-bit fixed length instructions (basic instructions) • Instruction execution speed : 1 instruction per cycle • Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions : Instructions suitable for embedded applications • Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language • Register interlock functions : Facilitates assembly-language coding (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2007 FUJITSU LIMITED All rights reserved MB91313 Series • On-chip multiplier supported at the instruction level - Signed 32-bit multiplication : 5 cycles - Signed 16-bit multiplication : 3 cycles • Interrupt (PC, PS save) : 6 cycles, 16 priority levels • Harvard architecture enabling program access and data access to be executed simultaneously • Instruction prefetch feature implemented using a 4-word queue in the CPU • Instruction compatible with the FR family 2. Simple External Bus Interface • • • • Function as an 8-bit or 16-bit multiplexed bus through programmatic settings Operating frequency : Max 16.5 MHz Multiplexed I/O for 8/16-bit data/address Capable of chip-select signal output for 4 completely independent areas configurable in minimum units of 64 Kbytes • Basic bus cycle : 3 cycles • Automatic wait cycle generation function to be programmed for each area • Unused data/address/control signal pins can serve as general-purpose I/O 3. Built-in Memory Flash : 544 Kbytes, RAM : 32 Kbytes 4. DMAC (DMA Controller) • • • • • 5 channels Two transfer sources : Internal peripheral/software Addressing modes : 20/24-bit address selectable (increment/decrement/fixed) Transfer modes : Burst transfer/step transfer/block transfer Transfer data size : Selectable from 8, 16, or 32 bits 5. Bit Search Module (for REALOS) Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word 6. 16-bit Reload Timer (Including 1 Channel for REALOS) • 6 channels • Internal clock: Frequency division selectable from 2, 8, and 32 (Continued) 2 MB91313 Series 7. Serial Interface • 11 channels • Full duplex double buffer • Communication mode : Asynchronous (start-stop synchronization) communication, clock synchronous communication (8.25 Mbps Max), I2C* standard mode (100 kbps Max), high-speed mode (400 kbps Max) • Parity on/off selectable • Baud rate generators for each channel • Extensive error detection functions : Parity, frame, and overrun • External clock can be used as transfer clock • Ch.0 to ch.2 : DMA transfers/each equipped with a pair of 16-byte transmit and receive FIFOs • Ch.8 to ch.10 : 5 V tolerant • Ch.8 : Open drain outputs • I2C bridge function (bridges between channels 0, 1, and 2) • SPI mode 8. Interrupt Controller • • • • External interrupt lines: Total of 24 lines (INT23 to INT0) Interrupts from internal peripherals Programmable 16 priority levels Capable of using wakeup from STOP mode 9. 10-bit A/D Converter • • • • 10 channels Successive approximation type : Conversion time : About 7.94 µs Conversion mode : Single-shot conversion mode, scan conversion mode Activation sources : Software/external trigger 10. PPG • • • • • • 4 channels 16-bit down counter, 16-bit data register with cycle setting buffer Internal clock : Frequency division selected from 1, 4, 16, and 64 Support for automatic cycle setting by DMA transfer Function for supporting remote control transmission Open drain outputs 11. PWC • 1 channel (1 input) • 16-bit up counter • Simple digital lowpass filter 12. Multi-function Timer • • • • • • 4 channels Lowpass filter eliminating noise below a pre-set clock frequency Capable of pulse width measurement using seven types of clock signals Pin input event count function Interval timer function using seven types of clock signals and external input clock Internal HSYNC counter mode (Continued) 3 MB91313 Series (Continued) 13. HDMI-CEC/Remote Control Receiver • 2 channels • HDMI-CEC receiver function (with automatic ACK response function) • Remote control receiver function (built-in 4-byte receive buffer) 14. Other Interval Timers • Watch timer (32 kHz, counts up to a maximum of 60 seconds) • Watchdog timer 15. I/O Ports Max 86 ports 16. Other Features • • • • • Internal oscillator circuit as a clock source INITX provided as a reset pin Watchdog timer reset and software reset are available Stop and sleep modes supported as low-power consumption modes Gear function • Time-base timer • 5 V tolerant I/O (some pins) • Package LQFP-120, 0.50 mm pitch, 16.0 mm × 16.0 mm • CMOS technology (0.18µm) • Power supply voltage 3.3 V ± 0.3 V, 1.8 V ± 0.15 V dual power supply * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 4 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS VDDI P23/SIN1 P24/SOT1/SDA1 (I2C bridge) P25/SCK1/SCL1 (I2C bridge) P26/SIN2 P27/SOT2/SDA2 (I2C bridge) P30/SCK2/SCL2 (I2C bridge) P31/TOT0 P32/TOT1 P33/TOT2 P34/TIN0 P35/TIN1 P36/TIN2 P37/RIN P40/TMO0/INT16 P41/TMO1/INT17 P42/TMO2/INT18 P43/TMO3/INT19 P44/TMI0/INT20 P45/TMI1/INT21/SIN10 P46/TMI2/INT22/SOT10/SDA10 P47/TMI3/INT23/SCK10/SCL10 P60/TOT3/TRG2 P61/TOT4/TRG3 P62/TOT5/RDY P63/TIN3/CLK P64/TIN4 P65/TIN5 VDDE VSS PF0/RCIN0 PF1/RCIN1 PF2 PF3 PF4 PF5 PF6 PF7 VDDE VSS AVSS AVRH AVCC PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 PE0/AN8/INT0 PE1/AN9/PPG0/INT1 PE2/PPG1/INT2/ATRG PE3/PPG2/INT3 VDDE INITX X0A X1A 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 VDDE P22/SCK0/SCL0 (I2C bridge) P21/SOT0/SDA0 (I2C bridge) P20/SIN0 P57/WR1X P56/WR0X P55/RDX P54/ASX P53/CS3X/PPG3 P52/CS2X/PPG2 P51/CS1X/PPG1 P50/CS0X/PPG0 P17/AD15 P16/AD14/SCK7/SCL7 P15/AD13/SOT7/SDA7 P14/AD12/SIN7 P13/AD11/SCK6/SCL6 P12/AD10/SOT6/SDA6 P11/AD09/SIN6 P10/AD08/SCK5/SCL5 P07/AD07/SOT5/SDA5/INT15 P06/AD06/SIN5/INT14 P05/AD05/SCK4/SCL4/INT13 P04/AD04/SOT4/SDA4/INT12 P03/AD03/SIN4/INT11 P02/AD02/SCK3/SCL3/INT10 P01/AD01/SOT3/SDA3/INT9 P00/AD00/SIN3/INT8 VDDI VSS MB91313 Series ■ PIN ASSIGNMENT (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDDE IBREAK ICLK ICS2 ICS1 ICS0 ICD3 ICD2 ICD1 ICD0 TRSTX PC7/TRG1 PC6/TRG0 PC5/PPGB PC4/PPGA PC3 PC2/SCK9/SCL9 PC1/SOT9/SDA9 PC0/SIN9 PE7/SCK8/SCL8/INT7 PE6/SOT8/SDA8/INT6 PE5/SIN8/INT5 PE4/PPG3/INT4 MD2 MD1 MD0 VDDI X0 X1 VSS (FPT-120P-M21) 5 MB91313 Series ■ PIN DESCRIPTION Pin no. Pin name I/O circuit type* 1 VSS ⎯ GND pin 2 VDDI ⎯ 1.8 V power supply pin 3 4 5 6 7 8 9 10 11 12 13 14 15 P23 SIN1 P24 2 SOT1/SDA1 (I C bridge) P25 SCK1/SCL1 (I2C bridge) P26 SIN2 P27 SOT2/SDA2 (I2C bridge) P30 2 SCK2/SCL2 (I C bridge) P31 TOT0 P32 TOT1 P33 TOT2 P34 TIN0 P35 TIN1 P36 TIN2 P37 RIN D L L D L L D D D D D D D P40 16 TMO0 INT16 Description General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin General-purpose port Reload timer output pin General-purpose port Reload timer output pin General-purpose port Reload timer output pin General-purpose port Event input pin for reload timer General-purpose port Event input pin for reload timer General-purpose port Event input pin for reload timer General-purpose port PWC input pin General-purpose port B Multi-function timer output pin External interrupt request input pin (Continued) 6 MB91313 Series Pin no. Pin name I/O circuit type* P41 17 TMO1 General-purpose port B INT17 TMO2 General-purpose port B INT18 TMO3 General-purpose port B INT19 TMI0 General-purpose port B INT20 TMI1 INT21 General-purpose port B SIN10 TMI2 INT22 B INT23 B 25 26 Multi-function timer input pin External interrupt request input pin Serial communication clock I/O pin/I2C clock I/O pin P60 TOT3 External interrupt request input pin General-purpose port SCK10/SCL10 24 Multi-function timer input pin Serial data output pin/I2C data I/O pin P47 TMI3 External interrupt request input pin General-purpose port SOT10/SDA10 23 Multi-function timer input pin Serial data input pin P46 22 Multi-function timer input pin External interrupt request input pin P45 21 Multi-function timer output pin External interrupt request input pin P44 20 Multi-function timer output pin External interrupt request input pin P43 19 Multi-function timer output pin External interrupt request input pin P42 18 Description General-purpose port C Reload timer output pin TRG2 PPG trigger input pin P61 General-purpose port TOT4 C Reload timer output pin TRG3 PPG trigger input pin P62 General-purpose port TOT5 RDY C Reload timer output pin External ready input pin (Continued) 7 MB91313 Series Pin no. Pin name I/O circuit type* P63 27 TIN3 General-purpose port C CLK 28 29 P64 TIN4 P65 TIN5 Description Event input pin for reload timer External clock output pin C C General-purpose port Event input pin for reload timer General-purpose port Event input pin for reload timer 30 VDDE ⎯ 3.3 V power supply pin 31 VSS ⎯ GND pin 32 33 PF0 RCIN0 PF1 RCIN1 D D General-purpose port HDMI-CEC/Remote control 0 I/O pin General-purpose port HDMI-CEC/Remote control 1 I/O pin 34 PF2 D General-purpose port 35 PF3 D General-purpose port 36 PF4 D General-purpose port 37 PF5 D General-purpose port 38 PF6 D General-purpose port 39 PF7 D General-purpose port 40 VDDE ⎯ 3.3 V power supply pin 41 VSS ⎯ GND pin 42 AVSS ⎯ A/D converter GND pin 43 AVRH ⎯ A/D converter reference voltage pin 44 AVCC ⎯ A/D converter power supply pin 45 46 47 48 49 50 PD0 AN0 PD1 AN1 PD2 AN2 PD3 AN3 PD4 AN4 PD5 AN5 L L L L L L General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin (Continued) 8 MB91313 Series Pin no. 51 52 Pin name PD6 AN6 PD7 AN7 I/O circuit type* L L PE0 53 54 55 AN8 General-purpose port A/D converter analog input pin General-purpose port A/D converter analog input pin General-purpose port L A/D converter analog input pin INT0 External interrupt request input pin PE1 General-purpose port AN9 PPG0 L A/D converter analog input pin PPG output pin INT1 External interrupt request input pin PE2 General-purpose port PPG1 INT2 B ATRG PPG2 PPG output pin External interrupt request input pin A/D converter trigger input pin PE3 56 Description General-purpose port B INT3 PPG output pin External interrupt request input pin 57 VDDE ⎯ 3.3 V power supply 58 INITX G Initial reset pin 59 X0A A Sub clock input pin 60 X1A A Sub clock output pin 61 VSS ⎯ GND pin 62 X1 A Main clock output pin 63 X0 A Main clock input pin 64 VDDI ⎯ 1.8 V power supply pin 65 MD0 F Mode pin 66 MD1 F Mode pin 67 MD2 F Mode pin PE4 68 69 PPG3 General-purpose port B PPG output pin INT4 External interrupt request input pin PE5 General-purpose port SIN8 INT5 B Serial data input pin External interrupt request input pin (Continued) 9 MB91313 Series Pin no. Pin name I/O circuit type* PE6 70 71 SOT8/SDA8 General-purpose port B 73 74 75 76 77 78 79 Serial data output pin/I2C data I/O pin INT6 External interrupt request input pin PE7 General-purpose port SCK8/SCL8 B INT7 72 Description PC0 SIN9 PC1 SOT9/SDA9 PC2 SCK9/SCL9 PC3 PC4 PPGA PC5 PPGB PC6 TRG0 PC7 TRG1 Serial communication clock I/O pin/I2C clock I/O pin External interrupt request input pin B B B B B B B B General-purpose port Serial data input pin General-purpose port Serial data output pin/I2C data I/O pin General-purpose port Serial communication clock I/O pin/I2C clock I/O pin General-purpose port General-purpose port PPG output pin General-purpose port PPG output pin General-purpose port PPG trigger input pin General-purpose port PPG trigger input pin 80 TRSTX G Development tool reset pin 81 ICD0 K Development tool data pin 82 ICD1 K Development tool data pin 83 ICD2 K Development tool data pin 84 ICD3 K Development tool data pin 85 ICS0 H Development tool status pin 86 ICS1 H Development tool status pin 87 ICS2 H Development tool status pin 88 ICLK H Development tool clock pin 89 IBREAK I Development tool break pin 90 VDDE ⎯ 3.3 V power supply pin 91 VSS ⎯ GND pin 92 VDDI ⎯ 1.8 V power supply pin (Continued) 10 MB91313 Series Pin no. Pin name I/O circuit type* P00 93 94 95 AD00 SIN3 General-purpose port O P01 General-purpose port AD01 SOT3/SDA3 O P02 General-purpose port AD02 SCK3/SCL3 O AD03 SIN4 AD04 SOT4/SDA4 SCK4/SCL4 O O O SCK5/SCL5 Serial communication clock I/O pin/I2C clock I/O pin General-purpose port O External address/data bus I/O pin Serial data input pin External interrupt request input pin General-purpose port O External address/data bus I/O pin Serial data output pin/I2C data I/O pin External interrupt request input pin P10 AD08 External address/data bus I/O pin External interrupt request input pin INT15 101 Serial data output pin/I2C data I/O pin General-purpose port P07 SOT5/SDA5 External address/data bus I/O pin External interrupt request input pin INT14 AD07 Serial data input pin General-purpose port P06 SIN5 External address/data bus I/O pin External interrupt request input pin INT13 AD06 Serial communication clock I/O pin/I2C clock I/O pin General-purpose port P05 AD05 External address/data bus I/O pin External interrupt request input pin INT12 100 Serial data output pin/I2C data I/O pin External interrupt request input pin P04 99 External address/data bus I/O pin INT9 INT11 98 Serial data input pin External interrupt request input pin P03 97 External address/data bus I/O pin INT8 INT10 96 Description General-purpose port O External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin (Continued) 11 MB91313 Series Pin no. Pin name I/O circuit type* P11 102 103 AD09 General-purpose port O Serial data input pin P12 General-purpose port AD10 O AD11 General-purpose port O P14 106 General-purpose port O Serial data input pin P15 General-purpose port AD13 O AD14 General-purpose port O AD15 O P50 109 CS0X C C General-purpose port C PPG2 CS3X General-purpose port C PPG3 113 P54 ASX External chip select pin PPG output pin P53 112 External chip select pin PPG output pin P52 CS2X External chip select pin General-purpose port PPG1 111 External address/data bus I/O pin PPG output pin P51 CS1X General-purpose port General-purpose port PPG0 110 External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin SCK7/SCL7 P17 External address/data bus I/O pin Serial data output pin/I2C data I/O pin P16 108 External address/data bus I/O pin SIN7 SOT7/SDA7 107 External address/data bus I/O pin Serial communication clock I/O pin/I2C clock I/O pin SCK6/SCL6 AD12 External address/data bus I/O pin Serial data output pin/I2C data I/O pin P13 105 External address/data bus I/O pin SIN6 SOT6/SDA6 104 Description External chip select pin PPG output pin C General-purpose port External address strobe output pin (Continued) 12 MB91313 Series (Continued) Pin no. 114 115 116 117 Pin name P55 RDX P56 WR0X P57 WR1X P20 SIN0 I/O circuit type* C C C D P21 118 SOT0/SDA0 (I2C bridge) Description General-purpose port External read strobe output pin General-purpose port External data bus write strobe output pin General-purpose port External data bus write strobe output pin General-purpose port Serial data input pin General-purpose port L P22 Serial data output pin/I2C data I/O pin General-purpose port 119 SCK0/SCL0 (I2C bridge) L 120 VDDE ⎯ Serial communication clock I/O pin/I2C clock I/O pin 3.3 V power supply pin * : For the details of the I/O circuit types. Refer to “■ I/O CIRCUIT TYPE”. 13 MB91313 Series ■ I/O CIRCUIT TYPE Type Circuit type Remarks X1, X1A Clock input A Oscillator circuit Internal feedback resistance X0 : 1 MΩ X0A : No X0, X0A Standby control P-ch Digital output Digital output B • CMOS level output IOH = 4 mA • CMOS level hysteresis input VIH = 0.7 × VDDE • With standby control • 5 V tolerant N-ch Digital input Standby control Pull-up control P-ch P-ch Digital output C Digital output • CMOS level output IOH = 4 mA • CMOS level hysteresis input VIH = 0.8 × VDDE • With standby control • With pull-up control • With pull-up resistor (33 kΩ) N-ch Digital input Standby control (Continued) 14 MB91313 Series Type Circuit type Remarks P-ch Digital output Digital output D • CMOS level output IOH = 4 mA • CMOS level hysteresis input VIH = 0.8 × VDDE With standby control Without pull-up resistor N-ch Digital input Standby control • CMOS level input • Without standby control P-ch F N-ch Digital input P-ch • CMOS hysteresis input • With pull-up resistor P-ch G N-ch Digital input CMOS level output P-ch Digital output H Digital output N-ch (Continued) 15 MB91313 Series Type Circuit type Remarks • CMOS hysteresis input • With pull-down resistor • Without standby control P-ch I N-ch N-ch Digital input P-ch Digital output K • • • • CMOS level output CMOS level input Without standby control With pull-down resistor • • • • CMOS level output CMOS level hysteresis input With standby control Analog input with switch Digital output N-ch N-ch Digital input P-ch Digital output Digital output N-ch L Analog input Control Digital input Standby control (Continued) 16 MB91313 Series (Continued) Type Circuit type Remarks Pull-up control P-ch P-ch Digital output Digital output O N-ch • CMOS level output IOH = 4 mA • CMOS input (external bus interface) CMOS level hysteresis input (port, resource) VIH = 0.8 × VDDE • With standby control • With pull-up control • With pull-up resistor (33 kΩ) Port input Resource input External bus input Standby control 17 MB91313 Series ■ HANDLING DEVICES • Preventing latch-up Latch-up may occur in a CMOS IC if a voltage higher than VDDE or VDDI, or less than VSS is applied to an input or output pin or if a voltage exceeding the rating is applied between VDDE and VSS, or VDDI and VSS. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. • Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor. • Power supply pins In MB91313 series, devices including multiple of VDDE pins, VDDI pins and VSS pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pin and GND pin must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the VDDE pins, VDDI pins and VSS pins of the MB91313 series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between VDDE pins, VDDI pins and VSS pins near this device. • Crystal oscillator circuit Noise in proximity to the X0 and X1 (X0A, X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board artwork be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. • Mode pins (MD0 to MD2) When using mode pins, connect them directly to power supply pin or GND pin. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or GND pin on the printed circuit board as possible and connect them with low impedance. • Operation at power-on Ensure that the INITX pin is reset and the settings are initialized (INIT) immediately after the power is turned on. Maintain the “L” level input to the INITX pin during the stabilization wait time immediately after the power on to ensure the stabilization wait time as required by the oscillator circuit (the stabilization wait time is reset to the minimum value when INIT is asserted using the INITX pin). • Note on oscillator input at power-on At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed. 18 MB91313 Series • Notes on the turning on/off VDDI pin (1.8 V internal power supply) and VDDE pin (3.3 V external pin power supply) Do not apply only VDDE pin (external power supply) voltage continuously (more than one minute) while the VDDI pin (internal power supply) is disconnected as it will adversely affect the reliability of the LSI. When the VDDE pin (external power supply) returns from the off state to the on state, the circuit may not be able to maintain its internal state, for example, due to power supply noise. Power on VDD pin (internal power supply) → VDDE pin (external power supply) → Analog→ Signal Power off Signal → Analog→ VDDE pin (external power supply) → VDDI pin (internal power supply) When the power is turned on, the states of the output pins may remain undefined until the internal power supply becomes stable. • Notes on using an external clock When using the external clock as a general rule you should simultaneously supply X0 (X0A) and X1 (X1A) pins. And also, the clock signal to X0 (X0A) should be supplied a clock signal with the reverse phase to X1 (X1A) pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the X1 (X1A) pin stops at “H” output in STOP mode). Furthermore, supply a clock to X0 (X0A) pin only if the device is operating in less than 12.5 MHz. Using an External Clock (Normal Method) X0, X0A X1, X1A MB91313 series Cannot be used in STOP mode (oscillation stop mode). Using an External Clock (available at 12.5 MHz or less) X0, X0A Open X1, X1A MB91313 series Note : When operating at a frequency of 10 MHz, the delay between the X0 (X0A) and X1 signals should be less than 15 ns. 19 MB91313 Series • AVCC pin The MB91313 has a built-in A/D converter. A capacitor of approximately 0.1µF must be connected between the AVCC pin and AVSS pin. AVCC 0.1µF MB91313 series AVSS • Notes when not using the emulator To operate the evaluation MCU on the user system without connecting the emulator, treat each input pin on the evaluation MCU connected to the emulator interface on the user system as shown below. Note that switching circuits or other measures may be needed on the user system. Emulator Interface Pin Treatment Evaluation MCU Pin Name Pin Connection TRSTX Connect to the reset output circuit on the user system. INITX Connect to the reset output circuit on the user system. Other Pins Open • Notes on selecting PLL clocks If the crystal oscillator is disconnected or the clock input stops while the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit within the PLL. However, this operation is not guaranteed. 20 MB91313 Series ■ RESTRICTIONS 1) Clock control block When an “L” level is input to the INITX pin, ensure that it is maintained for the duration of the oscillation stabilization wait time. 2) Bit Search Module The bit search data register for 0-detection (BSD0), bit search data register for 1-detection (BSD1), and bit search data register for change point detection (BSDC) can be accessed in word. 3) I/O Ports Ports can only be accessed in byte. 4) Low Power Consumption Mode • To place the device in standby mode, use the synchronous standby mode (set with bit 8 (SYNCS bit) of the timebase counter control register, TBCR) and be sure to use the following sequence : (LDI#value_of_standby, r0) (LDI#_STCR, R12) STB R0, @R12 LDUB @R12, R0 LDUB @R12, R0 NOP NOP NOP NOP NOP ; value_of_standby is the data to write to STCR ; _STCR is the address of STCR (481H) ; Write to the standby control register (STCR) ; Read STCR for synchronous standby ; Perform an additional dummy read of STCR ; 5 × NOP for timing adjustment • Do not perform any of the following actions when using the monitor debugger. • Set a breakpoint within the sequence of instructions shown above • Perform step execution of the sequence of instructions shown above 21 MB91313 Series 5) Notes on the PS register Some instructions write to the PS register in advance before executing. When a debugger is being used, execution may break within an interrupt handler routine, or the values of the flags within the PS register may be updated due to exception processing. However, the microcontroller is designed to reprocess correctly after returning from the EIT, and to execute before and after the EIT proceeds according to the specifications. • In any following situation, the previous instructions before a DIV0U or DIV0S instruction may take the processing in (1) to (3). - A user interrupt or NMI is accepted - Step execution is performed - A break occurs due to a data event or by being selected from the emulator menu (1) The D0 and D1 flags are updated in advance. (2) The EIT handling routine (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the DIV0U or DIV0S instruction is executed and the D0/D1 flags are updated back to the same value as in step (1). • If any of the OR CCR, ST ILM, or MOV Ri, PS instructions are executed to enable a user interrupt or NMI interrupt source when that interrupt has occurred, the following operation will be performed. (1) The PS register is updated in advance. (2) The EIT handling routine (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS registers are updated back to the same value as in step (1). 6) Watchdog timer The watchdog timer has a function to monitors the program to check that it delays a reset within a certain period of time, and resets the CPU if the program runs out of control and fails to delay the reset. Once the watchdog timer has been enabled, it keeps running until reset. As an exception, the reset is automatically delayed in conditions where the execution of the CPU program stops. It is possible that the watchdog timer will not be triggered if these conditions arise as a result of the system running out of control. In that case, please reset (INIT) using the external INITX pin. 7) Notes on using the A/D converter Do not supply a voltage higher than the VDDE pin to the AVCC pin. 8) Software reset in synchronous mode When using the software reset in synchronous mode, the following two conditions should be satisfied before setting the SRST bit in STCR (standby control register) to “0”. • The interrupt enable flag (I-Flag) is set to interrupts disabled (I-Flag = 0) . • The NMI is not being used. 22 MB91313 Series ■ BLOCK DIAGRAM FR CPU CORE 32 Flash 544 Kbytes 32 Bit search module RAM 32 Kbytes Bus converter 32 ↔ 16 adapter DMAC 5 channels Simple external bus I/F 8/16-bit multiplexed bus Clock control Interrupt controller UART/SIO/I2C 11 channels A/D converter 10 channels HDMI-CEC/ Remote control receiver 2 channel External interrupt Ports PWC 1 channel PPG 4 channels Reload timer 6 channels Multifunction timer 4 channels 23 MB91313 Series ■ CPU AND CONTROL UNIT Internal architecture The FR family of CPUs is a line of high-performance cores providing advanced instructions for embedded applications based on the RISC architecture. 1. Features • RISC architecture Basic instructions : Execute at one instruction per cycle • 32-bit architecture General purpose registers : 32 bits × 16 • 4 Gbytes of linear memory space • Built-in multiplier 32-bit × 32-bit multiplication : 5 cycles 16-bit × 16-bit multiplication : 3 cycles • Enhanced interrupt servicing High-speed response (6 cycles) Multi-level interrupt support Level mask feature (16 levels) • Enhanced I/O manipulation instructions Memory-to-memory transfer instructions Bit manipulation instructions • Basic instruction word length : 16 bits • Lower-power consumption Sleep mode/stop mode Gear function 24 MB91313 Series 2. Internal architecture The FR family of CPUs uses a Harvard architecture in which the instruction bus and data bus are separated. A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the CPU and peripheral resources. A Harvard ↔ Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller. FRex CPU D-bus I-bus 32 I address External address 32 Harvard I data External data D address 32 Data RAM 32-bit 16-bit bus converter 24 D data Princeton bus converter 16 32 Address 32 Data 32 16 R-bus Peripheral resources F-bus Internal I/O Bus converter 25 MB91313 Series 3. Programming model 32 bits [Initial Value] R0 XXXX XXXXH R1 ... ... ... General purpose registers 26 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Program status PS TBR RP System stack pointer SSP User stack pointer USP Multiplication and division register ... R13 PC Return pointer ... ... R12 Program counter Table base register ... ... MDH MDL ILM SCR CCR MB91313 Series 4. Register • General-purpose registers 32 bits [Initial Value] R0 XXXX XXXXH R1 ... ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Registers R0 to R15 are general-purpose registers. These registers are used as the accumulator and memory access pointers in CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced. • R13 : Virtual accumulator (AC) • R14 : Frame pointer (FP) • R15 : Stack pointer (SP) The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value). • PS (Program Status) This register holds the program status and is divided into the ILM, SCR, and CCR. All undefined bits are reserved bits. Reading these bits always returns 0. Writing to them has no effect. bit 31 bit 20 bit 16 ILM bit 10 bit 8 bit 7 SCR bit 0 CCR 27 MB91313 Series • CCR (Condition Code Register) bit 7 S I N Z V C bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 S I N Z V C bit 10 bit 9 bit 8 D1 D0 T [Initial Value] --00XXXXB : Stack flag : Interrupt Enable flag : Negative flag : Zero flag : Overflow flag : Carrying flag • SCR (System Condition Code Register) [Initial Value] XX0B D1, D0 : Flag for step division This flag stores interim data during execution of step multiplication. T : Step trace trap flag This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. This function therefore cannot be used within a user program when an emulator is being used. • ILM (Interrupt Level Mask Register) bit 20 bit 19 bit 18 bit 17 bit 16 [Initial Value] ILM4 ILM3 ILM2 ILM1 ILM0 01111B This register stores the value of the interrupt level mask, with the value stored in the ILM used as the interrupt level mask. The register is initialized to “01111B” on reset. 28 MB91313 Series • PC (Program Counter) bit 31 bit 0 [Initial Value] XXXXXXXXH The program counter indicates the address of the instruction that is being executed. The initial value on reset is undefined. • TBR (Table Base Register) bit 31 bit 0 [Initial Value] 000FFC00H The table base register stores the starting address of the vector table used for EIT processing. The initial value on reset is 000FFC00H. • RP (Return Pointer) bit 31 bit 0 [Initial Value] XXXXXXXXH The return pointer stores the address to return from a subroutine. When the CALL instruction is executed, the value of the PC is transferred to the RP register. When the RET instruction is executed, the value of the RP is transferred to the PC register. The initial value on reset is undefined. • SSP (System Stack Pointer) bit 31 bit 0 [Initial Value] 00000000H The SSP is the system stack pointer. The SSP functions as R15 when the S flag is “0”. The SSP can be explicitly specified. The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs. The initial value after a reset is 00000000H. 29 MB91313 Series • USP (User Stack Pointer) bit 31 bit 0 [Initial Value] XXXXXXXXH The USP is the user stack pointer. The USP functions as R15 when the S flag is “1”. The USP can be explicitly specified. The initial value after a reset is indeterminate. This pointer cannot be used by the RETI instruction. • MDH, MDL (Multiplication and Division Registers) bit 31 bit 0 MDH MDL These registers are used for multiplications and divisions and are each 32 bits long. The initial value after a reset is indeterminate. 30 MB91313 Series ■ MEMORY SPACE 1. Memory space The FR family has 4 Gbytes of logical address space (232 addresses) linearly accessible to the CPU. Direct Addressing Areas The following areas in the address space are used as I/O areas. These areas are called direct addressing areas. The addresses of operands in these areas can be specified directly within some instructions. The direct addressing area varies depending on the size of data to be accessed as follows : → Byte data access : 000H to 0FFH → Half word data access : 000H to 1FFH → Word data access : 000H to 3FFH 2. Memory Map Single chip mode Internal ROM external bus mode I/O I/O I/O I/O Access prohibited Access prohibited Internal RAM 32 Kbytes Internal RAM 32 Kbytes 00000000H 00000400H 00010000H 00038000H 00040000H Access prohibited Direct addressing area Refer to “ ■ I/O MAP”. Access prohibited 00050000H 00078000H External area Internal Flash 544 Kbytes 00100000H 00200000H 007FFFFFH FFFFFFFFH Access prohibited Internal Flash 544 Kbytes Access prohibited External area Access prohibited 31 MB91313 Series ■ I/O MAP The following table shows the correspondence between the memory space area and each of the peripheral resource registers. [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit Port data register Read/Write attribute Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 1) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data. Note : The bit values in the register represent the following initial values : • “1” : Initial value “1” • “0” : Initial value “0” • “X” : Initial value “Undefined” • “-” : No physical register at this location Access is prohibited for data access attributes that are not listed. 32 MB91313 Series Address Register 0 1 2 3 000000H PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX 000004H PDR4 [R/W] XXXXXXXX PDR5 [R/W] XXXXXXXX PDR6 [R/W] --XXXXXX Reserved Reserved 000008H 00000CH PDRC [R/W] XXXXXXXX PDRD [R/W] XXXXXXXX 000010H to 00001CH 000020H PDRE [R/W] XXXXXXXX ADCTL[R/W] 00000000 Reserved ADCH[R/W] 00000000 00000000 000024H ADAT0[R] XXXXXX00 00000000 ADAT1[R] XXXXXX00 00000000 000028H ADAT2[R] XXXXXX00 00000000 ADAT3[R] XXXXXX00 00000000 00002CH ADAT4[R] XXXXXX00 00000000 ADAT5[R] XXXXXX00 00000000 000030H ADAT6[R] XXXXXX00 00000000 ADAT7[R] XXXXXX00 00000000 000034H ADAT8[R] XXXXXX00 00000000 ADAT9[R] XXXXXX00 00000000 000038H, 00003CH Port data register PDRF [R/W] XXXXXXXX Reserved ADCTH[R/W] 00000000 Block Reserved 10-bit A/D converter Reserved 000040H EIRR0 [R/W] 00000000 ENIR0 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 External interrupt 0 to 7 000044H DICR [R/W] -------0 HRCL [R, R/W] ---11111 Reserved Delayed/I-unit TMRLR0 [W] XXXXXXXX XXXXXXXX TMR0 [R] XXXXXXXX XXXXXXXX 00004CH Reserved TMCSR0 [R, RW] 00000000 00000000 000050H TMRLR1 [W] XXXXXXXX XXXXXXXX TMR1 [R] XXXXXXXX XXXXXXXX 000054H Reserved TMCSR1 [R, RW] 00000000 00000000 000058H TMRLR2 [W] XXXXXXXX XXXXXXXX TMR2 [R] XXXXXXXX XXXXXXXX 00005CH Reserved TMCSR2 [R, RW] 00000000 00000000 000048H Reload timer 0 Reload timer 1 Reload timer 2 (Continued) 33 MB91313 Series Address 000060H 000064H Register 0 1 2 3 SCR0 [R, R/W] 0--00000 SMR0 [W, R/W] 000-0000 SSR0 [R, R/W] 0-000011 ESCR0 [R/W] --000000 BGR01 [R/W] 00000000 BGR00 [R/W] 00000000 FCR01 [R/W] 00-00100 FCR00 [R/W] 00000000 RDR0/TRD0 [R/W] -------- 00000000 : RDR0 -------- 11111111 : TRD0 000068H ISMK0 [R/W] 01111110 IBSA [R/W] 00000000 00006CH FBYTE01 [R/W] 00000000 FBYTE00 [R/W] 00000000 000070H SCR1 [R, R/W] 0--00000 SMR1 [W, R/W] 000-0000 000074H RDR1/TRD1 [R/W] -------- 00000000 : RDR1 -------- 11111111 : TRD1 000078H ISMK1 [R/W] 01111110 IBSA1 [R/W] 00000000 00007CH FBYTE11 [R/W] 00000000 FBYTE10 [R/W] 00000000 000080H SCR2 [R, R/W] 0--00000 SMR2 [W, R/W] 000-0000 000084H RDR2/TRD2 [R/W] -------- 00000000 : RDR2 -------- 11111111 : TRD2 000088H ISMK2 [R/W] 01111110 IBSA2 [R/W] 00000000 00008CH FBYTE21 [R/W] 00000000 FBYTE20 [R/W] 00000000 000090H SCR3 [R, R/W] 0--00000 SMR3 [W, R/W] 000-0000 000094H 000098H RDR3/TRD3 [R/W] -------- 00000000 : RDR3 -------- 11111111 : TRD3 ISMK3 [R/W] 01111110 0000A0H 0000A4H 0000A8H 0000ACH Serial interface 0 FIFO 0 Reserved SSR1 [R, R/W] 0-000011 ESCR1 [R/W] --000000 BGR11 [R/W] 00000000 BGR10 [R/W] 00000000 FCR11 [R/W] 00-00100 FCR10 [R/W] 00000000 Serial interface 1 FIFO 1 Reserved SSR2 [R, R/W] 0-000011 ESCR2 [R/W] --000000 BGR21 [R/W] 00000000 BGR20 [R/W] 00000000 FCR21 [R/W] 00-00100 FCR20 [R/W] 00000000 Serial interface 2 Reserved SSR3 [R, R/W] 0-000011 ESCR3 [R/W] --000000 BGR31 [R/W] 00000000 BGR30 [R/W] 00000000 IBSA3 [R/W] 00000000 00009CH Block Serial interface 3 Reserved Reserved SCR4 [R, R/W] 0--00000 SMR4 [W, R/W] 000-0000 RDR4/TRD4 [R/W] -------- 00000000 : RDR4 -------- 11111111 : TRD4 ISMK4 [R/W] 01111110 SSR4 [R, R/W] 0-000011 ESCR4 [R/W] --000000 BGR41 [R/W] 00000000 BGR40 [R/W] 00000000 IBSA4 [R/W] 00000000 Serial interface 4 Reserved Reserved (Continued) 34 MB91313 Series Address 0000B0H 0000B4H 0000B8H Register 0 1 2 3 SCR5 [R, R/W] 0--00000 SMR5 [W, R/W] 000-0000 SSR5 [R, R/W] 0-000011 ESCR5 [R/W] --000000 BGR51 [R/W] 00000000 BGR50 [R/W] 00000000 RDR5/TRD5 [R/W] -------- 00000000 : RDR5 -------- 11111111 : TRD5 ISMK5 [R/W] 01111110 IBSA5 [R/W] 00000000 0000BCH Block Serial interface 5 Reserved Reserved 0000C0H EIRR1 [R/W] 00000000 ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 External interrupt 8 to 15 0000C4H EIRR2 [R/W] 00000000 ENIR2 [R/W] 00000000 ELVR2 [R/W] 00000000 00000000 External interrupt 16 to 23 0000C8H, 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH Reserved PWCCL[R/W] 0000--00 PWCCH[R/W] 00-00000 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH Reserved PWCD[R] XXXXXXXX XXXXXXXX Reserved PWC PWCC2[R/W] 000----- Reserved PWCUD[R/W] XXXXXXXX XXXXXXXX 0000E0H to 0000ECH 0000F0H Reserved Reserved Reserved T0LPCR [R/W] -----000 T0CCR [R/W] 0-000000 T0DRR [R/W] XXXXXXXX XXXXXXXX T1LPCR [R/W] -----000 T1CCR [R/W] 0-000000 T1DRR [R/W] XXXXXXXX XXXXXXXX T2LPCR [R/W] -----000 T2CCR [R/W] 0-000000 T2DRR [R/W] XXXXXXXX XXXXXXXX T3LPCR [R/W] -----000 T3CCR [R/W] 0-000000 T3DRR [R/W] XXXXXXXX XXXXXXXX Reserved T0TCR [R/W] 00000000 T0R [R/W] ---00000 T0CRR [R/W] XXXXXXXX XXXXXXXX T1TCR [R/W] 00000000 T1R [R/W] ---00000 T1CRR [R/W] XXXXXXXX XXXXXXXX T2TCR [R/W] 00000000 T2R [R/W] ---00000 Multi-function timer T2CRR [R/W] XXXXXXXX XXXXXXXX T3TCR [R/W] 00000000 T3R [R/W] ---00000 T3CRR [R/W] XXXXXXXX XXXXXXXX (Continued) 35 MB91313 Series Address 000110H Register 0 1 2 TMODE [R/W] 00000000 00000000 000114H to 00011CH 3 Reserved Reserved 000120H PDUT0[W] XXXXXXXX XXXXXXXX 000124H PTMR0[R] 11111111 11111111 000128H PDUT1[W] XXXXXXXX XXXXXXXX 00012CH PTMR1[R] 11111111 11111111 000130H PDUT2[W] XXXXXXXX XXXXXXXX 000134H PTMR2[R] 11111111 11111111 000138H PDUT3[W] XXXXXXXX XXXXXXXX 00013CH PTMR3[R] 11111111 11111111 000140H, 000144H PCSR0[W] XXXXXXXX XXXXXXXX PCNH0[R/W] 0000000- PCNL0[R/W] 000000-0 PCSR1[W] XXXXXXXX XXXXXXXX PCNH1[R/W] 0000000- PCNL1[R/W] 000000-0 PCSR2[W] XXXXXXXX XXXXXXXX PCNH2[R/W] 0000000- PCNL2[R/W] 000000-0 PCSR3[W] XXXXXXXX XXXXXXXX PCNH3[R/W] 0000000- PCNL3[R/W] 000000-0 Reserved 00014CH Reserved TMCSR3 [R, RW] 00000000 00000000 000150H TMRLR4 [W] XXXXXXXX XXXXXXXX TMR4 [R] XXXXXXXX XXXXXXXX 000154H Reserved TMCSR4 [R, RW] 00000000 00000000 000158H TMRLR5 [W] XXXXXXXX XXXXXXXX TMR5 [R] XXXXXXXX XXXXXXXX Reserved TMCSR5 [R, RW] 00000000 00000000 000160H to 00017CH Reserved PPG0 PPG1 PPG2 PPG3 Reserved TMR3 [R] XXXXXXXX XXXXXXXX 00015CH Multi-function timer Reserved TMRLR3 [W] XXXXXXXX XXXXXXXX 000148H Block Reload timer 3 Reload timer 4 Reload timer 5 Reserved (Continued) 36 MB91313 Series Address Register 0 1 2 3 000180H RCCR0 [R/W] 0---0000 RCST0 [R/W] 00000000 RCSHW0 [R/W] 00000000 RCDAHW0 [R/W] 00000000 000184H RCDBHW0 [R/W] 00000000 Reserved RCADR01 [R/W] 00000000 RCADR02 [R/W] 00000000 000188H RCDT0HH [R] 00000000 RCDT0HL [R] 00000000 RCDT0LH [R] 00000000 RCDT0LL [R] 00000000 00018CH RCCKD0 [R/W] 00000000 00000000 RCCR1 [R/W] 0---0000 RCST1 [R/W] 00000000 RCSHW1 [R/W] 00000000 RCDAHW1 [R/W] 00000000 000194H RCDBHW1 [R/W] 00000000 Reserved RCADR11 [R/W] 00000000 RCADR12 [R/W] 00000000 000198H RCDT1HH [R] 00000000 RCDT1HL [R] 00000000 RCDT1LH [R] 00000000 RCDT1LL [R] 00000000 RCCKD1 [R/W] 00000000 00000000 0001A0H to 0001ACH 0001B0H 0001B4H 0001B8H SMR6 [W, R/W] 000-0000 RDR6/TRD6 [R/W] -------- 00000000 : RDR6 -------- 11111111 : TRD6 ISMK6 [R/W] 01111110 0001C0H 0001C4H 0001C8H 0001CCH Reserved SSR6 [R, R/W] 0-000011 ESCR6 [R/W] --000000 BGR61 [R/W] 00000000 BGR60 [R/W] 00000000 IBSA6 [R/W] 00000000 0001BCH Remote controller 1 Reserved Reserved SCR6 [R, R/W] 0--00000 Remote controller 0 Reserved 000190H 00019CH Block Serial interface 6 Reserved Reserved SCR7 [R, R/W] 0--00000 SMR7 [W, R/W] 000-0000 RDR7/TRD7 [R/W] -------- 00000000 : RDR7 -------- 11111111 : TRD7 ISMK7 [R/W] 01111110 SSR7 [R, R/W] 0-000011 ESCR7 [R/W] --000000 BGR71 [R/W] 00000000 BGR70 [R/W] 00000000 IBSA7 [R/W] 00000000 Serial interface 7 Reserved Reserved (Continued) 37 MB91313 Series Address 0001D0H 0001D4H 0001D8H Register 0 1 2 3 SCR8 [R, R/W] 0--00000 SMR8 [W, R/W] 000-0000 SSR8 [R, R/W] 0-000011 ESCR8 [R/W] --000000 BGR81 [R/W] 00000000 BGR80 [R/W] 00000000 RDR8/TRD8 [R/W] -------- 00000000 : RDR8 -------- 11111111 : TRD8 ISMK8 [R/W] 01111110 IBSA8 [R/W] 00000000 0001DCH 0001E0H 0001E4H 0001E8H 0001F4H 0001F8H Serial interface 8 Reserved Reserved SCR9 [R, R/W] 0--00000 SMR9 [W, R/W] 000-0000 RDR9/TRD9 [R/W] -------- 00000000 : RDR9 -------- 11111111 : TRD9 ISMK9 [R/W] 01111110 SSR9 [R, R/W] 0-000011 ESCR9 [R/W] --000000 BGR91 [R/W] 00000000 BGR90 [R/W] 00000000 IBSA9 [R/W] 00000000 0001ECH 0001F0H Block Serial interface 9 Reserved Reserved SCRA[R, R/W] 0--00000 SMRA [W, R/W] 000-0000 RDRA/TRDA [R/W] -------- 00000000 : RDRA -------- 11111111 : TRDA ISMKA [R/W] 01111110 SSRA [R, R/W] 0-000011 ESCRA[R/W] --000000 BGRA1 [R/W] 00000000 BGRA0 [R/W] 00000000 IBSAA [R/W] 00000000 Serial interface 10 Reserved 0001FCH Reserved 000200H DMACA0 [R/W] 00000000 00000000 00000000 00000000 000204H DMACB0 [R/W] 00000000 00000000 00000000 00000000 000208H DMACA1 [R/W] 00000000 00000000 00000000 00000000 00020CH DMACB1 [R/W] 00000000 00000000 00000000 00000000 000210H DMACA2 [R/W] 00000000 00000000 00000000 00000000 000214H DMACB2 [R/W] 00000000 00000000 00000000 00000000 000218H DMACA3 [R/W] 00000000 00000000 00000000 00000000 00021CH DMACB3 [R/W] 00000000 00000000 00000000 00000000 000220H DMACA4 [R/W] 00000000 00000000 00000000 00000000 DMAC (Continued) 38 MB91313 Series Address Register 0 1 2 3 000224H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000228H to 00023CH Reserved 000240H DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX 000244H to 0003ECH Reserved 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMAC Reserved Bit search module 000400H DDR0 [R/W] 00000000 DDR1 [R/W] 00000000 DDR2 [R/W] 00000000 DDR3 [R/W] 00000000 000404H DDR4 [R/W] 00000000 DDR5 [R/W] 00000000 DDR6 [R/W] --000000 Reserved 000408H 00040CH Data direction register Reserved DDRC [R/W] 00000000 DDRD [R/W] 00000000 DDRE [R/W] 00000000 000410H Reserved 000414H to 00041CH Reserved DDRF [R/W] 00000000 Reserved 000420H PFR0 [R/W] 00000000 PFR1 [R/W] 00000000 PFR2 [R/W] 00000000 PFR3 [R/W] 00000000 000424H PFR4 [R/W] 00000000 PFR5 [R/W] 00000000 PFR6 [R/W] --000000 Reserved 000428H 00042CH Port function register Reserved PFRC [R/W] 00000000 PFRD [R/W] 00000000 PFRE [R/W] 00000000 000430H Reserved 000434H to 00043CH Reserved Block PFRF [R/W] 00000000 Reserved (Continued) 39 MB91313 Series Address Register 0 1 2 3 000440H ICR00 [R, R/W] ---11111 ICR01 [R, R/W] ---11111 ICR02 [R, R/W] ---11111 ICR03 [R, R/W] ---11111 000444H ICR04 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 000448H ICR08 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 00044CH ICR12 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 000450H ICR16 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 000454H ICR20 [R, R/W] ---11111 ICR21 [R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 000458H ICR24 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 00045CH ICR28 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 000460H ICR32 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 000464H ICR36 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 000468H ICR40 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 00046CH ICR44 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 ICR47 [R, R/W] ---11111 000470H to 00047CH Reserved RSRR [R, R/W] 10000000 STCR [R/W] 00110011 TBCR [R/W] 00XXXX00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] 00000000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 OSCCR [R/W] XXXXXXX0 Reserved Reserved 00048CH WPCR [R/W] 00000000 000490H OSCR [R/W] 00000000 000494H to 0004FCH Reserved OSCT [R/W] XXXXXXXX Reserved Interrupt control unit Reserved 000480H 000488H Block Clock control unit Clock timer Reserved Stabilization wait timer Reserved (Continued) 40 MB91313 Series Address Register 0 1 2 000500H PCR0 [R/W] 00000000 PCR1 [R/W] 00000000 000504H Reserved PCR5 [R/W] 00000000 3 Reserved PCR6 [R/W] --000000 000508H to 000510H Reserved 000514H to 00051CH Reserved Reserved EPFR0 [R/W] 00000000 EPFR1 [R/W] 00000000 EPFR2 [R/W] 11111111 EPFR3 [R/W] 11111111 000524H EPFR4 [R/W] 11111111 EPFR5 [R/W] 11111111 EPFR6 [R/W] --001000 Reserved 00052CH Reserved EPFRC [R/W] 00000000 EPFRD [R/W] 00000000 EPFRE [R/W] 00000000 000530H Reserved 000534H to 00056CH Reserved 000570H ADER[R/W] 00000011 11111111 000574H 000578H Reserved Reserved 00057CH to 00063CH Reserved I2C Noise filter Reserved 000640H ASR0 [R/W] 00000000 00000000 ACR0 [R/W] 00110X00 00000000 000644H ASR1 [R/W] 00000000 XXXXXXXX ACR1 [R/W] 00XX0X00 00X0XXXX 000648H ASR2 [R/W] 00000000 XXXXXXXX ACR2 [R/W] 00XX0X00 00X0XXXX 00064CH ASR3 [R/W] 00000000 XXXXXXXX ACR3 [R/W] 00XX0X00 00X0XXXX 000660H EXT/I2C/ A/D Reserved Reserved 000650H to 00065CH External port function register EPFRF [R/W] 00000000 Reserved NSF[R/W] -----000 00000000 Port pull-up control registers Reserved 000520H 000528H Block External bus interface Reserved AWR0 [R/W] 01110000 01011011 AWR1 [R/W] 0XXX0000 0X0X1XXX (Continued) 41 MB91313 Series Address 000664H Register 0 3 Reserved CSER[R/W] 00000001 External bus interface Reserved Reserved 000688H to 0007F8H Reserved Reserved Block AWR3 [R/W] 0XXX0000 0X0X1XXX 000684H 0007FCH 42 2 AWR2 [R/W] 0XXX0000 0X0X1XXX 000668H to 00067CH 000680H 1 MODR [W] XXXXXXXX Unused Reserved ⎯ 000800H to 000AFCH Reserved Unused 000B00H to 000FFCH Reserved Reserved 001000H DMASA0 [R/W] 00000000 00000000 00000000 00000000 001004H DMADA0 [R/W] 00000000 00000000 00000000 00000000 001008H DMASA1 [R/W] 00000000 00000000 00000000 00000000 00100CH DMADA1 [R/W] 00000000 00000000 00000000 00000000 001010H DMASA2 [R/W] 00000000 00000000 00000000 00000000 001014H DMADA2 [R/W] 00000000 00000000 00000000 00000000 001018H DMASA3 [R/W] 00000000 00000000 00000000 00000000 00101CH DMADA3 [R/W] 00000000 00000000 00000000 00000000 001020H DMASA4 [R/W] 00000000 00000000 00000000 00000000 001024H DMADA4 [R/W] 00000000 00000000 00000000 00000000 001028H to 006FFCH Reserved DMAC Reserved MB91313 Series (Continued) Address Register 0 1 2 007000H FLCR[R/W] 0000X000 Reserved 007004H FLWC[R/W] 00011011 Reserved 3 Block Flash I/F 43 MB91313 Series ■ VECTOR TABLE Interrupt source Interrupt number Decimal Hexadecimal Interrupt level Offset DMAC TBR default DMA STOP transfer address source Reset 0 00 ⎯ 3FCH 000FFFFCH ⎯ ⎯ Mode vector 1 01 ⎯ 3F8H 000FFFF8H ⎯ ⎯ System reserved 2 02 ⎯ 3F4H 000FFFF4H ⎯ ⎯ System reserved 3 03 ⎯ 3F0H 000FFFF0H ⎯ ⎯ System reserved 4 04 ⎯ 3ECH 000FFFECH ⎯ ⎯ System reserved 5 05 ⎯ 3E8H 000FFFE8H ⎯ ⎯ System reserved 6 06 ⎯ 3E4H 000FFFE4H ⎯ ⎯ Coprocessor absent trap 7 07 ⎯ 3E0H 000FFFE0H ⎯ ⎯ Coprocessor error trap 8 08 ⎯ 3DCH 000FFFDCH ⎯ ⎯ INTE instruction 9 09 ⎯ 3D8H 000FFFD8H ⎯ ⎯ System reserved 10 0A ⎯ 3D4H 000FFFD4H ⎯ ⎯ System reserved 11 0B ⎯ 3D0H 000FFFD0H ⎯ ⎯ Step trace trap 12 0C ⎯ 3CCH 000FFFCCH ⎯ ⎯ NMI request (tool) 13 0D ⎯ 3C8H 000FFFC8H ⎯ ⎯ Undefined instruction exception 14 0E ⎯ 3C4H 000FFFC4H ⎯ ⎯ System reserved 15 0F 15 (FH) fixed 3C0H 000FFFC0H ⎯ ⎯ External interrupt 0 16 10 ICR00 3BCH 000FFFBCH ⎯ ⎯ External interrupt 1 17 11 ICR01 3B8H 000FFFB8H ⎯ ⎯ External interrupt 2 18 12 ICR02 3B4H 000FFFB4H ⎯ ⎯ External interrupt 3 19 13 ICR03 3B0H 000FFFB0H ⎯ ⎯ External interrupt 4 20 14 ICR04 3ACH 000FFFACH ⎯ ⎯ External interrupt 5 21 15 ICR05 3A8H 000FFFA8H ⎯ ⎯ External interrupt 6 22 16 ICR06 3A4H 000FFFA4H ⎯ ⎯ External interrupt 7 23 17 ICR07 3A0H 000FFFA0H ⎯ ⎯ Reload timer 0 24 18 ICR08 39CH 000FFF9CH ⎯ ⎯ Reload timer 1 25 19 ICR09 398H 000FFF98H ⎯ ⎯ Reload timer 2 26 1A ICR10 394H 000FFF94H ⎯ ⎯ UART0 RX/I2C status 27 1B ICR11 390H 000FFF90H STOP UART0 TX 28 1C ICR12 38CH 000FFF8CH ⎯ UART1 RX/I C status 29 1D ICR13 388H 000FFF88H STOP UART1 TX 30 1E ICR14 384H 000FFF84H ⎯ UART2 RX/I2C status 31 1F ICR15 380H 000FFF80H STOP UART2 TX 32 20 ICR16 37CH 000FFF7CH ⎯ 33 21 ICR17 378H 000FFF78H 2 2 UART3 RX/TX/I C status ⎯ ⎯ (Continued) 44 MB91313 Series Interrupt source Interrupt number Decimal Hexadecimal Interrupt level Offset DMAC TBR default DMA STOP transfer source address UART4 RX/TX/I2C status 34 22 ICR18 374H 000FFF74H ⎯ ⎯ UART5 RX/TX/I2C status 35 23 ICR19 370H 000FFF70H ⎯ ⎯ 2 36 24 ICR20 36CH 000FFF6CH ⎯ ⎯ 2 37 25 ICR21 368H 000FFF68H ⎯ ⎯ 2 UART8 RX/TX/I C status 38 26 ICR22 364H 000FFF64H ⎯ ⎯ UART9 RX/TX/I2C status 39 27 ICR23 360H 000FFF60H ⎯ ⎯ UART10 RX/TX/I2C status 40 28 ICR24 35CH 000FFF5CH ⎯ ⎯ A/D converter 41 29 ICR25 358H 000FFF58H ⎯ ⎯ PPG0 42 2A ICR26 354H 000FFF54H PWC 43 2B ICR27 350H 000FFF50H ⎯ ⎯ HDMI-CEC/Remote controller 0, 1 44 2C ICR28 34CH 000FFF4CH ⎯ ⎯ Watch timer 45 2D ICR29 348H 000FFF48H ⎯ ⎯ Main oscillation wait 46 2E ICR30 344H 000FFF44H ⎯ ⎯ Timebase timer 47 2F ICR31 340H 000FFF40H ⎯ ⎯ Reload timer 3 48 30 ICR32 33CH 000FFF3CH ⎯ ⎯ Reload timer 4 49 31 ICR33 338H 000FFF38H ⎯ ⎯ Reload timer 5 50 32 ICR34 334H 000FFF34H ⎯ ⎯ PPG1 51 33 ICR35 330H 000FFF30H ⎯ PPG2 52 34 ICR36 32CH 000FFF2CH ⎯ PPG3 53 35 ICR37 328H 000FFF28H ⎯ DMAC0 54 36 ICR38 324H 000FFF24H ⎯ ⎯ DMAC1 55 37 ICR39 320H 000FFF20H ⎯ ⎯ DMAC2 56 38 ICR40 31CH 000FFF1CH ⎯ ⎯ DMAC3 57 39 ICR41 318H 000FFF18H ⎯ ⎯ DMAC4 58 3A ICR42 314H 000FFF14H ⎯ ⎯ External interrupt 8 to 15 59 3B ICR43 310H 000FFF10H ⎯ ⎯ External interrupt 16 to 23 60 3C ICR44 30CH 000FFF0CH ⎯ ⎯ Multi-function timer 0, 1 61 3D ICR45 308H 000FFF08H ⎯ ⎯ Multi-function timer 2, 3 62 3E ICR46 304H 000FFF04H ⎯ ⎯ Delay interrupt 63 3F ICR47 300H 000FFF00H ⎯ ⎯ System reserved (Used by REALOS) 64 40 ⎯ 2FCH 000FFEFCH ⎯ ⎯ System reserved (Used by REALOS) 65 41 ⎯ 2F8H 000FFEF8H ⎯ ⎯ System reserved 66 42 ⎯ 2F4H 000FFEF4H ⎯ ⎯ UART6 RX/TX/I C status UART7 RX/TX/I C status ⎯ (Continued) 45 MB91313 Series (Continued) Interrupt source 46 Interrupt number Decimal Hexadecimal Interrupt level Offset DMAC TBR default DMA STOP transfer source address System reserved 67 43 ⎯ 2F0H 000FFEF0H ⎯ ⎯ System reserved 68 44 ⎯ 2ECH 000FFEECH ⎯ ⎯ System reserved 69 45 ⎯ 2E8H 000FFEE8H ⎯ ⎯ System reserved 70 46 ⎯ 2E4H 000FFEE4H ⎯ ⎯ System reserved 71 47 ⎯ 2E0H 000FFEE0H ⎯ ⎯ System reserved 72 48 ⎯ 2DCH 000FFEDCH ⎯ ⎯ System reserved 73 49 ⎯ 2D8H 000FFED8H ⎯ ⎯ System reserved 74 4A ⎯ 2D4H 000FFED4H ⎯ ⎯ System reserved 75 4B ⎯ 2D0H 000FFED0H ⎯ ⎯ System reserved 76 4C ⎯ 2CCH 000FFECCH ⎯ ⎯ System reserved 77 4D ⎯ 2C8H 000FFEC8H ⎯ ⎯ System reserved 78 4E ⎯ 2C4H 000FFEC4H ⎯ ⎯ System reserved 79 4F ⎯ 2C0H 000FFEC0H ⎯ ⎯ Used by INT instruction 80 to 255 50 to FF ⎯ 2BCH to 000H 000FFEBCH to 000FFC00H ⎯ ⎯ MB91313 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Min Max VDDE (3.3 V) Vss − 0.5 Vss + 4.0 V VDDI (1.8 V) Vss − 0.3 Vss + 2.5 V AVCC Vss − 0.5 Vss + 4.0 V AVRH Vss − 0.5 Vss + 4.0 V Vss − 0.5 VDDE + 0.5 V Vss − 0.5 Vss + 6.0 V VIA Vss − 0.5 AVcc + 0.5 V VO Vss − 0.5 VDDE + 0.5 V IOL ⎯ 8 mA “L” level average output current*3 IOLAV ⎯ 4 mA “L” level total maximum output current ΣIOL ⎯ 60 mA ΣIOLAV ⎯ 30 mA IOH ⎯ −8 mA “H” level average output current*3 IOHAV ⎯ −4 mA “H” level total maximum output current ΣIOH ⎯ − 60 mA ΣIOHAV ⎯ − 30 mA Power consumption PD ⎯ 300 mW Storage temperature Tstg − 40 + 125 °C Power supply voltage*1 Analog power supply voltage*1 Input voltage*1 VI Analog pin input voltage* Output voltage* 1 1 “L” level maximum output current*2 “L” level total average output current*4 “H” level maximum output current*2 “H” level total average output current*4 Remarks 5 V tolerant pin *1 : This parameter is based on VSS = AVSS = 0.0 V *2 : The maximum output current is the peak value for a single pin. *3 : The average output current is the average current for a single pin over a period of 100 ms. *4 : The total average output current is the average current for all pins over a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 47 MB91313 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol Value Unit Min Max Ta − 40 + 85 VDDE (3.3 V) 3.0 3.6 VDDI (1.8 V) 1.65 1.95 Analog power supply voltage AVCC 3.0 VDDE V 5 V tolerant pin input voltage VI ⎯ VSS + 5.5 V Operating temperature Power supply voltage °C V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 48 MB91313 Series 3. DC Characteristics (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter Symbol Pin name ⎯ ICCT ⎯ ⎯ ICC Current Consumption (upper : 1.8 V lower : 3.3 V) ⎯ ⎯ ICCS ⎯ ⎯ ICCL ⎯ ⎯ ⎯ ICCH ⎯ ⎯ “H” level input voltage VIH P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P65, PD0 to PD7, PE0, PE1, PF0 to PF7 Conditions “L” level input voltage VIL Unit Min Typ Max Clock mode Ta = + 25 °C, fclk = 32 kHz ⎯ 200 400 ⎯ 100 300 During normal operation Ta = + 25 °C, fcp = 33 MHz, fcpp = 33 MHz ⎯ 55 80 ⎯ 25 40 Main sleep mode Ta = + 25 °C, fcp = 33 MHz, fcpp = 33 MHz ⎯ 30 50 ⎯ 15 30 Sub RUN mode Ta = + 25 °C, fclk = 32 kHz ⎯ 250 450 ⎯ 150 400 Main Stop mode Ta = + 25 °C, fclk = 0 ⎯ 150 300 ⎯ 40 80 Main Stop mode Ta = + 70 °C, fclk = 0 ⎯ 400 800 ⎯ 100 200 VDDE × 0.8 ⎯ VDDE V VDDE × 0.7 ⎯ VDDE V VSS ⎯ VDDE × 0.2 V VSS ⎯ VDDE × 0.3 V µA mA mA µA µA µA VDDE = 3.3 V PE2 to PE7, PC0 to PC7, P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P65, PD0 to PD7, PE0, PE1, PF0 to PF7 Value VDDE = 3.3 V PE2 to PE7, PC0 to PC7, P40 to P47 “H” level output voltage VOH All port pins VDDE = 3.3 V, IOH = − 4 mA VDDE − 0.5 ⎯ VDDE V “L” level output voltage VOL All port pins VDDE = 3.3 V, IOL = 4 mA VSS ⎯ 0.4 V (Continued) 49 MB91313 Series (Continued) Parameter Input leak current (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = − 40 °C to + 85 °C) Symbol IIL Pin name Other than PD0 to PD7, PE0, PE1 Conditions ⎯ PD0 to PD7, PE0, PE1 Pull-up/ Pull-down resistance I2C bus switch connection resistance 50 RP Pull-up : P00 to P07, P10 to P17, P50 to P57, P60 to P65, INITX, TRSTX Pull-down : ICD0 to ICD3, IBREAK RBS Between P21 and P24 Between P22 and P25 Between P24 and P27 Between P25 and P30 Pull-up : VIL = 0 V Pull-down : VIH = VDDE ⎯ Value Unit Min Typ Max −5 ⎯ +5 µA − 10 ⎯ + 10 µA 10 33 80 kΩ ⎯ ⎯ 130 Ω MB91313 Series 4. AC Characteristics (1) Clock Timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter Symbol Clock frequency Sub clock frequency Pin name Value Conditions Min Max Unit Remarks fC X0, X1 ⎯ 10 16.5 33 PLL clock (self-oscillation 16.5 MHz doubled via MHz PLL : internal operation at 33 MHz max.) fclk X0A, X1A ⎯ ⎯ 32.768 ⎯ kHz ⎯ ⎯ 33 MHz CPU ⎯ ⎯ 33 MHz Peripheral ⎯ ⎯ 16.5 fCP Internal operating clock frequency Typ ⎯ fCPP ⎯ fCPT MHz External bus (2) Clock Output Timing (VDDE = AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = − 40 °C to + 85 °C) Symbol Pin name Cycle time tCYC CLK CLK ↑ → CLK ↓ tCHCL CLK CLK ↓ → CLK ↑ tCLCH CLK Parameter Value Conditions ⎯ Unit Remarks Min Max 60.7 ⎯ ns *1 1/2 × tCYC − 5 1/2 × tCYC + 5 ns *2 1/2 × tCYC − 5 1/2 × tCYC + 5 ns *3 *1 : tCYC is the frequency of one clock cycle after gearing. *2 : These ratings are for the gear ratio set to × 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. (1/2 × 1/n) × tCYC − 10 *3 : These ratings are for the gear ratio set to × 1. tCYC tCHCL CLK VOH tCLCH VOH VOL (3) PLL Oscillation Stabilization Wait Time (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter Symbol PLL oscillation stabilization wait time tLOCK Value Min Max 600 ⎯ Unit Remarks µs The length of time to wait for the PLL oscillations to stabilize. 51 MB91313 Series (4) Reset Input (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter Symbol Pin name INITX input time (at power-on) INITX input time (other than power-on) INITX input time (Stop recovery time) tINTL INITX Value Conditions Max Oscillation stabilization delay time of oscillator + tcp × 10 ⎯ µs tcp × 10 ⎯ ns Oscillation stabilization delay time of oscillator + tcp × 10 ⎯ µs ⎯ tINTL INITX 52 Unit Min 0.2 VCC MB91313 Series (5) Normal Access Read/Write Operation (VDDE = AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = − 40 °C to + 85 °C) Parameter Symbol Pin name tCSLCH CS0X to CS3X setup tCSDLCH CLK CS0X to CS3X Conditions Value Unit Max AWRxL : WO2 = 0 3 ⎯ ns *1 AWRxL : WO2 = 1 −3 ⎯ ns *1 3 1/2 × tCYC + 6 ns 3 ⎯ ns 3 1/2 × tCYC + 6 ns ⎯ 6 ns ⎯ 6 ns CS0X to CS3X hold tCHCSH Address setup time tASCH Address hold time tCHAX WR0X, WR1X delay time tCHWL WR0X, WR1X delay time tCHWH CLK WR0X, WR1X WR0X, WR1X minimum pulse width tWLWH WR0X, WR1X 12 ⎯ ns Data setup → WRxX ↑ tDSWH tCYC ⎯ ns WRxX ↑ → Data hold time tWHDX WR0X, WR1X AD15 to AD00 3 ⎯ ns RDX delay time tCHRL ⎯ 6 ns RDX delay time tCHRH ⎯ 6 ns RDX ↓ → Valid data input time tRLDV ⎯ tCYC − 30 ns Data setup → RDX ↑ Time tDSRH 30 ⎯ ns RDX ↑ → Data hold time tRHDX 0 ⎯ ns RDX minimum pulse width tRLRH RDX 12 ⎯ ns ASX setup tASLCH 3 ⎯ ns ASX hold tASHCH CLK ASX 3 1/2 × tCYC + 6 ns CLK AD15 to AD00 CLK RDX RDX AD15 to AD00 Remarks Min ⎯ *2 *1 : AWRxL : Area Wait Register *2 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of cycles added for the delay) to this rating. 53 MB91313 Series (6) Multiplexed Bus Access Read/Write Operation (VDDE = 3.3 ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Symbol AD15 to AD00 address setup time → CLK ↑ tASCH CLK ↑→ AD15 to AD00 address setup time tCHAX AD15 to AD00 address setup time → ASX ↑ tASASH ASX ↑→ AD15 to AD00 address setup time tASHAX Pin name Conditions Value Max 3 ⎯ ns 3 1/2 × tCYC + 6 ns 12 ⎯ ns * tCYC − 3 tCYC + 3 ns * CLK AD15 to AD00 ⎯ ASX AD15 to AD00 * : CSxX → RDX/WRxX setup extension = 1 Note : Use the same rating as normal bus interface except for this rating. 54 Unit Remarks Min MB91313 Series • CSxX → RDX/WRxX setup extension = 1 tCYC BA1 BA2 BA1W BA3 CLK tASLCH tASHCH ASX tASASH tASHAX tCSLCH CS0X to CS3X tASCH AD15 to AD00 tCHAX Address Read data tDSRH tRHDX tRLDV RDX tRLRH tCHRH tCHRL AD15 to AD00 Address Write data tDSWH tWHDX WR0X, WR1X tWLWH tCHWL tCHWH 55 MB91313 Series • CSxX → RDX/WRxX setup extension = 0 tCYC BA1 BA2 BA3 CLK ASX tASLCH tASHCH tCSLCH CS0X to CS3X tASCH AD15 to AD00 tCHAX Address Read data tDSRH tRHDX tRLDV RDX tRLRH tCHRH tCHRL AD15 to AD00 Address Write data tDSWH tWHDX WR0X, WR1X tWLWH tCHWL 56 tCHWH MB91313 Series (7) Ready Input Timings (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Symbol Pin name Conditions RDY setup time → CLK ↓ tRDYS CLK, RDY CLK ↓ → RDY hold time tRDYH CLK, RDY Value Unit Min Max ⎯ 25 ⎯ ns ⎯ 0 ⎯ ns tCYC CLK VOH VOH VOL VOL tRDYS tRDYH RDY wait applied RDY wait not applied tRDYS tRDYH VOH VOL VOH VOL VOH VOH VOL VOL 57 MB91313 Series (8) UART timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK ↓ → SOT delay time Conditions Unit Min Max SCK0 to SCK10 4 tCYCP ⎯ ns tSLOV SCK0 to SCK10 SOT0 to SOT10 − 20 + 20 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK10 SIN0 to SIN10 30 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK10 SIN0 to SIN10 20 ⎯ ns Serial clock “H” pulse width tSHSL SCK0 to SCK10 2 tCYCP ⎯ ns Serial clock “L” pulse width tSLSH SCK0 to SCK10 2 tCYCP ⎯ ns SCK ↓ → SOT delay time tSLOV SCK0 to SCK10 SOT0 to SOT10 ⎯ 30 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK10 SIN0 to SIN10 20 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK10 SIN0 to SIN10 20 ⎯ ns Internal shift clock operation External shift clock operation Notes : • The above standards apply to the CLK synchronous mode. • tCYCP indicates the peripheral clock cycle time. 58 Value MB91313 Series • Internal shift clock mode tSCYC SCK0 to SCK10 VOH VOL VOL tSLOV VOH VOL SOT0 to SOT10 tIVSH tSHIX VOH VOL SIN0 to SIN10 VOH VOL • External shift clock mode tSLSH SCK0 to SCK10 tSHSL VOL VOL VOH VOH tSLOV SOT0 to SOT10 VOH VOL tIVSH SIN0 to SIN10 VOH VOL tSHIX VOH VOL 59 MB91313 Series (9) Reload timer clock, PPG timer input, multi-function timer input timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Input pulse width Symbol Pin name Conditions tTIWH tTIWL TIN0 to TIN5 TRG0 to TRG3 ⎯ Value Min Max 2 tCYCP ⎯ Unit ns Note : tCYCP is the cycle time of the peripheral clock. TIN0 to TIN5 TRG0 to TRG3 tTIWH tTIWL (10) Trigger Input Timing (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter A/D activation trigger input time Symbol Pin name Conditions tATRG ATRG ⎯ Note : tCYCP is the cycle time of the peripheral clock. tATRG ATRG 60 Value Min Max 5 tCYCP ⎯ Unit ns MB91313 Series (11) Remote control signal input timing (VDDE = 3.3 V + 0.3 V, VDDI = 1.8 V + 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Remote control input pulse width Symbol Pin name tRCIN RCIN0 RCIN1 Value Conditions At 32.768 kHz Min Max 62 ⎯ Unit Parameter µs Count 2 clocks or more tRCIN RCIN0 RCIN1 61 MB91313 Series (12) I2C timing • When operating in master mode (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Symbol Conditions High-speed mode*1 Typical mode Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz “L” period of SCL clock tLOW 4.7 ⎯ 1.3 ⎯ µs “H” period of SCL clock tHIGH 4.0 ⎯ 0.6 ⎯ µs Bus free time between “STOP condition” and “START condition” tBUS 4.7 ⎯ 1.3 ⎯ µs SCL ↓ → SDA output delay time tDLDAT ⎯ 5 × M*3 ⎯ 5 × M*3 ns “Repeated START condition” setup time SCL ↑ → SDA ↓ tSUSTA 4.7 ⎯ 0.6 ⎯ µs “Repeated START condition” hold time SDA ↓ → SCL ↓ tHDSTA 4.0 ⎯ 0.6 ⎯ µs “STOP condition” setup time SCL ↑ → SDA ↑ tSUSTO 4.0 ⎯ 0.6 ⎯ µs SDA data input hold time (vs. SCL ↓) tHDDAT 2 × M*3 ⎯ 2 × M*3 ⎯ µs SDA data input setup time (vs. SCL ↑) tSUDAT 250 ⎯ 100*4 ⎯ ns R = 1 kΩ, C = 50 pF*2 Remarks The first clock pulse is generated after this. *1 : For use at over 100 kHz, set the resource clock to 6 MHz or higher. *2 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. *3 : M = Resource clock cycle (ns) *4 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of “tSUDAT ≥ 250 ns”. When a device does not extend the “L” period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) from when the SCL line is released. 62 MB91313 Series • When operating in slave mode (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Symbol Conditions Typical mode High-speed mode*1 Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz “L” period of SCL clock tLOW 4.7 ⎯ 1.3 ⎯ µs “H” period of SCL clock tHIGH 4.0 ⎯ 0.6 ⎯ µs Bus free time between “STOP condition” and “START condition” tBUS 4.7 ⎯ 1.3 ⎯ µs SCL ↓ → SDA output delay time tDLDAT ⎯ 5 × M*3 ⎯ 5 × M*3 ns “Repeated START condition” setup time SCL ↑ → SDA ↓ tSUSTA 4.7 ⎯ 0.6 ⎯ µs “Repeated START condition” hold time SDA ↓ → SCL ↓ tHDSTA 4.0 ⎯ 0.6 ⎯ µs “STOP condition” setup time SCL ↑ → SDA ↑ tSUSTO 4.0 ⎯ 0.6 ⎯ µs SDA data input hold time (vs. SCL ↓) tHDDAT 2 × M*3 ⎯ 2 × M*3 ⎯ µs SDA data input setup time (vs. SCL↑) tSUDAT 250 ⎯ 100*4 ⎯ ns R = 1 kΩ, C = 50 pF*2 Remarks The first clock pulse is generated after this. *1 : For use at over 100 kHz, set the resource clock to 6 MHz or higher. *2 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. *3 : M = Resource clock cycle (ns) *4 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of “tSUDAT ≥ 250 ns”. When a device does not extend the “L” period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) from when the SCL line is released. 63 MB91313 Series 5. Electrical Characteristics for the A/D Converter (1) Electrical Characteristics (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C) Parameter Value Typ Max Resolution ⎯ ⎯ 10 bit Total error*1 ⎯ ⎯ ± 5.5 LSB Nonlinear error*1 ⎯ ⎯ ± 3.5 LSB Differential linear error*1 ⎯ ⎯ ± 2.0 LSB Zero transition voltage*1 − 4.0 ⎯ + 6.0 LSB Full transition voltage*1 AVRH − 5.5 ⎯ AVRH + 3.0 LSB 7.94*2 ⎯ ⎯ µs Power supply current (analog + digital) ⎯ ⎯ 3 mA Reference power supply current (between AVRH and AVSS) ⎯ ⎯ 100 µA Analog input capacitance ⎯ ⎯ 21 pF Interchannel disparity ⎯ ⎯ 4 LSB Conversion time *1 : Measured in the CPU sleep state *2 : Depending on the clock cycle supplied to peripheral resources Comparator RIN AN9 to AN0 Analog input pin CIN 64 Unit Min RIN = 5 kΩ CIN = 21 pF Remarks AVcc = 3.3 V, AVRH = 3.3 V (CPU sleep) AVRH = 3.0 V, AVSS = 0.0 V MB91313 Series • The relationship between peripheral clock and external impedance (Peripheral clock frequency and external impedance) (Peripheral clock cycle and external impedance) MB91F313 External impedance [kΩ] External impedance [kΩ] MB91F313 120 110 100 90 80 70 60 50 40 30 20 20 15 20 25 30 35 Peripheral clock frequency [MHz] 40 120 110 100 90 80 70 60 50 40 30 20 10 30 50 70 90 110 Peripheral clock cycle [ns] 65 MB91313 Series (2) Definition of terms Resolution Linearity error : Analog variation that is recognized by an A/D converter. : The deviation between the actual conversion characteristics and a straight line connecting the device's zero transition point (“00 0000 0000B” ←→ “00 0000 0001B”) and full scale transition point (“11 1111 1110B” ←→ “11 1111 1111B”). Differential linear error : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Total error : This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error Linearity error 3FFH Differential linearity error Actual conversion characteristics Actual conversion characteristics (N + 1)H 3FEH {1 LSB' (N − 1) + VOT} VFST (measurement value) VNT (measurement value) 004H 003H Digital output Digital output 3FDH Ideal characteristics NH Actual conversion characteristics 002H Ideal characteristics 001H (N − 2)H VOT (measurement value) AVSS AVRH Analog input V(N + 1)T (measurement value) (N − 1)H VNT (measurement value) Actual conversion characteristics AVSS AVRH Analog input VNT − {1 LSB' × (N − 1) + VOT} [LSB] 1 LSB' V (N+1) T − VNT Differential linear error in digital output N = −1[LSB] 1 LSB' VFST − VOT 1 LSB = [V] 1022 Linear error in digital output N = N VOT VFST VNT : A/D converter digital output value : The voltage at which digital output changes from (000) H to (001) H : The voltage at which digital output changes from (3FE) H to (3FF) H : The voltage at which digital output changes from (N + 1) H to NH (Continued) 66 MB91313 Series (Continued) Total error 3FFH 1.5 LSB' 3FEH Actual conversion characteristics Digital output 3FDH {1 LSB' (N - 1) + 0.5 LSB'} 004H VNT 003H (measurement value) 002H Actual conversion characteristics Ideal characteristics 001H 0.5 LSB' AVSS AVRH Analog input AVRH − AVSS [V] 1024 VNT − {1 LSB' × (N − 1) + 0.5 LSB'} Total error of digital output N = 1 LSB' 1LSB' (ideal value) = N : A/D converter digital output value VNT : The voltage at which digital output changes from (N + 1) H to NH VOT' (ideal value) = AVSS + 0.5 LSB' [V] VFST' (ideal value) = AVRH − 1.5 LSB' [V] 67 MB91313 Series 6. Flash Memory Write/Erase Characteristics (VDDE = 3.3 V, VDDI = 1.8 V, Ta = + 25 °C) Parameter Value Unit Remarks Min Typ Max Sector erase time ⎯ 0.9 3.6 s Excludes internal programming prior erasure. Word write time ⎯ 23 370 µs Excludes system-level overhead. Chip write time ⎯ 6.2 102 s Excludes system-level overhead. 10000 ⎯ ⎯ cycle 20* ⎯ ⎯ year Erase/write cycle Data retention time Average Ta = + 85 °C * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C). 68 MB91313 Series ■ ORDERING INFORMATION Part number Package MB91F313PMC-GE1 120-pin plastic LQFP (FPT-120P-M21) 69 MB91313 Series ■ PACKAGE DIMENSION 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 16.0 × 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.88 g Code (Reference) P-LFQFP120-16×16-0.50 (FPT-120P-M21) 120-pin plastic LQFP (FPT-120P-M21) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ +0.40 * 16.00 –0.10 .630 +.016 –.004 SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0~8˚ 120 LEAD No. 1 30 0.50(.020) C "A" 31 0.22±0.05 (.009±.002) 0.08(.003) M 0.145 .006 2002 FUJITSU LIMITED F120033S-c-4-4 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 70 +0.05 –0.03 +.002 –.001 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. MB91313 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. 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