MICROCHIP PIC18LF8393-E/PT

PIC18F6393/6493/8393/8493
Data Sheet
64/80-Pin High Performance,
Flash Microcontrollers with LCD Driver,
12-Bit ADC and nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39896B
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All other trademarks mentioned herein are property of their
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© 2009, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
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Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39896B-page 2
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
64/80-Pin High-Performance, Flash Microcontrollers
with LCD Driver, 12-Bit ADC and nanoWatt Technology
LCD Driver Module Features:
Peripheral Highlights:
• Direct Driving of LCD Panel
• Up to 192 Pixels: Software Selectable
• Programmable LCD Timing module:
- Multiple LCD timing sources available
- Up to four commons: Static, 1/2, 1/3 or
1/4 multiplex
- Static, 1/2 or 1/3 bias configuration
• Can Drive LCD Panel while in Sleep mode for
Low-Power Operation
• 12-Bit, Up to 12-Channel Analog-to-Digital (A/D)
Converter module:
- Auto-acquisition capability
- Conversion available during Sleep
• High-Current Sink/Source 25 mA/25 mA
• Four External Interrupts
• Four Input Change Interrupts
• Four 8-Bit/16-Bit Timer/Counter modules
• Real-Time Clock (RTC) Software module:
- Configurable 24-hour clock, calendar, automatic
100-year or 12,800-year, day-of-week calculator
- Uses Timer1
• Up to Two Capture/Compare/PWM (CCP) modules
• Master Synchronous Serial Port (MSSP) module
Supporting Three-Wire SPI (all four modes) and
I2C™ Master and Slave modes
• Addressable USART module:
- Supports RS-485 and RS-232
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
• Dual Analog Comparators with Input Multiplexing
Power-Managed Modes:
•
•
•
•
•
•
•
•
•
Run: CPU On, Peripherals On
Idle: CPU Off, Peripherals On
Sleep: CPU Off, Peripherals Off
Run mode Current Down to 14 μA Typical
Idle mode Currents Down to 5.8 μA Typical
Sleep mode Currents Down to 0.1 μA Typical
Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
Watchdog Timer: 2.1 μA Typical
Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
• Four Crystal modes:
- LP: Up to 200 kHz
- XT: Up to 4 MHz
- HS: Up to 40 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
• 4x Phase Lock Loop (available for crystal and
internal oscillators)
• Two External RC modes, Up to 4 MHz
• Two External Clock modes, Up to 40 MHz
• Internal Oscillator Block:
- Eight selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary Oscillator Using Timer1 at 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown of device if primary
or secondary clock fails
© 2009 Microchip Technology Inc.
Special Microcontroller Features:
• C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
• 1000 Erase/Write Cycle Flash Program Memory
Typical
• Flash Retention: 100 Years Typical
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 132s
- 2% stability over VDD and temperature
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
Note:
This document is supplemented by the
“PIC18F6390/6490/8390/8490 Data Sheet”
(DS39629). See Section 1.0 “Device
Overview”.
DS39896B-page 3
Data
Memory
Program Memory
Device
Flash # Single-Word SRAM
(bytes) Instructions (bytes)
I/O
LCD
(pixel)
MSSP
12-Bit
CCP
A/D
(PWM)
(channels)
Master
I2C™
SPI
EUSART/
AUSART
PIC18F6393/6493/8393/8493
Comparators
Timers
8/16-Bit
PIC18F6393
8K
4096
768
50
128
12
2
Y
Y
1/1
2
1/3
PIC18F6493
16K
8192
768
50
128
12
2
Y
Y
1/1
2
1/3
PIC18F8393
8K
4096
768
66
192
12
2
Y
Y
1/1
2
1/3
PIC18F8493
16K
8192
768
66
192
12
2
Y
Y
1/1
2
1/3
Pin Diagrams
RD7/SEG7
RD6/SEG6
RD5/SEG5
RD4/SEG4
RD3/SEG3
RD2/SEG2
RD1/SEG1
VSS
VDD
RE7/CCP2(1)/SEG31
RD0/SEG0
RE6/COM3
RE5/COM2
RE4/COM1
COM0
LCDBIAS3
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LCDBIAS2
LCDBIAS1
RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
MCLR/VPP/RG5
RG4/SEG26
VSS
VDD
RF7/SS/SEG25
RF6/AN11/SEG24
RF5/AN10/CVREF/SEG23
RF4/AN9/SEG22
RF3/AN8/SEG21
RF2/AN7/C1OUT/SEG20
48
47
46
45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
44
43
42
41
40
PIC18F6393
PIC18F6493
39
38
37
36
35
34
33
15
16
RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/SEG13
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA4/T0CKI/SEG14
RC1/T1OSI/CCP2(1)
RA5/AN4/HLVDIN/SEG15
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/SEG16
AVSS
RA3/AN3/VREF+/SEG17
AVDD
RF0/AN5/SEG18
RF1/AN6/C2OUT/SEG19
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: RE7 is the alternate pin for CCP2 multiplexing.
DS39896B-page 4
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
Pin Diagrams (Continued)
RJ1/SEG33
RJ0/SEG32
RD7/SEG7
RD6/SEG6
RD5/SEG5
RD4/SEG4
RD3/SEG3
RD2/SEG2
RD1/SEG1
VDD
VSS
RD0/SEG0
RE7/CCP2(1)/SEG31
RE6/COM3
RE5/COM2
RE4/COM1
COM0
LCDBIAS3
RH0/SEG47
RH1/SEG46
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/SEG45
RH3/SEG44
LCDBIAS2
LCDBIAS1
RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
MCLR/VPP/RG5
RG4/SEG26
VSS
VDD
RF7/SS/SEG25
RF6/AN11/SEG24
RF5/AN10/CVREF/SEG23
RF4/AN9/SEG22
RF3/AN8/SEG21
RF2/AN7/C1OUT/SEG20
RH7/SEG43
RH6/SEG42
1
2
60
59
58
57
56
55
3
4
5
6
7
8
9
10
11
12
13
14
15
16
54
53
52
51
50
PIC18F8393
PIC18F8493
49
48
47
46
45
44
43
17
18
19
20
42
41
RJ2/SEG34
RJ3/SEG35
RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/SEG13
RJ7/SEG36
RJ6/SEG37
RJ5/SEG38
RJ4/SEG39
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA4/T0CKI/SEG14
RC1/T1OSI/CCP2(1)
VDD
RA5/AN4/HLVDIN/SEG15
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/SEG16
AVSS
RA3/AN3/VREF+/SEG17
AVDD
RF0/AN5/SEG18
RF1/AN6/C2OUT/SEG19
RH4/SEG40
RH5/SEG41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note 1: RE7 is the alternate pin for CCP2 multiplexing.
© 2009 Microchip Technology Inc.
DS39896B-page 5
PIC18F6393/6493/8393/8493
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 31
3.0 Special Features of the CPU ...................................................................................................................................................... 41
4.0 Electrical Characteristics ........................................................................................................................................................... 43
5.0 Packaging Information................................................................................................................................................................ 47
Appendix A: Revision History............................................................................................................................................................... 49
Appendix B: Device Differences........................................................................................................................................................... 49
Appendix C: Conversion Considerations ............................................................................................................................................. 50
Appendix D: Migration from Baseline to Enhanced Devices................................................................................................................ 50
Appendix E: migration from Mid-Range to Enhanced Devices ............................................................................................................ 51
Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................... 51
The Microchip Web Site ....................................................................................................................................................................... 55
Customer Change Notification Service ................................................................................................................................................ 55
Customer Support ................................................................................................................................................................................ 55
Reader Response ................................................................................................................................................................................ 56
Product Identification System............................................................................................................................................................... 57
DS39896B-page 6
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2009 Microchip Technology Inc.
DS39896B-page 7
PIC18F6393/6493/8393/8493
NOTES:
DS39896B-page 8
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F6393
• PIC18F8393
• PIC18F6493
• PIC18F8493
Note: This data sheet documents only the devices’
features and specifications that are in addition
to the features and specifications of the
PIC18F6390/6490/8390/8490 devices. For
information
on
the
features
and
specifications shared by the PIC18F6393/
6493/8393/8493 and PIC18F6390/6490/
8390/8490 devices, see the “PIC18F6390/
6490/8390/8490 Data Sheet” (DS39629).
This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price. In addition to
these features, the PIC18F6393/6493/8393/8493
family introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power-sensitive applications.
1.1
Special Features
• 12-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduces code overhead.
© 2009 Microchip Technology Inc.
1.2
Details on Individual Family
Members
Devices in the PIC18F6393/6493/8393/8493 family are
available in 64-pin (PIC18F6X93) and 80-pin
(PIC18F8X93) packages. Block diagrams for the two
groups are shown in Figure 1-1 and Figure 1-2,
respectively.
The devices are differentiated from each other in the
following ways:
• I/O Ports:
- 64-pin devices – 7 bidirectional ports
- 80-pin devices – 9 bidirectional ports
• LCD Pixels:
- 64-pin devices – 128 (32 SEGs x 4 COMs)
pixels can be driven
- 80-pin devices – 192 (48 SEGs x 4 COMs)
pixels can be driven
• Flash Program Memory:
- PIC18FX393 devices – 8 Kbytes
- PIC18FX493 devices – 16 Kbytes
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F6393/6493/8393/8493 family are available as
both standard and low-voltage devices. Standard
devices with Flash memory, designated with an “F” in
the part number (such as PIC18F6393), accommodate
an operating VDD range of 4.2V to 5.5V. Low-voltage
parts, designated by “LF” (such as PIC18LF6490),
function over an extended VDD range of 2.0V to 5.5V.
DS39896B-page 9
PIC18F6393/6493/8393/8493
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F6393
PIC18F6493
PIC18F8393
PIC18F8493
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
8K
16K
8K
16K
Program Memory (Instructions)
4096
8192
4096
8192
Data Memory (Bytes)
768
768
768
768
22
22
22
22
Operating Frequency
Program Memory (Bytes)
Interrupt Sources
I/O Ports
Number of Pixels the LCD Driver
Can Drive
Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G
F, G
F, G, H, J
F, G, H, J
128 (32 SEGs x
4 COMs)
128 (32 SEGs x
4 COMs)
192 (48 SEGs x
4 COMs)
192 (48 SEGs x
4 COMs)
Timers
4
4
4
4
Capture/Compare/PWM Modules
2
2
2
2
Serial Communications
MSSP, AUSART,
MSSP, AUSART,
MSSP, AUSART,
MSSP, AUSART,
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
12-Bit Analog-to-Digital Module
12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels
Resets (and Delays)
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction,
Stack Full,
Stack Full,
Stack Full,
Stack Full,
Stack Underflow
Stack Underflow
Stack Underflow
Stack Underflow
(PWRT, OST),
(PWRT, OST),
(PWRT, OST),
(PWRT, OST),
MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional),
WDT
WDT
WDT
WDT
Programmable Low-Voltage Detect
Programmable Brown-out Reset
Instruction Set
Packages
DS39896B-page 10
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
FIGURE 1-1:
PIC18F6X93 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Latch
8
8
inc/dec logic
PORTA
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
21
20
Address Latch
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
4
BSR
Address Latch
Program Memory
(48/64 Kbytes)
STKPTR
8
Instruction Bus <16>
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
PORTB
12
inc/dec
logic
Table Latch
PORTC
Address
Decode
ROM Latch
IR
Instruction
Decode and
Control
8
State Machine
Control Signals
OSC2
(3)
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
MCLR(2)
VDD, VSS
BOR
HLVD
Comparators
Note
Single-Supply
Programming
In-Circuit
Debugger
ADC
12-Bit
CCP1
RD7/SEG7:RD0/SEG0
8
W
Power-up
Timer
8
Oscillator
Start-up Timer
Power-on
Reset
PORTE
8
8
8
Internal
Oscillator
Block
8
ALU<8>
8
Watchdog
Timer
PORTF
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
Clock Monitor
PORTG
Timer0
CCP2
Timer1
MSSP
Timer2
EUSART1
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/SEG13
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO/SEG12
RC6/TX1/CK1
RC7/RX1/DT1
8 x 8 Multiply
BITOP
OSC1(3)
RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTD
PRODH PRODL
3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/SEG16
RA3/AN3/VREF+/SEG17
RA4/T0CKI/SEG14
RA5/AN4/HLVDIN/SEG15
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
Timer3
AUSART2
LCDBIAS1
LCDBIAS2
LCDBIAS3
COM0
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2(1)/SEG31
RF0/AN5/SEG18
RF1/AN6/C2OUT/SEG19
RF2/AN7/C1OUT/SEG20
RF3/AN8/SEG21
RF4/AN9/SEG22
RF5/AN10/CVREF/SEG23
RF6/AN11/SEG24
RF7/SS/SEG25
RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
RG4/SEG26
MCLR/VPP/RG5(2)
LCD
Driver
1:
CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RE7 when CCP2MX is not set.
2:
RG5 is only available when MCLR functionality is disabled.
3:
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
© 2009 Microchip Technology Inc.
DS39896B-page 11
PIC18F6393/6493/8393/8493
FIGURE 1-2:
PIC18F8X93 (80-PIN) BLOCK DIAGRAM
PORTA
Data Bus<8>
Table Pointer<21>
Data Latch
8
8
inc/dec logic
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
21
20
Address Latch
PCU PCH PCL
Program Counter
PORTB
12
Data Address<12>
31 Level Stack
4
BSR
Address Latch
Program Memory
(48/64 Kbytes)
STKPTR
Data Latch
8
Instruction Bus <16>
4
Access
Bank
12
FSR0
FSR1
FSR2
12
PORTC
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
8
Internal
Oscillator
Block
Power-up
Timer
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
Oscillator
Start-up Timer
Power-on
Reset
OSC2
Single-Supply
Programming
In-Circuit
Debugger
MCLR(2)
VDD, VSS
RD7/SEG7:RD0/SEG0
PORTE
PRODH PRODL
8 x 8 Multiply
8
W
BITOP
8
(3)
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/SEG13
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO/SEG12
RC6/TX1/CK1
RC7/RX1/DT1
State Machine
Control Signals
3
OSC1(3)
RB0/INT0
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTD
IR
Instruction
Decode and
Control
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/SEG16
RA3/AN3/VREF+/SEG17
RA4/T0CKI/SEG14
RA5/AN4/HLVDIN/SEG15
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
8
8
8
8
PORTF
ALU<8>
8
Watchdog
Timer
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
Clock Monitor
PORTG
LCDBIAS1
LCDBIAS2
LCDBIAS3
COM0
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2(1)/SEG31
RF0/AN5/SEG18
RF1/AN6/C2OUT/SEG19
RF2/AN7/C1OUT/SEG20
RF3/AN8/SEG21
RF4/AN9/SEG22
RF5/AN10/CVREF/SEG23
RF6/AN11/SEG24
RF7/SS/SEG25
RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
RG4/SEG26
MCLR/VPP/RG5(2)
PORTH
BOR
HLVD
ADC
12-Bit
Timer0
Timer1
Timer2
Timer3
RH3/SEG47:RH0/SEG44
RH7/SEG40:RH4/SEG43
PORTJ
RJ3/SEG35:RJ0/SEG32
Comparators
Note
CCP1
CCP2
LCD
Driver
MSSP
EUSART1
RJ7/SEG36:RJ4/SEG39
AUSART2
1:
CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set and RE7 when CCP2MX is not set.
2:
RG5 is only available when MCLR functionality is disabled.
3:
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
DS39896B-page 12
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
MCLR/VPP/RG5
MCLR
TQFP
7
VPP
RG5
OSC1/CLKI/RA7
OSC1
Pin Buffer
Type Type
I
ST
P
I
ST
39
I
CLKI
I
RA7
I/O
OSC2/CLKO/RA6
OSC2
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
CMOS
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL
General purpose I/O pin.
ST
40
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 13
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1
RA1
AN1
23
RA2/AN2/VREF-/SEG16
RA2
AN2
VREFSEG16
22
RA3/AN3/VREF+/SEG17
RA3
AN3
VREF+
SEG17
21
RA4/T0CKI/SEG14
RA4
T0CKI
SEG14
28
RA5/AN4/HLVDIN/SEG15
RA5
AN4
HLVDIN
SEG15
27
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
SEG16 output for LCD.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
SEG17 output for LCD.
I/O
I
O
ST/OD
ST
Analog
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SEG15 output for LCD.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 14
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
48
RB1/INT1/SEG8
RB1
INT1
SEG8
47
RB2/INT2/SEG9
RB2
INT2
SEG9
46
RB3/INT3/SEG10
RB3
INT3
SEG10
45
RB4/KBI0/SEG11
RB4
KBI0
SEG11
44
RB5/KBI1
RB5
KBI1
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 1.
SEG8 output for LCD.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 2.
SEG9 output for LCD.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 3.
SEG10 output for LCD.
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 15
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(1)
29
RC2/CCP1/SEG13
RC2
CCP1
SEG13
33
RC3/SCK/SCL
RC3
SCK
SCL
34
RC4/SDI/SDA
RC4
SDI
SDA
35
RC5/SDO/SEG12
RC5
SDO
SEG12
36
RC6/TX1/CK1
RC6
TX1
CK1
31
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
O
I
ST
—
ST
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
O
ST
—
Analog
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
SPI data out.
SEG12 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 16
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/SEG0
RD0
SEG0
58
RD1/SEG1
RD1
SEG1
55
RD2/SEG2
RD2
SEG2
54
RD3/SEG3
RD3
SEG3
53
RD4/SEG4
RD4
SEG4
52
RD5/SEG5
RD5
SEG5
51
RD6/SEG6
RD6
SEG6
50
RD7/SEG7
RD7
SEG7
49
I/O
O
ST
Analog
Digital I/O.
SEG0 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 17
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTE is a bidirectional I/O port.
LCDBIAS1
LCDBIAS1
2
LCDBIAS2
LCDBIAS2
1
LCDBIAS3
LCDBIAS3
64
COM0
COM0
63
RE4/COM1
RE4
COM1
62
RE5/COM2
RE5
COM2
61
RE6/COM3
RE6
COM3
60
RE7/CCP2/SEG31
RE7
CCP2(2)
SEG31
59
I
Analog
BIAS1 input for LCD.
I
Analog
BIAS2 input for LCD.
I
Analog
BIAS3 input for LCD.
O
Analog
COM0 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 18
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5/SEG18
RF0
AN5
SEG18
18
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
17
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
16
RF3/AN8/SEG21
RF3
AN8
SEG21
15
RF4/AN9/SEG22
RF4
AN9
SEG22
14
RF5/AN10/CVREF/SEG23
RF5
AN10
CVREF
SEG23
13
RF6/AN11/SEG24
RF6
AN11
SEG24
12
RF7/SS/SEG25
RF7
SS
SEG25
11
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 5.
SEG18 output for LCD.
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog input 6.
Comparator 2 output.
SEG19 output for LCD.
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog input 7.
Comparator 1 output.
SEG20 output for LCD.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 8.
SEG21 output for LCD.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 9.
SEG22 output for LCD.
I/O
I
O
O
ST
Analog
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
SEG23 output for LCD.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 11.
SEG24 output for LCD.
I/O
I
O
ST
TTL
Analog
Digital I/O.
SPI™ slave select input.
SEG25 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 19
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTG is a bidirectional I/O port.
RG0/SEG30
RG0
SEG30
3
RG1/TX2/CK2/SEG29
RG1
TX2
CK2
SEG29
4
RG2/RX2/DT2/SEG28
RG2
RX2
DT2
SEG28
5
RG3/SEG27
RG3
SEG27
6
RG4/SEG26
RG4
SEG26
8
I/O
O
ST
Analog
Digital I/O.
SEG30 output for LCD.
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
AUSART2 asynchronous transmit.
AUSART2 synchronous clock (see related RX2/DT2).
SEG29 output for LCD.
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
AUSART2 asynchronous receive.
AUSART2 synchronous data (see related TX2/CK2).
SEG28 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG27 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG26 output for LCD.
P
—
See MCLR/VPP/RG5 pin.
RG5
VSS
9, 25, 41, 56
Ground reference for logic and I/O pins.
VDD
10, 26, 38, 57
P
—
Positive supply for logic and I/O pins.
AVSS
20
P
—
Ground reference for analog modules.
AVDD
19
P
—
Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 20
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
MCLR/VPP/RG5
MCLR
TQFP
9
VPP
RG5
OSC1/CLKI/RA7
OSC1
Pin Buffer
Type Type
I
ST
P
I
ST
49
I
CLKI
I
RA7
I/O
OSC2/CLKO/RA6
OSC2
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
CMOS
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL
General purpose I/O pin.
ST
50
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 21
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
RA1/AN1
RA1
AN1
29
RA2/AN2/VREF-/SEG16
RA2
AN2
VREFSEG16
28
RA3/AN3/VREF+/SEG17
RA3
AN3
VREF+
SEG17
27
RA4/T0CKI/SEG14
RA4
T0CKI
SEG14
34
RA5/AN4/HLVDIN/SEG15
RA5
AN4
HLVDIN
SEG15
33
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
SEG16 output for LCD.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
SEG17 output for LCD.
I/O
I
O
ST/OD
ST
Analog
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SEG15 output for LCD.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 22
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
58
RB1/INT1/SEG8
RB1
INT1
SEG8
57
RB2/INT2/SEG9
RB2
INT2
SEG9
56
RB3/INT3/SEG10
RB3
INT3
SEG10
55
RB4/KBI0/SEG11
RB4
KBI0
SEG11
54
RB5/KBI1
RB5
KBI1
53
RB6/KBI2/PGC
RB6
KBI2
PGC
52
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 1.
SEG8 output for LCD.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 2.
SEG9 output for LCD.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 3.
SEG10 output for LCD.
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 23
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(1)
35
RC2/CCP1/SEG13
RC2
CCP1
SEG13
43
RC3/SCK/SCL
RC3
SCK
SCL
44
RC4/SDI/SDA
RC4
SDI
SDA
45
RC5/SDO/SEG12
RC5
SDO
SEG12
46
RC6/TX1/CK1
RC6
TX1
CK1
37
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
O
I
ST
—
ST
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
O
ST
—
Analog
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
SPI data out.
SEG12 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 24
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/SEG0
RD0
SEG0
72
RD1/SEG1
RD1
SEG1
69
RD2/SEG2
RD2
SEG2
68
RD3/SEG3
RD3
SEG3
67
RD4/SEG4
RD4
SEG4
66
RD5/SEG5
RD5
SEG5
65
RD6/SEG6
RD6
SEG6
64
RD7/SEG7
RD7
SEG7
63
I/O
O
ST
Analog
Digital I/O.
SEG0 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 25
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTE is a bidirectional I/O port.
LCDBIAS1
LCDBIAS1
4
LCDBIAS2
LCDBIAS2
3
LCDBIAS3
LCDBIAS3
78
COM0
COM0
77
RE4/COM1
RE4
COM1
76
RE5/COM2
RE5
COM2
75
RE6/COM3
RE6
COM3
74
RE7/CCP2/SEG31
RE7
CCP2(2)
SEG31
73
I
Analog
BIAS1 input for LCD.
I
Analog
BIAS2 input for LCD.
I
Analog
BIAS3 input for LCD.
O
Analog
COM0 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 26
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5/SEG18
RF0
AN5
SEG18
24
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
23
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
18
RF3/AN8/SEG21
RF3
AN8
SEG21
17
RF4/AN9/SEG22
RF4
AN9
SEG22
16
RF5/AN10/CVREF/SEG23
RF5
AN10
CVREF
SEG23
15
RF6/AN11/SEG24
RF6
AN11
SEG24
14
RF7/SS/SEG25
RF7
SS
SEG25
13
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 5.
SEG18 output for LCD.
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog input 6.
Comparator 2 output.
SEG19 output for LCD.
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog input 7.
Comparator 1 output.
SEG20 output for LCD.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 8.
SEG21 output for LCD.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 9.
SEG22 output for LCD.
I/O
I
O
O
ST
Analog
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
SEG23 output for LCD.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 11.
SEG24 output for LCD.
I/O
I
O
ST
TTL
Analog
Digital I/O.
SPI slave select input.
SEG25 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 27
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTG is a bidirectional I/O port.
RG0/SEG30
RG0
SEG30
5
RG1/TX2/CK2/SEG29
RG1
TX2
CK2
SEG29
6
RG2/RX2/DT2/SEG28
RG2
RX2
DT2
SEG28
7
RG3/SEG27
RG3
SEG27
8
RG4/SEG26
RG4
SEG26
10
RG5
I/O
O
ST
Analog
Digital I/O.
SEG30 output for LCD.
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
AUSART2 asynchronous transmit.
AUSART2 synchronous clock (see related RX2/DT2).
SEG29 output for LCD.
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
AUSART2 asynchronous receive.
AUSART2 synchronous data (see related TX2/CK2).
SEG28 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG27 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG26 output for LCD.
See MCLR/VPP/RG5 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 28
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTH is a bidirectional I/O port.
RH0/SEG47
RH0
SEG47
79
RH1/SEG46
RH1
SEG46
80
RH2/SEG45
RH2
SEG45
1
RH3/SEG44
RH3
SEG44
2
RH4/SEG40
RH4
SEG40
22
RH5/SEG41
RH5
SEG41
21
RH6/SEG42
RH6
SEG42
20
RH7/SEG43
RH7
SEG43
19
I/O
O
ST
Analog
Digital I/O.
SEG47 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG46 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG45 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG44 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG40 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG41 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG42 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG43 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 29
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTJ is a bidirectional I/O port.
RJ0/SEG32
RJ0
SEG32
62
RJ1/SEG33
RJ1
SEG33
61
RJ2/SEG34
RJ2
SEG34
60
RJ3/SEG35
RJ3
SEG35
59
RJ4/SEG39
RJ4
SEG39
39
RJ5/SEG38
RJ5
SEG38
40
RJ6/SEG37
RJ6
SEG37
41
RJ7/SEG36
RJ7
SEG36
42
I/O
O
ST
Analog
Digital I/O.
SEG32 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
VSS
11, 31, 51, 70
P
—
Ground reference for logic and I/O pins.
VDD
12, 32, 48, 71
P
—
Positive supply for logic and I/O pins.
AVSS
26
P
—
Ground reference for analog modules.
AVDD
25
P
—
Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 30
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module converts
an analog input signal to a 12-bit digital number. The
module has 12 inputs for both PIC18F6393/6493 (64-pin)
and PIC18F8393/8493 (80-pin) devices.
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
The module has five registers:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)
0110 = Channel 6 (AN6)
0111 = Channel 7 (AN7)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Unimplemented(1)
1101 = Unimplemented(1)
1110 = Unimplemented(1)
1111 = Unimplemented(1)
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0
ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1:
x = Bit is unknown
Performing a conversion on unimplemented channels will return a floating input measurement.
© 2009 Microchip Technology Inc.
DS39896B-page 31
PIC18F6393/6493/8393/8493
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
VCFG1:VCFG0: Voltage Reference Configuration bits
A/D VREF-
00
AVDD
AVSS
01
External VREF+
AVSS
10
AVDD
External VREF-
11
External VREF+
External VREF-
PCFG<3:0>
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG3:PCFG0: A/D Port Configuration Control bits
AN11
bit 3-0
A/D VREF+
x = Bit is unknown
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
DS39896B-page 32
D = Digital I/O
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
DS39896B-page 33
PIC18F6393/6493/8393/8493
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+/SEG17 and RA2/AN2/VREF-/SEG16 pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 2-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 2-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1011
1010
1001
1000
0111
0110
0101
0100
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
0010
0001
VCFG1:VCFG0
AVDD(1)
Reference
Voltage
VREF+
VREF-
0000
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
X0
X1
1X
0X
AVSS(1)
Note 1:
DS39896B-page 34
I/O pins have diode protection to VDD and VSS.
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
6.
7.
FIGURE 2-2:
The following steps should be followed to perform an A/D
conversion:
FIGURE 2-3:
FFEh
003h
002h
001h
4095 LSB
4095.5 LSB
4094 LSB
3 LSB
2 LSB
4094.5 LSB
000h
2.5 LSB
3.
4.
FFFh
0.5 LSB
2.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Digital Code Output
1.
A/D TRANSFER FUNCTION
1 LSB
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
5.
1.5 LSB
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
Analog Input Voltage
ANALOG INPUT MODEL
VDD
Rs
VAIN
Sampling
Switch
VT = 0.6V
ANx
RIC ≤ 1k
CPIN
5 pF
VT = 0.6V
SS
RSS
CHOLD = 25 pF
ILEAKAGE
±100 nA
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
= Sampling Switch
SS
= Sample/Hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance
© 2009 Microchip Technology Inc.
VDD
6V
5V
4V
3V
2V
1
2
3
4
Sampling Switch (kΩ)
DS39896B-page 35
PIC18F6393/6493/8393/8493
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor, CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
the minimum acquisition time before starting a
conversion.
Note:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 4 kΩ
85°C (system max.)
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 2-2:
VHOLD
or
TC
Equation 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
TACQ
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
A/D MINIMUM CHARGING TIME
=
(VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
=
– (CHOLD)(RIC + RSS + RS) ln(1/4096)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
TAMP
=
0.2 µs
TCOFF
=
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ
=
0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
DS39896B-page 36
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
2.2
Selecting and Configuring
Acquisition Time
2.3
Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provide a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
•
•
•
•
•
•
•
Manual
acquisition
is
selected
when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD. (See parameter 130 for more
information.)
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 2-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Assumes TAD Min. = 0.8 μs
A/D Clock Source (TAD)
Note 1:
2:
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
000
2.50 MHz
4 TOSC
100
5.00 MHz
8 TOSC
001
10.00 MHz
16 TOSC
101
20.00 MHz
32 TOSC
010
40.00 MHz
64 TOSC
RC(1)
110
40.00 MHz
x11
1.00 MHz(2)
The RC source has a typical TAD time of 2.5 μs.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
© 2009 Microchip Technology Inc.
DS39896B-page 37
PIC18F6393/6493/8393/8493
2.4
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After entering the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog conversion on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a digital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If the ACQT2:ACQT0 bits are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
DS39896B-page 38
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
2.6
A/D Conversions
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acquisition time has been selected before the conversion
starts.
2.7
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous-measure values.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
not be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b11
b10
b9
b8
b7
b6
b3
b4
b5
b2
b1
b0
Conversion starts
Discharge
(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
FIGURE 2-5:
TAD Cycles
TACQT Cycles
1
2
3
4
1
Automatic
Acquisition
Time
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
© 2009 Microchip Technology Inc.
2
b11
3
b10
4
b9
5
b8
6
b7
7
b6
8
b5
9
b4
10
b3
11
b2
12
b1
13
b0
TAD1
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
DS39896B-page 39
PIC18F6393/6493/8393/8493
2.8
Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
bits
(CCP2CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
TABLE 2-2:
Name
INTCON
desired location). The appropriate analog input channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
(3)
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
(3)
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
(3)
IPR1
—
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
(3)
PIR2
OSCFIF
CMIF
—
—
BCL1IF
HLVDIF
TMR3IF
CCP2IF
(3)
PIE2
OSCFIE
CMIE
—
—
BCL1IE
HLVDIE
TMR3IE
CCP2IE
(3)
IPR2
OSCFIP
CMIP
—
—
BCL1IP
HLVDIP
TMR3IP
CCP2IP
(3)
ADRESH
A/D Result Register High Byte
(3)
ADRESL
A/D Result Register Low Byte
(3)
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
(3)
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
(3)
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
(3)
TRISA
TRISA7(1)
TRISA6(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
(3)
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
(3)
TRISH(2)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
(3)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on 64-pin devices.
3: For these Reset values, see the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
DS39896B-page 40
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
3.0
SPECIAL FEATURES OF THE
CPU
Note:
3.1
For additional details on the Configuration
bits, refer to Section 23.1 “Configuration
Bits” in the “PIC18F6390/6490/8390/8490
Data Sheet” (DS39629). Device ID information presented in this section is for the
PIC18F6393/6493/8393/8493 devices only.
Device ID Registers
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers and can be read by firmware using table
reads.
PIC18F6393/6493/8393/8493 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Device ID Registers
TABLE 3-1:
DEVICE IDs
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(1)
3FFFFFh
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
xxxx xxxx(1)
DEVID2
Legend: x = unknown
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the user.
© 2009 Microchip Technology Inc.
DS39896B-page 41
PIC18F6393/6493/8393/8493
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6393/6493/8393/8493 DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-5
DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
bit 4-0
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F6393/6493/8393/8493 DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
bit 7-0
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DEV10:DEV3: Device ID bits
DS39896B-page 42
Device
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>)
PIC18F6393
0001 1010
000
PIC18F6493
0000 1110
000
PIC18F8393
0001 1010
001
PIC18F8493
0000 1110
001
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
4.0
ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only the PIC18F6393/6493/8393/8493 devices’ specifications that differ from those of the PIC18F6390/6490/8390/8490 devices. For detailed information on the
electrical specifications shared by the PIC18F6393/6493/8393/8493 and PIC18F6390/6490/8390/8490
devices, see the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑ (VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RG5 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RG5 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
DS39896B-page 43
PIC18F6393/6493/8393/8493
FIGURE 4-1:
PIC18F6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18FX393/X493
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 4-2:
PIC18LF6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18LFX393/X493
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39896B-page 44
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 4-1:
Param
No.
Sym
A/D CONVERTER CHARACTERISTICS: PIC18F6393/6493/8393/8493 (INDUSTRIAL)
Characteristic
Min
Typ
Max
Units
Conditions
ΔVREF ≥ 3.0V
A01
NR
Resolution
—
—
12
bit
A03
EIL
Integral Linearity Error
—
<±1
±2.0
LSB
VDD = 3.0V
—
—
±2.0
LSB
VDD = 5.0V
—
<±1
+1.5/-1.0
LSB
VDD = 3.0V
—
—
+1.5/-1.0
LSB
VDD = 5.0V
A04
A06
A07
EDL
EOFF
EGN
Differential Linearity Error
Offset Error
Gain Error
A10
—
A20
ΔVREF Reference Voltage Range
(VREFH – VREFL)
—
<±1
±5
LSB
VDD = 3.0V
—
—
±3
LSB
VDD = 5.0V
—
<±1
±2.00
LSB
VDD = 3.0V
—
—
±2.00
LSB
VDD = 5.0V
Monotonicity
ΔVREF ≥ 3.0V
ΔVREF ≥ 3.0V
ΔVREF ≥ 3.0V
ΔVREF ≥ 3.0V
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
—
VDD – VSS
V
For 12-bit resolution
3
A21
VREFH Reference Voltage High
VSS + 3.0V
—
VDD + 0.3V
V
For 12-bit resolution
A22
VREFL Reference Voltage Low
VSS – 0.3V
—
VDD – 3.0V
V
For 12-bit resolution
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A30
ZAIN
Recommended
Impedance of Analog
Voltage Source
—
—
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA
μA
Note 1:
2:
During VAIN acquisition.
During A/D conversion
cycle.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from the RA3/AN3/VREF+/SEG17 pin or VDD, whichever is selected as the VREFH source. VREFL
current is from the RA2/AN2/VREF-/SEG16 pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc.
DS39896B-page 45
PIC18F6393/6493/8393/8493
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK(1)
132
11
A/D DATA
10
9
...
...
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
Param
Symbol
No.
130
TAD
A/D CONVERSION REQUIREMENTS
Characteristic
A/D Clock Period
Min
Max
Units
PIC18FXXXX
0.8
12.5(1)
μs
TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
1.4
25.0(1)
μs
VDD = 3.0V; TOSC based,
VREF full range
PIC18FXXXX
—
1
μs
A/D RC mode
VDD = 3.0V; A/D RC mode
—
3
μs
131
TCNV
Conversion Time
(not including acquisition time)(2)
13
14
TAD
132
TACQ
Acquisition Time(3)
1.4
—
μs
135
TSWC
Switching Time from Convert → Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
PIC18LFXXXX
Note 1:
2:
3:
4:
Conditions
μs
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
DS39896B-page 46
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F6390/6490/
8390/8490 Data Sheet” (DS39629).
© 2009 Microchip Technology Inc.
DS39896B-page 47
PIC18F6393/6493/8393/8493
NOTES:
DS39896B-page 48
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
APPENDIX A:
REVISION HISTORY
Revision A (September 2007)
Original data sheet for the PIC18F6393/6493/8393/
8493 devices.
APPENDIX B:
DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
Revision B (October 2009)
Removed ”Preliminary” marking.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F6393
PIC18F6493
PIC18F8393
PIC18F8493
Number of Pixels the LCD Driver
Can Drive
128 (4 x 32)
128 (4 x 32)
192 (4 x 48)
192 (4 x 48)
I/O Ports
Flash Program Memory
Packages
© 2009 Microchip Technology Inc.
Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G
F, G
F, G, H, J
F, G, H, J
8 Kbytes
16 Kbytes
8 Kbytes
16 Kbytes
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
DS39896B-page 49
PIC18F6393/6493/8393/8493
APPENDIX C:
CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
DS39896B-page 50
APPENDIX D:
MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Currently Available
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
APPENDIX E:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while devicespecific, are generally applicable to all mid-range to
enhanced device migrations.
APPENDIX F:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”. This Application Note is
available as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
© 2009 Microchip Technology Inc.
DS39896B-page 51
PIC18F6393/6493/8393/8493
NOTES:
DS39896B-page 52
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
INDEX
A
A/D ...................................................................................... 31
A/D Converter Interrupt, Configuring .......................... 35
Acquisition Requirements ........................................... 36
ADCON0 Register....................................................... 31
ADCON1 Register....................................................... 31
ADCON2 Register....................................................... 31
ADRESH Register................................................. 31, 34
ADRESL Register ....................................................... 31
Analog Port Pins, Configuring..................................... 38
Associated Registers .................................................. 40
Configuring the Module............................................... 35
Conversion Clock (TAD) .............................................. 37
Conversion Requirements .......................................... 46
Conversion Status (GO/DONE Bit) ............................. 34
Conversions ................................................................ 39
Converter Characteristics ........................................... 45
Discharge.................................................................... 39
Operation in Power-Managed Modes ......................... 38
Selecting and Configuring Acquisition Time ............... 37
Special Event Trigger (ECCP2) .................................. 40
Transfer Function........................................................ 35
Use of the ECCP2 Trigger .......................................... 40
Absolute Maximum Ratings ................................................ 43
ADCON0 Register............................................................... 31
GO/DONE Bit.............................................................. 34
ADCON1 Register............................................................... 31
ADCON2 Register............................................................... 31
ADRESH Register............................................................... 31
ADRESL Register ......................................................... 31, 34
Analog-to-Digital Converter. See A/D.
B
Block Diagrams
A/D .............................................................................. 34
Analog Input Model ..................................................... 35
PIC18F6X93 ............................................................... 11
PIC18F8X93 ............................................................... 12
C
Compare (ECCP2 Module)
Special Event Trigger.................................................. 40
Conversion Considerations ................................................. 50
Customer Change Notification Service ............................... 55
Customer Notification Service............................................. 55
Customer Support ............................................................... 55
D
Device Differences .............................................................. 49
Device ID Registers ............................................................ 41
Device Overview ................................................................... 9
Details of Individual Devices ......................................... 9
Features (table)........................................................... 10
Special Features ........................................................... 9
Documentation
Most Current Versions .................................................. 7
Related Data Sheet....................................................... 9
E
Electrical Characteristics..................................................... 43
A/D Converter ............................................................. 45
Absolute Maximum Ratings ........................................ 43
Low-Power Voltage-Frequency Graph........................ 44
© 2009 Microchip Technology Inc.
Voltage-Frequency Graph .......................................... 44
Equations
A/D Acquisition Time .................................................. 36
A/D Minimum Charging Time ..................................... 36
Calculating the Minimum Required Acquisition Time . 36
Errata .................................................................................... 7
I
Internet Address ................................................................. 55
Interrupt Sources
A/D Conversion Complete .......................................... 35
L
LCD Driver
Features ....................................................................... 3
M
Microchip Internet Web Site................................................ 55
Microcontroller
Special Features........................................................... 3
Migration from Baseline to Enhanced Devices ................... 50
Migration from High-End to Enhanced Devices.................. 51
Migration from Mid-Range to Enhanced Devices ............... 51
O
Oscillator Structure
Features ....................................................................... 3
P
Packaging
Information.................................................................. 47
Peripheral Highlights............................................................. 3
Pin Diagrams
64-Pin TQFP................................................................. 4
80-Pin TQFP................................................................. 5
Pin Functions
AVDD ........................................................................... 20
AVDD ........................................................................... 30
AVSS ........................................................................... 20
AVSS ........................................................................... 30
COM0 ................................................................... 18, 26
LCDBIAS1 ............................................................ 18, 26
LCDBIAS2 ............................................................ 18, 26
LCDBIAS3 ............................................................ 18, 26
MCLR/VPP/RG5.................................................... 13, 21
OSC1/CLKI/RA7................................................... 13, 21
OSC2/CLKO/RA6 ................................................. 13, 21
RA0/AN0............................................................... 14, 22
RA1/AN1............................................................... 14, 22
RA2/AN2/VREF-/SEG16........................................ 14, 22
RA3/AN3/VREF+/SEG17....................................... 14, 22
RA4/T0CKI/SEG14............................................... 14, 22
RA5/AN4/HLVDIN/SEG15.................................... 14, 22
RB0/INT0.............................................................. 15, 23
RB1/INT1/SEG8 ................................................... 15, 23
RB2/INT2/SEG9 ................................................... 15, 23
RB3/INT3/SEG10 ................................................. 15, 23
RB4/KBI0/SEG11 ................................................. 15, 23
RB5/KBI1.............................................................. 15, 23
RB6/KBI2/PGC ..................................................... 15, 23
RB7/KBI3/PGD ..................................................... 15, 23
RC0/T1OSO/T13CKI ............................................ 16, 24
RC1/T1OSI/CCP2 ................................................ 16, 24
RC2/CCP1/SEG13 ............................................... 16, 24
DS39896B-page 53
PIC18F6393/6493/8393/8493
RC3/SCK/SCL ...................................................... 16, 24
RC4/SDI/SDA ....................................................... 16, 24
RC5/SDO/SEG12 ................................................. 16, 24
RC6/TX1/CK1 ....................................................... 16, 24
RC7/RX1/DT1 ....................................................... 16, 24
RD0/SEG0 ............................................................ 17, 25
RD0/SEG1 .................................................................. 17
RD1/SEG1 .................................................................. 25
RD2/SEG2 ............................................................ 17, 25
RD3/SEG3 ............................................................ 17, 25
RD4/SEG4 ............................................................ 17, 25
RD5/SEG5 ............................................................ 17, 25
RD6/SEG6 ............................................................ 17, 25
RD7/SEG7 ............................................................ 17, 25
RE4/COM1............................................................ 18, 26
RE5/COM2............................................................ 18, 26
RE6/COM3............................................................ 18, 26
RE7/CCP2/SEG31 ................................................ 18, 26
RF0/AN5/SEG18................................................... 19, 27
RF1/AN6/C2OUT/SEG19 ..................................... 19, 27
RF2/AN7/C1OUT/SEG20 ..................................... 19, 27
RF3/AN8/SEG21................................................... 19, 27
RF4/AN9/SEG22................................................... 19, 27
RF5/AN10/CVREF/SEG23 ..................................... 19, 27
RF6/AN11/SEG24................................................. 19, 27
RF7/SS/SEG25 ..................................................... 19, 27
RG0/SEG30 .......................................................... 20, 28
RG1/TX2/CK2/SEG29 .......................................... 20, 28
RG2/RX2/DT2/SEG28 .......................................... 20, 28
RG3/SEG27 .......................................................... 20, 28
RG4/SEG26 .......................................................... 20, 28
RG5....................................................................... 20, 28
RH0/SEG47 ................................................................ 29
RH1/SEG46 ................................................................ 29
RH2/SEG45 ................................................................ 29
RH3/SEG44 ................................................................ 29
RH4/SEG40 ................................................................ 29
RH5/SEG41 ................................................................ 29
RH6/SEG42 ................................................................ 29
RH7/SEG43 ................................................................ 29
RJ0/SEG32 ................................................................. 30
RJ1/SEG33 ................................................................. 30
RJ2/SEG34 ................................................................. 30
RJ3/SEG35 ................................................................. 30
RJ4/SEG39 ................................................................. 30
RJ5/SEG38 ................................................................. 30
RJ6/SEG37 ................................................................. 30
RJ7/SEG36 ................................................................. 30
VDD.............................................................................. 20
VDD.............................................................................. 30
VSS .............................................................................. 20
VSS .............................................................................. 30
Pinout I/O Descriptions
PIC18F6X93 ............................................................... 13
PIC18F8X93 ............................................................... 21
Power-Managed Modes
and A/D Operation ...................................................... 38
Features ........................................................................ 3
Product Identification System.............................................. 57
DEVID1 (Device ID 1)................................................. 42
DEVID2 (Device ID 2)................................................. 42
Revision History.................................................................. 49
S
Special Features of the CPU .............................................. 41
Device ID Registers .................................................... 41
T
Timing Diagrams
A/D Conversion........................................................... 46
W
WWW Address ................................................................... 55
WWW, On-Line Support ....................................................... 7
R
Reader Response ............................................................... 56
Registers
ADCON0 (A/D Control 0) ............................................ 31
ADCON1 (A/D Control 1) ............................................ 32
ADCON2 (A/D Control 2) ............................................ 33
DS39896B-page 54
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
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customers. Accessible by using your favorite Internet
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Users of Microchip products can receive assistance
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•
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•
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•
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Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
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Microchip’s customer notification service helps keep
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© 2009 Microchip Technology Inc.
DS39896B-page 55
PIC18F6393/6493/8393/8493
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Device: PIC18F6393/6493/8393/8493
Literature Number: DS39896B
Questions:
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3. Do you find the organization of this document easy to follow? If not, why?
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7. How would you improve this document?
DS39896B-page 56
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device(1), (2)
PIC18F6393, PIC18F6493, PIC18F8393, PIC18F8493 –
VDD range: 4.2V to 5.5V
PIC18LF6393, PIC18LF6493, PIC18LF8393, PIC18LF8493 –
VDD range: 2.0V to 5.5V
Temperature Range
I
E
= -40°C to +85°C
= -40°C to +125°C
Package
PT
=
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
c)
PIC18LF6393-I/PT 301 = Industrial temp.,
TQFP package, Extended VDD limits,
QTP pattern #301.
PIC18LF6393-I/PT = Industrial temp., TQFP
package, Extended VDD limits.
PIC18F6393-E/PT = Extended temp., TQFP
package, normal VDD limits.
(Industrial)
(Extended)
TQFP (Thin Quad Flatpack)
Note 1:
2:
© 2009 Microchip Technology Inc.
F = Standard Voltage Range
LF = Wide Voltage Range
T = in tape and reel TQFP
packages only.
DS39896B-page 57
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 91-11-4160-8631
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Tel: 43-7242-2244-39
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03/26/09
DS39896B-page 58
© 2009 Microchip Technology Inc.