PIC18F87J93 DATA SHEET (03/28/2010) DOWNLOAD

PIC18F87J93 Family
Data Sheet
64/80-Pin, High-Performance Microcontrollers
with LCD Driver, 12-Bit A/D
and nanoWatt Technology
© 2009 Microchip Technology Inc.
Preliminary
DS39948A
Note the following details of the code protection feature on Microchip devices:
•
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•
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•
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•
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
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Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
Omniscient Code Generation, PICC, PICC-18, PICkit,
PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB,
Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39948A-page ii
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
64/80-Pin, High-Performance Microcontrollers with
LCD Driver, 12-Bit A/D and nanoWatt Technology
LCD Driver and Keypad Interface
Features:
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Up to Four External Interrupts
• Four 8-Bit/16-Bit Timer/Counter modules
• Two Capture/Compare/PWM (CCP) modules
• Master Synchronous Serial Port (MSSP) module
with Two Modes of Operation:
- 3-Wire/4-Wire SPI (supports all four SPI modes)
- I2C™ Master and Slave mode
• One Addressable USART module
• One Enhanced Addressable USART module:
- LIN/J2602 support
- Auto-wake-up on Start bit and Break character
- Auto-Baud Detect (ABD)
• 12-Bit, up to 12-Channel A/D Converter:
- Auto-acquisition
- Conversion available during Sleep
• Two Analog Comparators
• Programmable Reference Voltage for Comparators
• Hardware Real-Time Clock and Calendar (RTCC)
with Clock, Calendar and Alarm Functions
• Charge Time Measurement Unit (CTMU):
- Capacitance measurement
- Time measurement with 1 ns typical resolution
• Direct LCD Panel Drive Capability:
- Can drive LCD panel while in Sleep mode
• Up to 48 Segments and 192 Pixels, Software
Selectable
• Programmable LCD Timing module:
- Multiple LCD timing sources available
- Up to four commons: static, 1/2, 1/3 or
1/4 multiplex
- Static, 1/2 or 1/3 bias configuration
• On-Chip LCD Boost Voltage Regulator for
Contrast Control
• Charge Time Measurement Unit (CTMU) for
Capacitive Touch Sensing
• ADC for Resistive Touch Sensing
Low-Power Features:
• Power-Managed modes:
- Run: CPU On, Peripherals On
- Idle: CPU Off, Peripherals On
- Sleep: CPU Off, Peripherals Off
• Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
•
•
•
•
Two Crystal modes, 4-25 MHz
Two External Clock modes, up to 48 MHz
4x Phase Lock Loop (PLL)
Internal Oscillator Block with PLL:
- Eight user-selectable frequencies from
31.25 kHz to 8 MHz
• Secondary Oscillator using Timer1 at 32 kHz
• Fail-Safe Clock Monitor (FSCM):
- Allows for safe shutdown if peripheral clock fails
PIC18F86J93
64K
PIC18F87J93
128K
CTMU
3,923
RTCC
3,923
128K
Master
I2C™
BOR/LVD
64K
PIC18F67J93
SPI
Comparators
PIC18F66J93
CCP
12-Bit A/D
(Channels)
I/O
Device
EUSART
AUSART
SRAM
Data
Memory
(Bytes)
1/3
2
Yes
Yes
1/1
12
2
Yes
Yes
Yes
2
Yes
Yes
1/1
12
2
Yes
Yes
Yes
1/3
2
Yes
Yes
1/1
12
2
Yes
Yes
Yes
1/3
2
Yes
Yes
1/1
12
2
Yes
Yes
Yes
LCD
(Pixels)
51
132
51
132
1/3
3,923
67
192
3,923
67
192
© 2009 Microchip Technology Inc.
This document is supplemented by the
“PIC18F87J90 Family Data Sheet”
(DS39933). See Section 1.0 “Device
Overview”.
Timers
8/16-Bit
Flash
Program
Memory
(Bytes)
Note:
MSSP
Preliminary
DS39948A-page 1
PIC18F87J93 FAMILY
Special Microcontroller Features:
• 10,000 Erase/Write Cycle Flash Program
Memory, Typical
• Flash Retention 20 Years, Minimum
• Self-Programmable under Software Control
• Flash Program Memory has Word Write
Capability for Data EEPROM Emulators
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
DS39948A-page 2
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
• In-Circuit Debug via Two Pins
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• Selectable Open-Drain Configuration for Serial
Communication and CCP Pins for Driving Outputs
up to 5V
• On-Chip 2.5V Regulator
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
Pin Diagrams – PIC18F6XJ93
RD7/SEG7
RD6/SEG6
RD5/SEG5
RD4/SEG4
RD3/SEG3
RD2/SEG2
RD1/SEG1
VDD
VSS
RD0/SEG0/CTPLS
RE7/CCP2(1)/SEG31
RE6/COM3
RE5/COM2
RE4/COM1
RE3/COM0
LCDBIAS3
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/VLCAP1
RG3/VLCAP2
MCLR
RG4/SEG26/RTCC
VSS
VDDCORE/VCAP
RF7/AN5/SS/SEG25
RF6/AN11/SEG24/C1INA
RF5/AN10/CVREF/SEG23/C1INB
RF4/AN9/SEG22/C2INA
RF3/AN8/SEG21/C2INB
RF2/AN7/C1OUT/SEG20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48
47
RB0/INT0/SEG30
RB1/INT1/SEG8
46
45
RB2/INT2/SEG9/CTED1
44
43
42
PIC18F66J93
41
40
PIC18F67J93
39
38
37
36
35
15
34
33
16
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
Note 1:
RC7/RX1/DT1/SEG28
RC6/TX1/CK1/SEG27
RC0/T1OSO/T13CKI
RA4/T0CKI/SEG14
RC1/T1OSI/CCP2(1)/SEG32
VDD
RA5/AN4/SEG15
VSS
RA0/AN0
RA1/AN1/SEG18
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
ENVREG
RF1/AN6/C2OUT/SEG19
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
The CCP2 pin placement depends on the CCP2MX Configuration bit setting.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 3
PIC18F87J93 FAMILY
Pin Diagrams – PIC18F8XJ93
RJ1/SEG33
RJ0
RD7/SEG7
RD6/SEG6
RD5/SEG5
RD4/SEG4
RD3/SEG3
RD2/SEG2
RD1/SEG1
VDD
VSS
RE7/CCP2(1)/SEG31
RD0/SEG0/CTPLS
RE6/COM3
RE5/COM2
RE4/COM1
RE3/COM0
LCDBIAS3
RH0/SEG47
RH1/SEG46
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/SEG45
RH3/SEG44
RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/VLCAP1
RG3/VLCAP2
MCLR
RG4/SEG26/RTCC
VSS
VDDCORE/VCAP
1
60
59
2
3
58
4
57
5
6
7
56
55
54
53
52
51
50
49
8
9
PIC18F86J93
10
PIC18F87J93
11
12
RF7/AN5/SS/SEG25
RF6/AN11/SEG24/C1INA
RF5/AN10/CVREF/SEG23/C1INB
RF4/AN9/SEG22/C2INA
13
14
15
48
47
46
16
RF3/AN8/SEG21/C2INB
RF2/AN7/C1OUT/SEG20
RH7/SEG43
17
18
45
44
Note 1:
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
RJ7/SEG36
RJ6/SEG37
RJ5/SEG38
RJ4/SEG39
RC7/RX1/DT1/SEG28
RC6/TX1/CK1/SEG27
RC0/T1OSO/T13CKI
RA4/T0CKI/SEG14
RC1/T1OSI/CCP2(1)I/SEG32
VDD
RA5/AN4/SEG15
VSS
RA0/AN0
RA1/AN1/SEG18
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
ENVREG
RF1/AN6/C2OUT/SEG19
RH4/SEG40
RH5/SEG41
RH6/SEG42
43
42
19
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RJ2/SEG34
RJ3/SEG35
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9/CTED1
RB3/INT3/SEG10/CTED2
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
The CCP2 pin placement depends on the CCP2MX Configuration bit setting.
DS39948A-page 4
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 27
3.0 Special Features of the CPU...................................................................................................................................................... 37
4.0 Electrical Characteristics ............................................................................................................................................................ 39
5.0 Packaging Information................................................................................................................................................................ 43
Appendix A: Revision History............................................................................................................................................................... 45
Appendix B: Device Differences .......................................................................................................................................................... 45
Appendix C: Conversion Considerations ............................................................................................................................................. 46
Appendix D: Migration From Baseline to Enhanced Devices .............................................................................................................. 46
Index .................................................................................................................................................................................................... 47
The Microchip Web Site ....................................................................................................................................................................... 49
Customer Change Notification Service ................................................................................................................................................ 49
Customer Support ................................................................................................................................................................................ 49
Reader Response ................................................................................................................................................................................ 50
Product Identification System .............................................................................................................................................................. 51
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 5
PIC18F87J93 FAMILY
TO OUR VALUED CUSTOMERS
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DS39948A-page 6
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
1.0
DEVICE OVERVIEW
1.2
This document contains device-specific information for
the following devices:
• PIC18F66J93
• PIC18F67J93
• PIC18F86J93
• PIC18F87J93
The PIC18F87J93 family of devices offers the
advantages of all PIC18 microcontrollers – high computational performance, a rich feature set and economical
price – with the addition of a versatile, on-chip LCD
driver. These features make the PIC18F87J93 family a
logical choice for many high-performance applications
where price is a primary consideration.
Special Features
• 12-Bit A/D Converter: The PIC18F87J93 family
implements a 12-bit A/D converter. A/D converters
in both families incorporate programmable acquisition time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code
overhead.
• Data RAM: The PIC18F87J93 family devices have
3,923 bytes of RAM.
© 2009 Microchip Technology Inc.
Devices in the PIC18F87J93 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in the
following ways:
Note: This data sheet documents only the devices’
features and specifications that are in addition
to the features and specifications of the
PIC18F87J90 family devices. For information
on the features and specifications shared by
the PIC18F87J93 family and PIC18F87J90
family devices, see the “PIC18F87J90 Family
Data Sheet” (DS39933).
1.1
Details on Individual Family
Members
• Flash Program Memory (64 Kbytes for
PIC18FX6J93 devices and 128 Kbytes for
PIC18FX7J93).
• LCD Pixels:
- 64-pin devices – 132 pixels
(33 SEGs x 4 COMs)
- 80-pin devices – 192 pixels
(48 SEGs x 4 COMs)
• I/O Ports (seven bidirectional ports on
PIC18F6XJ93 devices and nine bidirectional ports
on PIC18F8XJ93 devices).
All other features for devices in this family are identical
and are summarized in Table 1-1 and Table 1-2.
The devices’ block diagrams are given in Figure 1-1
and Figure 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
Preliminary
DS39948A-page 7
PIC18F87J93 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ93 (64-PIN DEVICES)
Features
PIC18F66J93
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
PIC18F67J93
DC – 48 MHz
64K
128K
32,768
65,536
3,923
3,923
Interrupt Sources
29
I/O Ports
Ports A, B, C, D, E, F, G
LCD Driver (available pixels to drive)
132 (33 SEGs x 4 COMs)
Timers
4
Comparators
2
CTMU
Yes
RTCC
Yes
Capture/Compare/PWM Modules
Serial Communications
2
MSSP, Addressable USART, Enhanced USART
12-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
12 Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ93 (80-PIN DEVICES)
Features
PIC18F86J93
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
DC – 48 MHz
64K
128K
32,768
65,536
3,923
3,923
Interrupt Sources
I/O Ports
LCD Driver (available pixels to drive)
PIC18F87J93
29
Ports A, B, C, D, E, F, G, H, J
192 (48 SEGs x 4 COMs)
Timers
4
Comparators
2
CTMU
Yes
RTCC
Yes
Capture/Compare/PWM Modules
Serial Communications
2
MSSP, Addressable USART, Enhanced USART
12-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
12 Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
DS39948A-page 8
80-Pin TQFP
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
FIGURE 1-1:
PIC18F6XJ93 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
RA0:RA7(1,2)
Data Memory
(2.0, 3.9
Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
RB0:RB7(1)
31-Level Stack
4
BSR
Address Latch
Program Memory
(96 Kbytes)
STKPTR
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
12
PORTC
RC0:RC7(1)
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
Instruction Bus <16>
PORTD
RD0:RD7(1)
IR
8
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
Power-up
Timer
INTRC
Oscillator
8 MHz
Oscillator
Oscillator
Start-up Timer
ENVREG
Voltage
Regulator
PORTE
RE0:RE1,
RE3:RE7(1)
PRODH PRODL
8 x 8 Multiply
3
Timing
Generation
Precision
Band Gap
Reference
State Machine
Control Signals
8
BITOP
W
8
8
8
8
Power-on
Reset
8
PORTF
RF1:RF7(1)
ALU<8>
Watchdog
Timer
8
BOR and
LVD(3)
PORTG
RG0:RG4(1)
VDDCORE/VCAP
VDD, VSS
MCLR
Timer0
Timer1
Timer2
Timer3
CTMU
ADC
12-Bit
Comparators
CCP1
CCP2
AUSART
EUSART
RTCC
MSSP
LCD
Driver
Note 1:
See Table 1-3 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3:
Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 9
PIC18F87J93 FAMILY
FIGURE 1-2:
PIC18F8XJ93 (80-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
RA0:RA7(1,2)
Data Memory
(2.0, 3.9
Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
Address Latch
20
PCU PCH PCL
Program Counter
PORTB
RB0:RB7(1)
12
Data Address<12>
31-Level Stack
4
BSR
Address Latch
Program Memory
(96 Kbytes)
STKPTR
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
PORTC
RC0:RC7(1)
12
inc/dec
logic
8
Table Latch
PORTD
RD0:RD7(1)
Address
Decode
ROM Latch
Instruction Bus <16>
PORTE
RE0:RE1,
RE3:RE7(1)
IR
8
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
PORTF
PRODH PRODL
Power-up
Timer
INTRC
Oscillator
8 MHz
Oscillator
Oscillator
Start-up Timer
8
BITOP
W
RG0:RG4(1)
8
Watchdog
Timer
Voltage
Regulator
BOR and
LVD(3)
PORTG
8
8
8
Power-on
Reset
Precision
Band Gap
Reference
RF1:RF7(1)
8 x 8 Multiply
3
Timing
Generation
ENVREG
State Machine
Control Signals
8
ALU<8>
PORTH
RH0:RH7(1)
8
PORTJ
VDDCORE/VCAP
VDD,VSS
RJ0:RJ7(1)
MCLR
Timer0
Timer1
Timer2
Timer3
CTMU
ADC
12-Bit
Comparators
CCP1
CCP2
AUSART
EUSART
RTCC
MSSP
LCD
Driver
Note 1:
See Table 1-3 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/Os in select oscillator modes.
3:
Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
DS39948A-page 10
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
TQFP
MCLR
7
OSC1/CLKI/RA7
OSC1
CLKI
39
Pin Buffer
Type Type
I
ST
I
I
CMOS
CMOS
I/O
TTL
O
—
CLKO
O
—
RA6
I/O
TTL
RA7
OSC2/CLKO/RA6
OSC2
40
Description
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
Oscillator crystal or external clock input.
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1/SEG18
RA1
AN1
SEG18
23
RA2/AN2/VREFRA2
AN2
VREF-
22
RA3/AN3/VREF+
RA3
AN3
VREF+
21
RA4/T0CKI/SEG14
RA4
T0CKI
SEG14
28
RA5/AN4/SEG15
RA5
AN4
SEG15
27
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
I/O
I
O
ST
ST
Analog
Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 11
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
INT0
SEG30
48
RB1/INT1/SEG8
RB1
INT1
SEG8
47
RB2/INT2/SEG9/CTED1
RB2
INT2
SEG9
CTED1
46
RB3/INT3/SEG10/CTED2
RB3
INT3
SEG10
CTED2
45
RB4/KBI0/SEG11
RB4
KBI0
SEG11
44
RB5/KBI1/SEG29
RB5
KBI1
SEG29
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
I/O
I
O
I
TTL
ST
Analog
ST
Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.
I/O
I
O
I
TTL
ST
Analog
ST
Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 12
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/CCP2/SEG32
RC1
T1OSI
CCP2(1)
SEG32
29
RC2/CCP1/SEG13
RC2
CCP1
SEG13
33
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
34
RC4/SDI/SDA/SEG16
RC4
SDI
SDA
SEG16
35
RC5/SDO/SEG12
RC5
SDO
SEG12
36
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
31
RC7/RX1/DT1/SEG28
RC7
RX1
DT1
SEG28
32
I/O
O
I
ST
—
ST
I/O
I
I/O
O
ST
CMOS
ST
Analog
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
I/O
I/O
I/O
O
ST
ST
ST
Analog
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
SPI data in.
I2C data I/O.
SEG16 output for LCD.
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 13
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
SEG0
CTPLS
58
RD1/SEG1
RD1
SEG1
55
RD2/SEG2
RD2
SEG2
54
RD3/SEG3
RD3
SEG3
53
RD4/SEG4
RD4
SEG4
52
RD5/SEG5
RD5
SEG5
51
RD6/SEG6
RD6
SEG6
50
RD7/SEG7
RD7
SEG7
49
I/O
O
O
ST
Analog
—
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 14
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
LCDBIAS1
2
RE1/LCDBIAS2
RE1
LCDBIAS2
1
LCDBIAS3
64
RE3/COM0
RE3
COM0
63
RE4/COM1
RE4
COM1
62
RE5/COM2
RE5
COM2
61
RE6/COM3
RE6
COM3
60
RE7/CCP2/SEG31
RE7
CCP2(2)
SEG31
59
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
I
Analog
BIAS3 input for LCD.
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 15
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
17
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
16
RF3/AN8/SEG21/C2INB
RF3
AN8
SEG21
C2INB
15
RF4/AN9/SEG22/C2INA
RF4
AN9
SEG22
C2INA
14
RF5/AN10/CVREF/
SEG23/C1INB
RF5
AN10
CVREF
SEG23
C1INB
13
RF6/AN11/SEG24/C1INA
RF6
AN11
SEG24
C1INA
12
RF7/AN5/SS/SEG25
RF7
AN5
SS
SEG25
11
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
I/O
I
O
I
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 8.
SEG21 output for LCD.
Comparator 2 input B.
I/O
I
O
I
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 9.
SEG22 output for LCD
Comparator 2 input A.
I/O
I
O
O
I
ST
Analog
Analog
Analog
Analog
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 input B.
I/O
I
O
I
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 11.
SEG24 output for LCD
Comparator 1 input A.
I/O
O
I
O
ST
Analog
TTL
Analog
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 16
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-3:
PIC18F6XJ93 (64-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
LCDBIAS0
3
RG1/TX2/CK2
RG1
TX2
CK2
4
RG2/RX2/DT2/VLCAP1
RG2
RX2
DT2
VLCAP1
5
RG3/VLCAP2
RG3
VLCAP2
6
RG4/SEG26/RTCC
RG4
SEG26
RTCC
8
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
I/O
O
I/O
ST
—
ST
Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
I/O
I
I/O
I
ST
ST
ST
Analog
Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
I/O
O
O
ST
Analog
—
Digital I/O.
SEG26 output for LCD.
RTCC output
VSS
9, 25, 41, 56
P
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
26, 38, 57
P
—
AVSS
20
P
—
Ground reference for analog modules.
AVDD
19
P
—
Positive supply for analog modules.
ENVREG
18
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
10
P
—
P
—
VCAP
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 17
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
TQFP
MCLR
9
OSC1/CLKI/RA7
OSC1
CLKI
49
Pin Buffer
Type Type
I
ST
I
I
CMOS
CMOS
I/O
TTL
O
—
CLKO
O
—
RA6
I/O
TTL
RA7
OSC2/CLKO/RA6
OSC2
50
Description
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
Oscillator crystal or external clock input.
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
RA1/AN1/SEG18
RA1
AN1
SEG18
29
RA2/AN2/VREFRA2
AN2
VREF-
28
RA3/AN3/VREF+
RA3
AN3
VREF+
27
RA4/T0CKI/SEG14
RA4
T0CKI
SEG14
34
RA5/AN4/SEG15
RA5
AN4
SEG15
33
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
I/O
I
O
ST
ST
Analog
Digital I/O.
Timer0 external clock input.
SEG14 output for LCD.
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 18
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
INT0
SEG30
58
RB1/INT1/SEG8
RB1
INT1
SEG8
57
RB2/INT2/SEG9/CTED1
RB2
INT2
SEG9
CTED1
56
RB3/INT3/SEG10/
CTED2
RB3
INT3
SEG10
CTED2
55
RB4/KBI0/SEG11
RB4
KBI0
SEG11
54
RB5/KBI1/SEG29
RB5
KBI1
SEG29
53
RB6/KBI2/PGC
RB6
KBI2
PGC
52
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
I/O
I
O
I
TTL
ST
Analog
ST
Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
CTMU Edge 1 input.
I/O
I
O
I
TTL
ST
Analog
ST
Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
CTMU Edge 2 input.
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 19
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
RC1/T1OSI/CCP2/SEG32
RC1
T1OSI
CCP2(1)
SEG32
35
RC2/CCP1/SEG13
RC2
CCP1
SEG13
43
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
44
RC4/SDI/SDA/SEG16
RC4
SDI
SDA
SEG16
45
RC5/SDO/SEG12
RC5
SDO
SEG12
46
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
37
RC7/RX1/DT1/SEG28
RC7
RX1
DT1
SEG28
38
I/O
O
I
ST
—
ST
I/O
I
I/O
O
ST
CMOS
ST
Analog
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
I/O
I/O
I/O
O
ST
ST
ST
Analog
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
SPI data in.
I2C data I/O.
SEG16 output for LCD.
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 20
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
SEG0
CTPLS
72
RD1/SEG1
RD1
SEG1
69
RD2/SEG2
RD2
SEG2
68
RD3/SEG3
RD3
SEG3
67
RD4/SEG4
RD4
SEG4
66
RD5/SEG5
RD5
SEG5
65
RD6/SEG6
RD6
SEG6
64
RD7/SEG7
RD7
SEG7
63
I/O
O
O
ST
Analog
ST
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 21
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
LCDBIAS1
4
RE1/LCDBIAS2
RE1
LCDBIAS2
3
LCDBIAS3
78
RE3/COM0
RE3
COM0
77
RE4/COM1
RE4
COM1
76
RE5/COM2
RE5
COM2
75
RE6/COM3
RE6
COM3
74
RE7/CCP2/SEG31
RE7
CCP2(2)
SEG31
73
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
I
Analog
BIAS3 input for LCD.
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 22
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
23
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
18
RF3/AN8/SEG21/C2INB
RF3
AN8
SEG21
C2INB
17
RF4/AN9/SEG22/C2INA
RF4
AN9
SEG22
C2INA
16
RF5/AN10/CVREF/
SEG23/C1INB
RF5
AN10
CVREF
SEG23
C1INB
15
RF6/AN11/SEG24/C1INA
RF6
AN11
SEG24
C1INA
14
RF7/AN5/SS/SEG25
RF7
AN5
SS
SEG25
13
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
I/O
I
O
I
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 8.
SEG21 output for LCD.
Comparator 2 input B.
I/O
I
O
I
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 9.
SEG22 output for LCD.
Comparator 2 input A.
I/O
I
O
O
I
ST
Analog
Analog
Analog
Analog
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
Comparator 1 input B.
I/O
I
O
I
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 11.
SEG24 output for LCD.
Comparator 1 input A.
I/O
O
I
O
ST
Analog
TTL
Analog
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 23
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
LCDBIAS0
5
RG1/TX2/CK2
RG1
TX2
CK2
6
RG2/RX2/DT2/VLCAP1
RG2
RX2
DT2
VLCAP1
7
RG3/VLCAP2
RG3
VLCAP2
8
RG4/SEG26/RTCC
RG4
SEG26
RTCC
10
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
I/O
O
I/O
ST
—
ST
Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
I/O
I
I/O
I
ST
ST
ST
Analog
Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
I/O
O
O
ST
Analog
—
Digital I/O.
SEG26 output for LCD.
RTCC output.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 24
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTH is a bidirectional I/O port.
RH0/SEG47
RH0
SEG47
79
RH1/SEG46
RH1
SEG46
80
RH2/SEG45
RH2
SEG45
1
RH3/SEG44
RH3
SEG44
2
RH4/SEG40
RH4
SEG40
22
RH5/SEG41
RH5
SEG41
21
RH6/SEG42
RH6
SEG42
20
RH7/SEG43
RH7
SEG43
19
I/O
O
ST
Analog
Digital I/O.
SEG47 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG46 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG45 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG44 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG40 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG41 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG42 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG43 output for LCD.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 25
PIC18F87J93 FAMILY
TABLE 1-4:
PIC18F8XJ93 (80-PIN DEVICE) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
TQFP
Pin Buffer
Type Type
Description
PORTJ is a bidirectional I/O port.
RJ0
62
RJ1/SEG33
RJ1
SEG33
61
RJ2/SEG34
RJ2
SEG34
60
RJ3/SEG35
RJ3
SEG35
59
RJ4/SEG39
RJ4
SEG39
39
RJ5/SEG38
RJ5
SEG38
40
RJ6/SEG37
RJ6
SEG37
41
RJ7/SEG36
RJ7
SEG36
42
I/O
ST
Digital I/O.
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
VSS
11, 31, 51, 70
P
—
Ground reference for logic and I/O pins.
VDD
32, 48, 71
P
—
Positive supply for logic and I/O pins.
AVSS
26
P
—
Ground reference for analog modules.
AVDD
25
P
—
Positive supply for analog modules.
ENVREG
24
I
ST
VDDCORE/VCAP
VDDCORE
12
VCAP
P
—
P
—
Enable for on-chip voltage regulator.
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39948A-page 26
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
12 inputs for all PIC18F87J93 family devices. This
module allows conversion of an analog input signal to
a corresponding 12-bit digital number.
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
The module has these registers:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCAL
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADCAL: A/D Calibration bit
1 = Calibration is performed on next A/D conversion
0 = Normal A/D converter operation (no calibration is performed)
bit 6
Unimplemented: Read as ‘0’
bit 5-2
CHS<3:0>: Analog Channel Select bits
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)
0110 = Channel 06 (AN6)
0111 = Channel 07 (AN7)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
11xx = Unused
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0
ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
© 2009 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39948A-page 27
PIC18F87J93 FAMILY
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIGSEL
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TRIGSEL: Special Trigger Select bit
1 = Selects the special trigger from the CTMU
0 = Selects the special trigger from the CCP2
bit 6
Unimplemented: Read as ‘0’
bit 5
VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = AVSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = AVDD
bit 3-0
PCFG<3:0>: A/D Port Configuration Control bits:
x = Bit is unknown
PCFG<3:0> AN11 AN10 AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
0000
A
A
A
A
A
A
A
A
A
A
A
A
0001
A
A
A
A
A
A
A
A
A
A
A
A
0010
A
A
A
A
A
A
A
A
A
A
A
A
0011
A
A
A
A
A
A
A
A
A
A
A
A
0100
D
A
A
A
A
A
A
A
A
A
A
A
0101
D
D
A
A
A
A
A
A
A
A
A
A
0110
D
D
D
A
A
A
A
A
A
A
A
A
0111
D
D
D
D
A
A
A
A
A
A
A
A
1000
D
D
D
D
D
A
A
A
A
A
A
A
1001
D
D
D
D
D
D
A
A
A
A
A
A
1010
D
D
D
D
D
D
D
A
A
A
A
A
1011
D
D
D
D
D
D
D
D
A
A
A
A
1100
D
D
D
D
D
D
D
D
D
A
A
A
1101
D
D
D
D
D
D
D
D
D
D
A
A
1110
D
D
D
D
D
D
D
D
D
D
D
A
1111
D
D
D
D
D
D
D
D
D
D
D
D
A = Analog input
DS39948A-page 28
D = Digital I/O
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0
ADCS<2:0>: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 29
PIC18F87J93 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS) or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF- pins.
A/D conversion. When the A/D conversion is complete,
the result is loaded into the ADRESH:ADRESL register
pair, the GO/DONE bit (ADCON0<1>) is cleared and the
A/D Interrupt Flag bit, ADIF, is set.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
The block diagram of the A/D module is shown in
Figure 2-1.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of the
FIGURE 2-1:
A/D BLOCK DIAGRAM(1,2)
CHS<3:0>
1011
1010
1001
1000
0111
0110
0101
0100
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
0010
0001
VCFG<1:0>
0000
AVDD
Reference
Voltage
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF+
VREFAVSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6XJ93 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39948A-page 30
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
2.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
3.
4.
5.
The following steps should be followed to do an A/D
conversion:
1.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 2-2:
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear ADIF bit, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
6.
7.
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
RS
VAIN
RIC ≤ 1k
ANx
CPIN
5 pF
VT = 0.6V
SS
RSS
ILEAKAGE
±100 nA
CHOLD = 25 pF
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
= Sampling Switch
SS
= Sample/Hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance
© 2009 Microchip Technology Inc.
Preliminary
VDD
1
2
3
4
Sampling Switch (kΩ)
DS39948A-page 31
PIC18F87J93 FAMILY
2.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
the minimum acquisition time before starting a
conversion.
Note:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 2 kΩ
85°C (system max.)
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 2-2:
VHOLD
or
TC
Equation 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
TACQ
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (1,024 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
A/D MINIMUM CHARGING TIME
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
TAMP
=
0.2 μs
TCOFF
=
(Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ
=
0.2 μs + 1 μs + 1.2 μs
2.4 μs
DS39948A-page 32
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
2.2
TABLE 2-1:
Selecting and Configuring
Automatic Acquisition Time
AD Clock Source (TAD)
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Operation
ADCS<2:0>
Maximum
Device
Frequency
2 TOSC
000
2.86 MHz
TOSC
100
5.71 MHz
8 TOSC
001
11.43 MHz
16 TOSC
101
22.86 MHz
32 TOSC
010
40.0 MHz
64 TOSC
110
40.0 MHz
RC(2)
x11
1.00 MHz(1)
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module continues
to sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisition
time is programmed, there may be no need to wait for an
acquisition time between selecting a channel and setting
the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
2.3
Selecting the A/D Conversion
Clock
4
Note 1: The RC source has a typical TAD time of
4 μs.
2: For device frequencies above 1 MHz, the
device must be in Sleep mode for the entire
conversion or the A/D accuracy may be out
of specification.
2.4
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for TAD:
•
•
•
•
•
•
•
TAD vs. DEVICE OPERATING
FREQUENCIES
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD.
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 33
PIC18F87J93 FAMILY
2.5
A/D Conversions
2.6
Figure 2-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
Figure 2-4 shows the operation of the A/D converter
after the GO/DONE bit has been set; the ACQT<2:0>
bits are set to ‘010’ and a 4 TAD acquisition time is
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note:
Use of the CCP2 Trigger
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 2-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
FIGURE 2-4:
TAD Cycles
TACQT Cycles
1
2
3
4
1
2
b9
Automatic
Acquisition
Time
4
5
b8
b7
b6
6
b5
7
b4
8
9
10
11
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
DS39948A-page 34
3
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
2.7
A/D Converter Calibration
The A/D converter in the PIC18F87J93 family of
devices includes a self-calibration feature which compensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (which means it is reading none of
the input channels) and store the resulting value
internally to compensate for offset. Thus, subsequent
offsets will be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
2.8
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
TABLE 2-2:
Name
INTCON
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
2
PIR1
—
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
2
PIE1
—
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
2
IPR1
—
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
2
PIR3
—
LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF
2
PIE3
—
LCDIE
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
2
IPR3
—
LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
2
ADRESH
A/D Result Register High Byte
2
ADRESL
A/D Result Register Low Byte
2
ADCON0
ADCAL
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
2
ADCON1
TRIGSEL
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
2
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
2
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
2
CCP2CON
PORTA
TRISA
RA7
(1)
RA6
(1)
TRISA7(1) TRISA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
2
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
2
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
2
TRISF
TRISF5
TRISF4
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
2: For these Reset values, see Section 4.0 “Reset” of the “PIC18F87J90 Family Data Sheet” (DS39933).
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 35
PIC18F87J93 FAMILY
NOTES:
DS39948A-page 36
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
3.0
SPECIAL FEATURES OF THE
CPU
3.1
Device ID Registers
The Device ID registers are “read-only” registers. They
identify the device type and revision for device
programmers and can be read by firmware using table
reads.
Note 1: This section documents only the CPU
features that are different from, or in addition to, the features of the PIC18F87J90
family devices.
2: For additional details on the Configuration
bits, refer to Section 24.1 “Configuration
Bits” in the “PIC18F87J90 Family Data
Sheet” (DS39933).
TABLE 3-1:
DEVICE ID REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value(1)
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(2)
3FFFFFh DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 10x1(2)
File Name
Legend:
Note 1:
2:
x = unknown, — = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
See Register 3-1 and Register 3-2 for DEVID values. These registers are read-only and cannot be programmed by
the user.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 37
PIC18F87J93 FAMILY
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J93 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-5
DEV<2:0>: Device ID bits
111 = PIC18F87J93
110 = PIC18F86J93
011 = PIC18F67J93
010 = PIC18F66J93
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J93 FAMILY DEVICES
R
DEV10
(1)
R
R
R
R
R
R
R
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-0
Note 1:
DEV<10:3>: Device ID bits(1)
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
0101 0000 = PIC18F87J93 family devices
The values for DEV<10:3> may be shared with other device families. The specific device is always
identified by using the entire DEV<10:0> bit sequence.
DS39948A-page 38
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
4.0
ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only the PIC18F87J93 family devices’ specifications that
differ from those of the PIC18F87J90 family devices. For detailed information on the electrical specifications
shared by the PIC18F87J93 family and PIC18F87J90 family devices, see the “PIC18F87J90 Family Data
Sheet” (DS39933).
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA
Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins .....................................................8 mA
Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA
Maximum current sunk by all ports combined.......................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 39
PIC18F87J93 FAMILY
VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL)(1)
FIGURE 4-1:
4.0V
3.6V
Voltage (VDD)
3.5V
3.0V
PIC18LF87J93 Family
2.5V
2.35V
2.0V
0
Note 1:
8 MHz
Frequency
48 MHz
When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before VDD reaches a level at which full-speed operation is not possible.
VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL)(1)
FIGURE 4-2:
3.00V
Voltage (VDDCORE)
2.75V
2.7V
2.50V
PIC18LF87J93 Family
2.35V
2.25V
2.00V
48 MHz
8 MHz
Frequency
Note 1:
When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE ≤ VDD ≤ 3.6V.
DS39948A-page 40
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
TABLE 4-1:
Param
No.
Sym
A/D CONVERTER CHARACTERISTICS: PIC18F87J93 FAMILY (INDUSTRIAL)
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
—
—
12
bit
ΔVREF ≥ 3.0V
A03
EIL
Integral Linearity Error
—
<±1
±2.0
LSB
ΔVREF ≥ 3.0V
A04
EDL
Differential Linearity Error
—
<±1
±1.5
LSB
ΔVREF ≥ 3.0V
A06
EOFF
Offset Error
—
<±1
±5
LSB
ΔVREF ≥ 3.0V
A07
EGN
Gain Error
—
<±1
±3
LSB
ΔVREF ≥ 3.0V
A10
—
Monotonicity
A20
ΔVREF Reference Voltage Range
(VREFH – VREFL)
A21
VREFH Reference Voltage High
A22
VREFL Reference Voltage Low
A25
VAIN
A30
A50
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
—
VDD – VSS
V
For 12-bit resolution
VSS + 3.0V
—
VDD + 0.3V
V
For 12-bit resolution
VSS – 0.3V
—
VDD – 3.0V
V
For 12-bit resolution
Analog Input Voltage
VREFL
—
VREFH
V
Note 2
ZAIN
Recommended
Impedance of Analog
Voltage Source
—
—
2.5
kΩ
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA
μA
Note 1:
2:
3
During VAIN acquisition.
During A/D conversion cycle.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from
the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 41
PIC18F87J93 FAMILY
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK(1)
132
11
A/D DATA
10
...
9
...
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
Param
Symbol
No.
A/D CONVERSION REQUIREMENTS
Characteristic
Min
Max
Units
130
TAD
A/D Clock Period
0.8
12.5(1)
μs
131
TCNV
Conversion Time
(not including acquisition time)(2)
13
14
TAD
132
TACQ
Acquisition Time(3)
1.4
—
μs
135
TSWC
Switching Time from Convert → Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
Note 1:
2:
3:
4:
Conditions
TOSC based, VREF ≥ 3.0V
μs
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
DS39948A-page 42
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F87J93
Family Data Sheet” (DS39933).
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 43
PIC18F87J93 FAMILY
NOTES:
DS39948A-page 44
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
APPENDIX A:
REVISION HISTORY
APPENDIX B:
Revision A (June 2009)
Original data sheet for PIC18F87J93 family devices.
TABLE B-1:
DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
PIC18F87J93 FAMILY DEVICE DIFFERENCES
Features
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
PIC18F66J93
PIC18F67J93
PIC18F86J93
PIC18F87J93
64K
128K
64K
128K
32768
65536
32768
65536
28
28
29
29
Ports A, B, C, D, E,
F, G
Ports A, B, C, D, E,
F, G
Ports A, B, C, D, E,
F, G, H, J
Ports A, B, C, D, E,
F, G, H, J
Capture/Compare/PWM Modules
2
2
2
2
Enhanced
Capture/Compare/PWM Modules
3
3
3
3
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
I/O Ports
Packages
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 45
PIC18F87J93 FAMILY
APPENDIX C:
CONVERSION
CONSIDERATIONS
APPENDIX D:
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
DS39948A-page 46
MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Baseline
device (such as the PIC16C5X) to an Enhanced MCU
device (such as the PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Currently Available
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
INDEX
A
E
A/D
Electrical Characteristics .................................................... 39
Equations
A/D Acquisition Time .................................................. 32
A/D Minimum Charging Time...................................... 32
Calculating the Minimum Required
Acquisition Time ................................................. 32
Errata .................................................................................... 6
A/D Converter Interrupt, Configuring .......................... 31
Acquisition Requirements ........................................... 32
ADCAL Bit ................................................................... 35
ADCON0 Register....................................................... 27
ADCON1 Register....................................................... 27
ADCON2 Register....................................................... 27
ADRESH Register................................................. 27, 30
ADRESL Register ....................................................... 27
Analog Port Pins, Configuring ..................................... 33
Associated Registers .................................................. 35
Configuring the Module ............................................... 31
Conversion Clock (TAD) .............................................. 33
Conversion Status (GO/DONE Bit) ............................. 30
Conversions ................................................................ 34
Converter Calibration .................................................. 35
Converter Characteristics ........................................... 41
Operation in Power-Managed Modes ......................... 35
Overview ..................................................................... 27
Selecting and Configuring Automatic
Acquisition Time.................................................. 33
Special Event Trigger (CCP)....................................... 34
Use of the CCP2 Trigger............................................. 34
Absolute Maximum Ratings ................................................ 39
ADCAL Bit ........................................................................... 35
ADCON0 Register............................................................... 27
GO/DONE Bit .............................................................. 30
ADCON1 Register............................................................... 27
ADCON2 Register............................................................... 27
ADRESH Register............................................................... 27
ADRESL Register ......................................................... 27, 30
Analog-to-Digital Converter. See A/D.
B
Block Diagrams
A/D .............................................................................. 30
Analog Input Model ..................................................... 31
PIC18F66J93/67J93 ..................................................... 9
PIC18F86J93/87J93 ................................................... 10
C
Compare (CCP Module)
Special Event Trigger.................................................. 34
Conversion Considerations ................................................. 46
Customer Change Notification Service ............................... 49
Customer Notification Service............................................. 49
Customer Support ............................................................... 49
D
Device Differences .............................................................. 45
Device Overview
Detailed Features.......................................................... 7
Features (64-Pin Devices) ............................................ 8
Features (80-Pin Devices) ............................................ 8
Special Features ........................................................... 7
DS39948A-page 47
F
Features Summary
Device Overview........................................................... 1
Flexible Oscillator Structure.......................................... 1
LCD Driver and Keypad Interface................................. 1
Low Power .................................................................... 1
Peripheral Highlights..................................................... 1
Special Microcontroller Attributes ................................. 2
I
Internet Address ................................................................. 49
Interrupt Sources
A/D Conversion Complete .......................................... 31
M
Microchip Internet Web Site................................................ 49
Migration From Baseline to Enhanced Devices.................. 46
P
Packaging Information ........................................................ 43
Pin Diagrams
PIC18F66J93/67J93 ..................................................... 3
PIC18F86J93/87J93 ..................................................... 4
Pin Functions
AVDD ........................................................................... 17
AVDD ........................................................................... 26
AVSS ........................................................................... 17
AVSS ........................................................................... 26
ENVREG .............................................................. 17, 26
LCDBIAS3 ............................................................ 15, 22
MCLR ................................................................... 11, 18
OSC1/CLKI/RA7 ................................................... 11, 18
OSC2/CLKO/RA6 ................................................. 11, 18
RA0/AN0............................................................... 11, 18
RA1/AN1/SEG18 .................................................. 11, 18
RA2/AN2/VREF- .................................................... 11, 18
RA3/AN3/VREF+ ................................................... 11, 18
RA4/T0CKI/SEG14 ............................................... 11, 18
RA5/AN4/SEG15 .................................................. 11, 18
RB0/INT0/SEG30 ................................................. 12, 19
RB1/INT1/SEG8 ................................................... 12, 19
RB2/INT2/SEG9/CTED1....................................... 12, 19
RB3/INT3/SEG10/CTED2..................................... 12, 19
RB4/KBI0/SEG11 ................................................. 12, 19
RB5/KBI1/SEG29 ................................................. 12, 19
RB6/KBI2/PGC ..................................................... 12, 19
RB7/KBI3/PGD ..................................................... 12, 19
RC0/T1OSO/T13CKI ............................................ 13, 20
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
RC1/T1OSI/CCP2/SEG32 .................................... 13, 20
RC2/CCP1/SEG13................................................ 13, 20
RC3/SCK/SCL/SEG17 .......................................... 13, 20
RC4/SDI/SDA/SEG16 ........................................... 13, 20
RC5/SDO/SEG12 ................................................. 13, 20
RC6/TX1/CK1/SEG27........................................... 13, 20
RC7/RX1/DT1/SEG28 .......................................... 13, 20
RD0/SEG0/CTPLS................................................ 14, 21
RD0/SEG1 .................................................................. 14
RD1/SEG1 .................................................................. 21
RD2/SEG2 ............................................................ 14, 21
RD3/SEG3 ............................................................ 14, 21
RD4/SEG4 ............................................................ 14, 21
RD5/SEG5 ............................................................ 14, 21
RD6/SEG6 ............................................................ 14, 21
RD7/SEG7 ............................................................ 14, 21
RE0/LCDBIAS1..................................................... 15, 22
RE1/LCDBIAS2..................................................... 15, 22
RE3/COM0............................................................ 15, 22
RE4/COM1............................................................ 15, 22
RE5/COM2............................................................ 15, 22
RE6/COM3............................................................ 15, 22
RE7/CCP2/SEG31 ................................................ 15, 22
RF1/AN6/C2OUT/SEG19 ..................................... 16, 23
RF2/AN7/C1OUT/SEG20 ..................................... 16, 23
RF3/AN8/SEG21/C2INB ....................................... 16, 23
RF4/AN9/SEG22/C2INA ....................................... 16, 23
RF5/AN10/CVREF/SEG23/C1INB ......................... 16, 23
RF6/AN11/SEG24/C1INA ..................................... 16, 23
RF7/AN5/SS/SEG25 ............................................. 16, 23
RG0/LCDBIAS0 .................................................... 17, 24
RG1/TX2/CK2 ....................................................... 17, 24
RG2/RX2/DT2/VLCAP1 .......................................... 17, 24
RG3/VLCAP2.......................................................... 17, 24
RG4/SEG26/RTCC ............................................... 17, 24
RH0/SEG47 ................................................................ 25
RH1/SEG46 ................................................................ 25
RH2/SEG45 ................................................................ 25
RH3/SEG44 ................................................................ 25
RH4/SEG40 ................................................................ 25
RH5/SEG41 ................................................................ 25
RH6/SEG42 ................................................................ 25
RH7/SEG43 ................................................................ 25
RJ0.............................................................................. 26
RJ1/SEG33 ................................................................. 26
RJ2/SEG34 ................................................................. 26
RJ3/SEG35 ................................................................. 26
RJ4/SEG39 ................................................................. 26
RJ5/SEG38 ................................................................. 26
RJ6/SEG37 ................................................................. 26
RJ7/SEG36 ................................................................. 26
VDD ............................................................................. 17
VDD ............................................................................. 26
VDDCORE/VCAP ...................................................... 17, 26
VSS .............................................................................. 17
VSS .............................................................................. 26
DS39948A-page 48
Pinout I/O Descriptions
PIC18F6XJ93 ............................................................. 11
PIC18F8XJ93 ............................................................. 18
Product Identification System ............................................. 51
R
Reader Response............................................................... 50
Registers
ADCON0 (A/D Control 0)............................................ 27
ADCON1 (A/D Control 1)............................................ 28
ADCON2 (A/D Control 2)............................................ 29
DEVID1 (Device ID 1)................................................. 38
DEVID2 (Device ID 2)................................................. 38
Revision History.................................................................. 45
S
Special Features of the CPU .............................................. 37
T
Timing Diagrams
A/D Conversion........................................................... 42
Timing Diagrams and Specifications
A/D Conversion Requirements ................................... 42
V
Voltage-Frequency Graphs
Regulator Disabled, Industrial..................................... 40
Regulator Enabled, Industrial ..................................... 40
W
Worldwide Sales and Service Offices................................. 52
WWW Address ................................................................... 49
WWW, On-Line Support ....................................................... 6
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2009 Microchip Technology Inc.
Preliminary
DS39948A-page 49
PIC18F87J93 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Application (optional):
Would you like a reply?
Y
Device: PIC18F87J93 Family
N
Literature Number: DS39948A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39948A-page 50
Preliminary
© 2009 Microchip Technology Inc.
PIC18F87J93 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain purchasing information such as pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device(1,2)
PIC18F66J93, PIC18F66J93T
PIC18F67J93, PIC18F67J93T
PIC18F86J93, PIC18F86J93T
PIC18F87J93, PIC18F87J93T
Temperature Range
I=
Package
PT = TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
PIC18F87J93-I/PT 301 = Industrial temperature,
TQFP package, QTP pattern #301.
PIC18F87J93T-I/PT = Tape and reel, Industrial
temperature, TQFP package.
-40°C to +85°C (Industrial)
© 2009 Microchip Technology Inc.
Preliminary
Note 1: F
2: T
= Standard Voltage Range
= In Tape and Reel
DS39948A-page 51
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
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Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
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Kokomo, IN
Tel: 765-864-8360
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Tel: 949-462-9523
Fax: 949-462-9608
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Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
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Tel: 82-53-744-4301
Fax: 82-53-744-4302
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Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/26/09
DS39948A-page 52
Preliminary
© 2009 Microchip Technology Inc.