ispLSI 1016E ® In-System Programmable High Density PLD Features B7 A2 Logic A3 Array B5 D Q D Q GLB B4 B3 A4 D Q B2 A5 B1 A6 Global Routing Pool (GRP) EW A7 • IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP™) 5V Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping B6 ES IG N • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power D Q D Output Routing Pool A0 A1 Output Routing Pool • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic S Functional Block Diagram B0 CLK 0139C1-isp N Description The ispLSI 1016E is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. 01 6 EA FO R • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity U SE is p LS I1 The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016e_08 1 January 2002 Specifications ispLSI 1016E Functional Block Diagram Figure 1. ispLSI 1016E Functional Block Diagram D ES IG N S Generic Logic Blocks (GLBs) GOE 0/IN 3 MODE/IN 2 Output Routing Pool (ORP) B5 A2 B4 EW Global Routing Pool (GRP) A3 B3 A4 B2 I/O 12 I/O 13 I/O 14 I/O 15 N A5 A6 R I/O 8 I/O 9 I/O 10 I/O 11 B6 A1 Input Bus I/O 4 I/O 5 I/O 6 I/O 7 A0 FO A7 B0 Clock Distribution Network Megablock Y0 Y1/RESET* SCLK/Y2 16 ispEN 10 *Note: Y1 and RESET are multiplexed on the same pin I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 B1 EA SDI/IN 0 SDO/IN 1 lnput Bus I/O 0 I/O 1 I/O 2 I/O 3 I/O 31 I/O 30 I/O 29 I/O 28 Output Routing Pool (ORP) B7 CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 0139B(1a)-isp The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. is pL SI The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. U SE Clocks in the ispLSI 1016E device are selected using the Clock Distribution Network. Three dedicated clock pins (Y0, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016E device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1016E device contains two Megablocks. 2 Specifications ispLSI 1016E Absolute Maximum Ratings 1 Supply Voltage VCC ................................ -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V S Storage Temperature ................................ -65 to 150°C D ES IG N Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). SYMBOL EW DC Recommended Operating Conditions PARAMETER VIL VIH Input Low Voltage UNITS TA = 0°C to + 70°C 4.75 5.25 V Industrial TA = -40°C to + 85°C 4.5 5.5 V 0 0.8 V 2.0 EA Vcc+1 V Table 2-0005/1016E FO Input High Voltage Capacitance (TA=25oC, f=1.0 MHz) MAX. Commercial N Supply Voltage R VCC MIN. TYPICAL UNITS C1 Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) 8 pf VCC = 5.0V, VPIN = 2.0V C2 Y0 Clock Capacitance 12 pf VCC = 5.0V, VPIN = 2.0V 16 PARAMETER TEST CONDITIONS Table 2-0006/1016E 10 SYMBOL is pL SI Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – Cycles Data Retention Table 2-0008/1016E U SE Erase/Reprogram Cycles 3 Specifications ispLSI 1016E Switching Test Conditions Figure 2. Test Load GND to 3.0V -125 ≤ 2 ns -100, -80 ≤ 3 ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 Device Output See Figure 2 Table 2-0003/1016E 3-state levels are measured 0.5V from steady-state active level. S Input Rise and Fall Time 10% to 90% Test Point D ES IG N Input Pulse Levels R2 Output Load Conditions (see Figure 2) R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF A B C *CL includes Test Fixture and Probe Capacitance. 0213a EW R1 N TEST CONDITION CL* FO R Table 2-0004/1016E DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS1 Output Low Voltage ICC2, 4 Output High Voltage CONDITION 3 MIN. TYP. IOL= 8 mA – – IOH = -4 mA EA PARAMETER MAX. UNITS 0.4 V – – V 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA Operating Power Supply Current VIL = 0.5V, VIH = 3.0V Commercial – 90 – mA fCLOCK = 1 MHz Industrial – 90 – mA is pL SI 10 16 2.4 Input or I/O Low Leakage Current Table 2-0007/1016E U SE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 4 Specifications ispLSI 1016E External Timing Parameters Over Recommended Operating Conditions 4 -80 -100 MIN. MAX. MIN. MAX. MIN. MAX. UNITS 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 ns A 2 Data Prop. Delay, Worst Case Path – 10.0 – 13.0 – 18.5 ns 125 – 100 – 84.0 – 100 – – 3 Clk. Frequency with Int. Feedback 4 Clk. Frequency with Ext. Feedback( 1 tsu2 + tco1 1 twh + tw1 ) – 5 Clk. Frequency, Max. Toggle( – 6 GLB Reg. Setup Time before Clk., 4 PT Bypass ) A – 167 – 5.0 – 7 GLB Reg. Clk. to Output Delay, ORP Bypass – 4.5 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 0.0 – 9 GLB Reg. Setup Time before Clk. – 10 GLB Reg. Clk. to Output Delay – 11 GLB Reg. Hold Time after Clk. 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable C 15 Input to Output Disable 5.5 0.0 – R – B – – – MHz – 57.0 – MHz 125 – 100 – MHz 7.0 – 8.5 – ns – 5.0 – 8.0 ns 0.0 – 0.0 – ns 8.0 – 9.5 – ns – 6.0 – 9.5 ns 0.0 – 0.0 – ns 13.5 – 17.0 ns 77.0 10.0 – 5.0 – 6.5 – ns 12.0 – 15.0 10.0 – – – 20.0 ns – 12.0 – 15.0 – 20.0 ns – 7.0 – 9.0 – 10.5 ns – 7.0 – 9.0 – 10.5 ns N A 5.5 EW – D ES IG N A 3 S A 16 Global OE Output Enable 17 Global OE Output Disable – 18 Ext. Sync. Clk. Pulse Duration, High 3.0 – 4.0 – 5.0 – ns – 19 Ext. Sync. Clk. Pulse Duration, Low 3.0 – 4.0 – 5.0 – ns – 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – 3.5 – 4.5 – ns – 0.0 – ns – FO B C 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – 10 Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions Section. U SE is pL SI 1. 2. 3. 4. -125 DESCRIPTION1 16 tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 TEST #2 COND. EA PARAMETER 5 0.0 Table 2-0030-16/125,100, 80 Specifications ispLSI 1016E Internal Timing Parameters1 PARAMETER 2 # -100 -125 DESCRIPTION -80 MIN. MAX. MIN. MAX. MIN. MAX. UNITS 22 I/O Register Bypass – 0.3 – 0.4 – 0.6 ns 23 I/O Latch Delay – 1.8 – 2.4 – 3.6 ns ns 24 I/O Register Setup Time before Clock 3.0 – 25 I/O Register Hold Time after Clock -0.3 – – 4.0 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay torp torpbp 5.0 7.5 ns 5.0 – 7.5 ns – 2.6 – 3.9 ns – 1.9 – 2.9 ns – 2.2 29 GRP Delay, 1 GLB Load – 1.8 30 GRP Delay, 4 GLB Loads – 1.9 – 2.2 – 3.3 ns – 2.1 – 2.5 – 3.8 ns – 2.4 – 3.1 – 4.7 ns – 3.9 – 5.7 – 8.1 ns 35 4 Product Term Bypass Path Delay (Registered) – 3.9 – 5.6 – 7.3 ns – 4.4 – 6.1 – 7.1 ns – 4.4 – 6.1 – 8.2 ns – 4.4 – 6.6 – 8.3 ns – 1.0 – 1.6 – 1.9 ns 40 GLB Register Setup Time before Clock 0.2 – 0.2 – -0.6 – ns 41 GLB Register Hold Time after Clock 1.5 – 2.5 – 4.3 – ns 42 GLB Register Clock to Output Delay – 1.8 – 1.9 – 2.9 ns 43 GLB Register Reset to Output Delay – 4.4 – 6.3 – 7.0 ns 44 GLB Product Term Reset to Register Delay – 3.5 – 5.1 – 7.2 ns EW 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads R 34 4 Product Term Bypass Path Delay (Combinatorial) 36 1 Product Term/XOR Path Delay 37 20 Product Term/XOR Path Delay EA 38 XOR Adjacent Path Delay 3 10 16 39 GLB Register Bypass Delay – 5.5 – 7.1 – 9.7 ns 3.2 3.5 4.8 5.3 6.8 7.5 ns 47 ORP Delay – 1.0 – 1.0 – 1.5 ns 48 ORP Bypass Delay – 0.0 – 0.0 – 0.0 ns 45 GLB Product Term Output Enable to I/O Cell Delay is pL SI ORP ns – GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck – – -0.6 – 28 Dedicated Input Delay GRP tgrp1 tgrp4 tgrp8 tgrp16 4.5 – N 4.0 – -0.4 FO – 3.5 – D ES IG N tiobp tiolat tiosu tioh tioco tior tdin S Inputs 46 GLB Product Term Clock Delay U SE 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice hard macros. 6 Table 2-0036-16/125,100, 80 Specifications ispLSI 1016E Internal Timing Parameters1 PARAMETER #2 -80 -100 -125 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS Outputs – 1.4 – 1.7 – 3.0 ns 50 Output Slew Limited Delay Adder – 10.0 – 10.0 – 10.0 ns 51 I/O Cell OE to Output Enabled – 4.3 – 5.3 – 6.4 ns 52 I/O Cell OE to Output Disabled – 4.3 – 5.3 – 6.4 ns 53 Global Output Enable – 2.7 – 3.7 – 4.1 ns 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.3 1.3 1.4 1.4 2.1 2.1 ns 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.3 2.7 2.4 2.9 3.6 4.4 ns 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 1.8 0.8 1.8 1.2 2.7 ns 57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line 0.0 0.3 0.0 0.4 0.0 0.6 ns 0.8 1.8 0.8 1.8 1.2 2.7 ns – 3.2 – 4.5 – 5.5 ns tgy0 tgy1/2 tgcp tioy1/2 tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line tgr 59 Global Reset to GLB and I/O Registers U SE is pL SI 10 16 EA FO R 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. N Global Reset 7 EW Clocks S 49 Output Buffer Delay D ES IG N tob tsl toen todis tgoe Table 2-0037-16/125,100,80 Specifications ispLSI 1016E ispLSI 1016E Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Comb 4 PT Bypass #34 Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #35 #39 #48 GRP Loading Delay 20 PT XOR Delays GLB Reg Delay ORP Delay #29, 31, 32 #36-38 I/O Reg Bypass I/O Pin (Input) #22 #30 Input D Register Q RST #23 - 27 #59 D Q #59 Clock Distribution Y1,2 #40-43 Control RE PTs OE #44-46 CK #55-58 EW #54 Y0 #53 N GOE 0 Derivations of tsu, th and tco from the Product Term Clock 1 = = = 1.4 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2) th = = = 0.6 ns = Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4) tco = = = 9.9 ns = Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4) 10 16 EA FO R tsu is pL SI Derivations of tsu, th and tco from the Clock GLB 1 = = = 2.9 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8) th = = = -0.2 ns = Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4) U SE tsu tco = = = 9.1 ns = Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4) Table 2-0042-16 1. Calculations are based upon timing specifications for the ispLSI 1016E-125 8 #51, 52 I/O Pin (Output) #47 RST Reset #49, 50 S #28 D ES IG N Ded. In 0491-16 Specifications ispLSI 1016E Maximum GRP Delay vs GLB Loads ispLSI 1016E-80 3 ispLSI 1016E-125 1 1 8 4 16 12 GLB Load 16E GRP/GLB.eps EW Power Consumption N Figure 3 shows the relationship between power and operating speed. Power consumption in the ispLSI 1016E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. R Figure 3. Typical Device Power Consumption vs fmax FO 130 ispLSI 1016E 120 EA 100 10 80 16 ICC (mA) 110 90 0 is pL SI S 2 D ES IG N GRP Delay (ns) ispLSI 1016E-100 20 40 60 80 100 120 140 fmax (MHz) Notes: Configuration of four 16-bit counters Typical current at 5V, 25°C ICC can be estimated for the ispLSI 1016E using the following equation: U SE ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004) Where: # of PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127B-16-80-isp/1016 9 Specifications ispLSI 1016E Pin Description PLCC PIN NUMBERS NAME 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 15, 19, 25, 29, 37, 41, 3, 7, GOE 0/IN 32 2 40 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. ispEN 13 7 Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. SDI/IN 01 14 8 Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. It is a dedicated input pin when ispEN is logic high.SDI/IN0 also is used as one of the two control pins for the isp state machine. MODE/IN 21 36 30 Input - This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. SDO/IN 11 24 18 Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. SCLK/Y21 33 27 Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Y0 11 5 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. Y1/RESET 35 29 S Input/Output Pins - These are the general purpose I/O pins used by the logic array. D ES IG N 18, 22, 28, 32, 40, 44, 6, 10 9, 13, 19, 23, 31, 35, 41, 1, I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 EW 17, 21, 27, 31, 39, 43, 5, 9, DESCRIPTION GND 1, VCC 12, 34 This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. 17, 39 Ground (GND) 6, Vcc 28 is pL SI 23 10 16 EA FO R N 16, 20, 26, 30, 38, 42, 4, 8, TQFP PIN NUMBERS Table 2-0002C-16-isp U SE 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. 10 Specifications ispLSI 1016E Pin Configurations I/O 20 I/O 19 I/O 21 I/O 22 I/O 23 GND GOE 0/IN 32 I/O 24 I/O 26 I/O 25 I/O 27 ispLSI 1016E 44-Pin PLCC Pinout Diagram 7 8 I/O 30 9 I/O 31 10 11 Y0 VCC 39 I/O 18 38 37 I/O 17 I/O 16 36 MODE/IN 21 D ES IG N I/O 29 I/O 28 S 6 5 4 3 2 1 44 43 42 41 40 12 ispLSI 1016E 35 34 Y1/RESET VCC Top View 13 33 SCLK/Y21 14 32 I/O 15 I/O 0 15 31 I/O 14 I/O 1 I/O 2 16 17 30 29 I/O 13 I/O 12 EW ispEN SDI/IN 0 1 N I/O 10 I/O 11 R I/O 9 I/O 8 GND SDO/IN 1 1 I/O 7 I/O 6 I/O 4 I/O 5 I/O 3 18 19 20 21 22 23 24 25 26 27 28 FO 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. EA 0123A-isp1016 10 is pL SI I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN 0 I/O 0 I/O 1 I/O 2 I/O 21 I/O 20 I/O 19 I/O 22 GND I/O 23 GOE 0/IN 32 I/O 24 44 43 42 41 40 39 38 37 36 35 34 33 I/O 18 32 31 I/O 17 I/O 16 30 MODE/IN 21 29 28 Y1/RESET VCC 27 SCLK/Y21 8 26 I/O 15 9 10 11 25 24 23 I/O 14 I/O 13 I/O 12 1 2 3 4 5 ispLSI 1016E 6 Top View 7 I/O 9 I/O 10 I/O 11 I/O 8 GND 1 1SDO/IN I/O 7 I/O 6 I/O 4 I/O 5 12 13 14 15 16 17 18 19 20 21 22 I/O 3 U SE 1SDI/IN I/O 26 I/O 25 I/O 27 16 ispLSI 1016E 44-Pin TQFP Pinout Diagram 1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. 0851-16E/TQFP 11 Specifications ispLSI 1016E Part Number Description ispLSI 1016E – XXX X XXX X Grade Blank = Commercial I = Industrial Device Family S Device Number Package J = PLCC T44 = TQFP D ES IG N Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 84 MHz fmax Power L = Low 0212/1016E ispLSI 1016E Ordering Information ORDERING NUMBER PACKAGE 125 7.5 ispLSI 1016E-125LJ 44-Pin PLCC 125 7.5 ispLSI 1016E-125LT44 100 10 N 44-Pin TQFP ispLSI 1016E-100LJ 44-Pin PLCC 100 10 ispLSI 1016E-100LT44 84 15 84 15 R tpd (ns) 44-Pin TQFP ispLSI 1016E-80LJ 44-Pin PLCC ispLSI 1016E-80LT44 44-Pin TQFP FO ispLSI fmax (MHz) EA FAMILY EW COMMERCIAL Table 2-0041A/1016E INDUSTRIAL tpd (ns) 84 84 ORDERING NUMBER PACKAGE 15 ispLSI 1016E-80LJI 44-Pin PLCC 15 ispLSI 1016E-80LT44I 44-Pin TQFP 10 ispLSI fmax (MHz) 16 FAMILY U SE is pL SI Table 2-0041B/1016E 12