Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the nine inputs (Ia, Ib) has a shorter propagation delay and, therefore, is ideal as the expansion input for parity generation of wider data. A Compare output (C) is also provided which allows comparison of two 8-bit words. A logic LOW on the C output indicates a match. The inputs on this device have 75KΩ pull-down resistors. Max. propagation delay of 2200ps IEE min. of –70mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 15% faster than Fairchild 300K Approximately 30% lower power than Fairchild 300K Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages BLOCK DIAGRAM I0a I1a I2a I3a Za I4a I5a I6a I7a Ia C I0b I1b I2b I3b I4b I5b Zb I6b I7b Ib M9999-032406 [email protected] or (408) 955-1690 Rev.: H 1 Amendment: /0 Issue Date: March 2006 SY100S360 Micrel, Inc. I1a I0a Ordering Information I2a I4a I3a VEES I5a PACKAGE/ORDERING INFORMATION 11 10 9 8 7 6 5 I6a I7a VEE VEES 12 13 4 3 14 15 2 1 I1b 16 17 I2b 18 I0b Top View PLCC J28-1 Ia Za VCCA VCC VCC 28 27 C 26 I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13 7 8 9 10 11 12 I0a Commercial SY100S360FC Sn-Pb F24-1 Commercial SY100S360FC Sn-Pb SY100S360JC J28-1 Commercial SY100S360JC Sn-Pb J28-1 Commercial SY100S360JC Sn-Pb SY100S360JZ J28-1 Commercial SY100S360JZ with Pb-Free bar-line indicator Matte-Sn SY100S360JZTR(1, 2) J28-1 Commercial SY100S360JZ with Pb-Free bar-line indicator Matte-Sn SY100S360JCTR (1) (2) Za Ia VCC VCCA Top View Flatpack F24-1 C F24-1 SY100S360FCTR(1) I6a I7a 24 23 22 21 20 19 18 Zb SY100S360FC I6b I7b Ib VEES I3b I4b I5b I1b I0b VEE I2b 1 6 Lead Finish 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. I3b Ib Package Marking Notes: 28-Pin PLCC (J28-1) 4 5 Operating Range Zb 19 20 21 22 23 24 25 I7b Package Type Part Number 24-Pin Cerpack (F24-1) M9999-032406 [email protected] or (408) 955-1690 2 SY100S360 Micrel, Inc. TRUTH TABLE(1) PIN NAMES Pin Function Ia, Ib, Ina, Inb Data Inputs (n = 1...7) Za – Zb Parity Odd Outputs C Compare Output VEES VEE Substrate VCCA VCCO for ECL Outputs Sum of High Inputs Output Z Even HIGH Odd LOW Note: 1. Comparator Function: C = (I0a ⊕ I1a) + (I2a ⊕ I3a) + (I4a ⊕ I5a) + (I6a ⊕ I7a) + (I0b ⊕ I1b) + (I2b ⊕ I3b) + (I4b ⊕ I5b) + (I6b ⊕ I7b) DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current Ia, Ib Ina, Inb Power Supply Current Min. Typ. Max. — — — — 300 200 –70 –45 –30 Unit Condition µA VIN = VIH (Max.) mA Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Ina, Inb to Za, Zb 500 2300 500 2300 500 2300 ps tPLH tPHL Propagation Delay Ina, Inb to C 500 1800 500 1800 500 1800 ps tPLH tPHL Propagation Delay Ia, Ib to Za, Zb 300 1000 300 1000 300 1000 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps Condition PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Ina, Inb to Za, Zb 500 2200 500 2200 500 2200 ps tPLH tPHL Propagation Delay Ina, Inb to C 500 1700 500 1700 500 1700 ps tPLH tPHL Propagation Delay Ia, Ib to Za, Zb 300 900 300 900 300 900 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps M9999-032406 [email protected] or (408) 955-1690 3 Condition SY100S360 Micrel, Inc. TIMING DIAGRAM 0.7 ± 0.1 ns 0.7 ± 0.1 ns INPUT –0.95V 80% 50% 20% –1.69V TRUE tPHL tPLH 50% tPLH OUTPUT tPHL 80% 50% 20% COMPLEMENT tTLH tTHL Propagation Delay and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND M9999-032406 [email protected] or (408) 955-1690 4 SY100S360 Micrel, Inc. 24-PIN CERPACK (F24-1) Rev. 03 M9999-032406 [email protected] or (408) 955-1690 5 SY100S360 Micrel, Inc. 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-032406 [email protected] or (408) 955-1690 6