SY89841U Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer General Description The SY89841U is a low jitter LVDS, 2:1 input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89841U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or “runt” pulses during switchover. In addition, a unique Fail-safe Input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV). The differential input includes Micrel’s unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DCcoupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The outputs are 350mV, LVDS with fast rise/fall times guaranteed to be less than 150ps. The SY89841U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89841U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at: www.micrel.com. Precision Edge® Features • Selects between two sources, and provides a glitch-free, stable LVDS output • Guaranteed AC performance over temperature and supply voltage: – wide operating frequency: 1kHz to >1.5GHz – <870ps In-to-Out tpd – <150ps tr/tf • Unique patent-pending input isolation design minimizes crosstalk • Fail-safe input prevents oscillations • Ultra-low jitter design: – <1psrms random jitter – <1psrms cycle-to-cycle jitter – <10pspp total jitter (clock) – <0.7psrms MUX crosstalk induced jitter • Unique patent-pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS) • 350mV LVDS output swing • 2.5V +5% power supply • –40°C to +85°C industrial temperature range • Available in 16-pin (3mm x 3mm) MLF™ package Applications • Redundant clock switchover • Fail-safe clock protection Markets • • • • LAN/WAN Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. February 2005 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Typical Application Primary Clock From System IN0 50Ω VT0 50Ω /IN0 VREF-AC0 Secondary Clock From Local Oscillator IN1 50Ω VT1 50Ω /IN1 VREF-AC1 SEL (LVTTL/CMOS) February 2005 Primary Clock 2:1 MUX Secondary Clock 0 SEL MUX 1 Select Primary Select Secondary OUTPUT S Runt pulse eliminated from output Switchover occurs Simplified Example Illustrating Runt Pulse Eliminator (RPE) Circuit when Primary Clock Fails Runt Pulse Elimination Logic 2 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89841UMG MLF-16 Industrial 841U with Pb-Free bar-line Indicator NiPdAu Pb-Free SY89841UMGTR(2) MLF-16 Industrial 841U with Pb-Free bar-line Indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only. 2. Tape and Reel. IN1 VT1 VREF-AC1 /IN1 Pin Configuration 16 15 14 13 VREF-AC0 2 11 CAP VT0 3 10 SEL IN0 4 9 GND 5 6 7 8 VCC VCC /Q 12 Q 1 VCC /IN0 16-Pin MLF™ (MLF-16) February 2005 3 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Pin Description Pin Number Pin Name Pin Function 4, 1, 16, 13 IN0, /IN0, IN1, /IN1 Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Please refer to the “Input Interface Applications” section for more details. VREF-AC0 VREF-AC1 Reference Voltage: This output biases to VCC –1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. See the “Input Interface Applications” section for more details. 3, 15 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See the “Input Interface Applications” section for more details. 5, 8, 12 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins as possible. 6, 7 Q, /Q Differential Outputs: This LVDS differential output is a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table below for details. 10 SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. 9 GND Exposed Pad 2, 14 11 CAP Ground: Ground and exposed pad must be connected to the same ground plane. Power-On Reset (POR) Initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See “Power-On Reset (POR) Description” section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open. Truth Table Inputs February 2005 Outputs IN0 /IN0 IN1 /IN1 SEL Q /Q 0 1 X X 0 0 1 1 0 X X 0 1 0 X X 0 1 1 0 1 X X 1 0 1 1 0 4 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC)............................. –0.5V to +4.0V Input Voltage (VIN)..................................... –0.5V to VCC Termination Current Source or sink current on VT..................... ±100mA Source or sink current on IN, /IN................ ±50mA VREF-AC Source or sink current.............................. ±2mA Lead Temperature (soldering, 20 sec.)............ +260°C Storage Temperature (Ts) ...................–65°C to 150°C Supply Voltage (VCC) ....................+2.375V to +2.625V Ambient Temperature (TA) .................. –40°C to +85°C Package Thermal Resistance(3) MLF™ (JA) Still-Air ........................................................ 60°C/W MLF™ (JB) Junction-to-Board ...................................... 33°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply ICC Power Supply Current RIN Input Resistance (IN-to-VT) RDIFF_IN Condition Min Typ Max Units 2.625 V 85 120 mA 45 50 55 Differential Input Resistance (IN-to-/IN) 90 100 110 VIH Input High Voltage (IN, /IN) 1.2 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH–0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 1a. Note 5. 0.1 VCC V VDIFF_IN Differential Input Voltage Swing |IN-/IN| See Figure 1b. 0.2 VIN_FSI Input Voltage Threshold that Triggers FSI VT_IN IN-to-VT (IN, /IN) VREF-AC Output Reference Voltage 2.375 No load, max VCC V 30 VCC–1.3 VCC–1.2 100 mV 1.28 V VCC–1.1 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIN(max) is specified when VT is floating. February 2005 5 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U LVDS Outputs DC Electrical Characteristics(7) VCC = 2.5V ±5%; RL = 100 across output pair or equivalent; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOCM Output Common Mode Voltage 1.125 1.275 V VOCM Change in Common Mode Voltage –50 +50 mV VOUT Output Voltage Swing See Figure 1a. 250 350 mV VDIFF-OUT Differential Output Voltage Swing See Figure 1b. 500 700 mV Min Typ LVTTL/CMOS DC Electrical Characteristics(7) VCC = 2.5V ±5%; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage Condition VIL Input LOW Voltage IIH Input HIGH Current -125 IIL Input LOW Current -300 Max 2.0 Units V 0.8 V 30 µA µA Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2005 6 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U AC Electrical Characteristics(8) VCC = 2.5V ±5%; RL = 100 across output pair or equivalent; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min Typ fMAX Maximum Operating Frequency Clock 1.5 2.0 tpd Differential Propagation Delay In-to-Q VIN = 100mV to 200mV(9) 470 625 870 ps In-to-Q VIN = 200mV to 800mV(9) 440 575 800 ps SEL-to-Q RPE enabled, see Timing Diagram 17 cycles SEL-to-Q RPE disabled (VIN = VCC/2) 900 ps 550 Max Units GHz tpd Tempco Differential Propagation Delay Temperature Coefficient tSKEW Part-to-Part Skew Note 10 200 ps tJitter Random Jitter Note 11 1 ps(rms) Cycle-to-Cycle Jitter Note 12 1 ps(rms) Total Jitter (TJ) Note 13 10 ps(pp) Crosstalk-Induced Jitter Note 14 0.7 ps(rms) Output Rise/Fall Time (20% to 80%) At full output swing. 150 ps tr, tf fs/oC 115 30 70 Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Propagation delay is measured with input tr, tf 300ps (20% to 80%) and VIL 800mV. 10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 11. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX. 12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 13. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 14. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. February 2005 7 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Functional Description RPE and FSI Functionality The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to “Timing Diagrams” section for detailed information. RPE MUX and Fail-Safe Input The SY89841U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits: Runt-Pulse Eliminator (RPE) Circuit The RPE MUX provides a “glitchless” switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. Case #1: Two Normal Clocks and RPE Enabled In this case, the frequency difference between the two running clocks, IN0 and IN1, must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz. If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages. Fail-Safe Input (FSI) Circuit • Stage 1: The output will continue to follow CLK1 for a limited number of pulses. • Stage 2: The output will remain LOW for a limited number of pulses of CLK2. • Stage 3: The output follows CLK2. The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum singleended input amplitude limit (VIN), or 200mV differentially (Vdiff_IN), the output will latch to the last valid clock state. Stage 1 Stage 2 Stage 3 CLK1 CLK2 SEL Select CLK2 Select CLK1 OUTPUT Runt pulse eliminated from output 3 to 5 falling edges of CLK1 4 to 5 falling edges of CLK2 Timing Diagram 1 February 2005 8 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Case #2: Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled). • Stage 1: The output will remain HIGH for a limited number of pulses of CLK2. • Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2. • Stage 3: The output will follow CLK2. If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages. Stage 1 Stage 2 Stage 3 CLK1 CLK2 Select CLK2 Select CLK1 SEL OUTPUT 14 to 16 falling edges of CLK2 Runt pulse eliminated from output Timing Diagram 2 Note: Output show extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period. Case #3: Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE enabled). • Stage 1: The output will remain LOW for a limited number of falling edges of CLK2. • Stage 2: The output will follow CLK2. If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages. Stage 1 Stage 2 CLK1 CLK2 SEL Select CLK2 Select CLK1 OUTPUT 13 to 17 falling edges of CLK2 Timing Diagram 3 February 2005 9 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Case #4: Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled). If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV (VIN) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending upon the last valid state at the CLK1 Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Operating Characteristics” for detailed information. CLK1 CLK2 SEL Select CLK2 Select CLK1 OUTPUT as in case #2 as in case #3 Timing Diagram 4 Power-On Reset (POR) Description The following formula describes this relationship: The SY89841U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between VCC and the CAP pin (pin 11) controls the delay for the power-on reset function. C(µF) ≥ As an example, if the time required for the system power supply to power up past 2.3V is 12ms, then the required capacitor value on pin 11 would be: The required capacitor value calculation is based upon the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V. February 2005 t dPS (ms) 12(ms/µF) C(µF) ≥ 12ms 12(ms/µF) C ≥ 1µF 10 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Typical Operating Characteristics VCC = 2.5, GND = 0V, VIN 400mVpk, tr/tf 300ps, RL = 100 across output pair or equivalent; TA = 25°C, unless otherwise stated. Functional Characteristics VCC = 2.5, GND = 0V, VIN 400mVpk, tr/tf 300ps, RL = 100 across output pair or equivalent; TA = 25°C, unless otherwise stated. February 2005 11 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Singled-Ended and Differential Swings VDIFF_IN, VDIFF_OUT 700mV (typical) VIN,VOUT 350mV (typical) Figure 1b. Differential Voltage Swing Figure 1a. Single-Ended Voltage Swing Input Stage VCC IN 50Ω VT 50Ω GND /IN Figure 2. Simplified Differential Input Stage February 2005 12 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U Input Interface Applications VCC VCC VCC IN GND 50Ω 0.01µF 50Ω VT GND VCC GND VT GND NC SY89841U SY89841U 19Ω VREF-AC /IN /IN SY89841U GND CML LVPECL /IN VCC IN IN LVPECL VREF-AC NC VT NC VREF-AC 0.01µF Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) VCC Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled) VCC IN IN CML LVDS /IN /IN SY89841U GND VCC VT VREF-AC SY89841U GND NC VT NC VREF-AC 0.01µF Figure 3d. CML Interface (AC-Coupled) February 2005 Figure 3e. LVDS Interface (DC-Coupled) 13 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U LVDS Output Interface Applications vOD 49.9Ω, ±1% 100Ω vOH, vOL vOH, vOL 49.9Ω, ±1% GND vOCM, ∆vOCM GND Figure 4a. LVDS Differential Measurement Figure 4b. LVDS Common Mode Measurement Related Product and Support Documentation Part Number Function Data Sheet Link SY89840U Precision LVPECL Runt Pulse Eliminator 2:1 Multiplexer www.micrel.com/product-info/products/sy89840u.shtml. SY89842U Precision CML Runt Pulse Eliminator 2:1 Multiplexer www.micrel.com/product-info/products/sy89842u.shtml. MLFTM Application Note www.amkor.com/products/notes_papers/MLFAppNote.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml HBW Solutions February 2005 14 M9999-021405 [email protected] or (408) 955-1690 Micrel, Inc. SY89841U 16 Lead MicroLeadFrameTM (MLF-16) Packages Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. February 2005 15 M9999-021405 [email protected] or (408) 955-1690