MC74F269 8-BIT BIDIRECTIONAL BINARY COUNTER The MC74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. • Synchronous Counting and Loading • Built-In Lookahead Carry Capability • Count Frequency 115 MHz Typical • Supply Current 95 mA Typical 8-BIT BIDIRECTIONAL BINARY COUNTER FAST SCHOTTKY TTL PIN ASSIGNMENT PE P0 P1 P2 P3 VCC P4 P5 P6 P7 TC CET 24 23 22 21 20 19 18 17 16 15 14 13 24 J SUFFIX CERAMIC CASE 758-01 1 1 U/D 2 Q0 3 Q1 4 Q2 5 Q3 8 6 7 Q4 GND Q5 9 Q6 10 Q7 11 12 CP CEP N SUFFIX PLASTIC CASE 724-03 24 1 DW SUFFIX SOIC CASE 751E-03 24 1 ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current High 74 –1.0 mA IOL Output Current Low 74 20 mA FAST AND LS TTL DATA 4-138 MC74F269 FUNCTION TABLE Inputs Operating Mode Outputs CP U/D CEP CET PE Pn Qn TC Parallel Load ↑ ↑ X X X X X X l l l h L H (a) (a) Count Up ↑ h l l h X Count Up (a) Count Down ↑ l l l h X Count Down (a) Hold Do Nothing ↑ ↑ X X h X X h h h X X qn qn (a) H H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don’t care q = Lower case letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition ↑ = LOW-to-HIGH clock transition (a) = The TC is LOW when CET is LOW and the counter is at Terminal Count. Terminal Count Up is with all Qn outputs HIGH and Terminal Count Down is with all (a) = Qn outputs LOW. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol Min Parameter Typ Max Unit Test Conditions 2.5 VOH Output HIGH Voltage VOL Output LOW Voltage VIK Input Clamp Diode Voltage 74 V 2.7 74 3.4 0.35 Input HIGH Current IIL Input LOW Current IOS Output Short Circuit Current (Note 2) ICC Total Supply Current (total) VCC = 4.75 V V IOL = 20 mA, VCC = 4.5 V –1.2 V VCC = MIN, IIN = –18 mA µA VCC = MAX – 0.6 mA VCC = MAX, VIN = 0.5 V –150 mA VCC = MAX, VOUT = 0 V mA VCC = MAX 20 – 60 VCC = 4.5 V 0.5 100 IIH IOH = –1.0 mA ICCH 93 120 ICCL 98 125 VIN = 7.0 V VIN = 2.7 V (Note 3) (Note 4) NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. 3. PE = CET = CEP = U/D = GND: Pn = 4.5 V: CP = ↑ 4. PE = CET = CEP = U/D = GND: CP = ↑ FAST AND LS TTL DATA 4-139 MC74F269 LOGIC DIAGRAM DETAIL A Pn DATA PE D Q CP Q P0 DETAIL A Q0 P1 DETAIL A Q1 P2 DETAIL A Q2 P3 DETAIL A Q3 P4 DETAIL A Q4 P5 DETAIL A Q5 P6 DETAIL A Q6 P7 DETAIL A Q7 CLOCK CE CP U/D CEP CET TC FAST AND LS TTL DATA 4-140 MC74F269 AC ELECTRICAL CHARACTERISTICS Symbol 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF Min Parameter Typ Max Min Max 85 Unit fMAX Maximum Clock Frequency 100 MHz tPLH tPHL Propagation Delay CP to Qn (Load) PE = LOW 3.0 4.0 5.5 5.0 9.0 9.0 3.0 4.0 9.5 9.5 ns tPLH tPHL Propagation Delay CP to Qn (Count) PE = HIGH 3.0 4.5 6.0 7.0 9.0 10 2.5 4.5 10 10.5 ns tPLH tPHL Propagation Delay CP to TC 4.5 5.0 7.5 7.5 10 10 4.5 5.0 10.5 11 ns tPLH tPHL Propagation Delay CET to TC 3.5 3.5 5.0 5.5 9.0 9.0 3.5 3.5 10 10 ns tPLH tPHL Propagation Delay U/D to TC 4.0 4.5 6.0 5.5 9.0 9.5 4.0 4.5 10 10 ns AC SETUP REQUIREMENTS Parameter Min Symbol 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF Typ Max Min Typ Max Unit ts(H) ts(L) Set-up Time, HIGH or LOW P to CP 2.0 2.0 2.5 2.5 ns th(H) th(L) Hold Time, HIGH or LOW P to CP 1.0 1.0 1.0 1.0 ns ts(H) ts(L) Set-up Time, HIGH or LOW PE to CP 5.0 5.5 5.5 6.5 ns th(H) th(L) Hold Time, HIGH or LOW PE to CP 0 0 0 0 ns ts(H) ts(L) Set-up Time, HIGH or LOW CET, CEP to CP 4.5 4.5 5.5 5.5 ns th(H) th(L) Hold Time, HIGH or LOW CET, CEP to CP 0 0 0 0 ns ts(H) ts(L) Set-up Time, HIGH or LOW U/D to CP 6.0 7.0 7.0 8.0 ns th(H) th(L) Hold Time, HIGH or LOW U/D to CP 0 0 0 0 ns tw(H) tw(L) Clock Pulse Width CP 4.0 4.5 4.0 5.0 ns FAST AND LS TTL DATA 4-141 MC74F269 TIMING DIAGRAM PE P0 P1 P2 P3 P4 P5 P6 P7 CP U/D CEP AND CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC 253 LOAD 254 255 0 1 COUNT UP 2 INHIBIT FAST AND LS TTL DATA 4-142 2 1 0 255 COUNT DOWN 254 253