For:laurie Printed on:Sat, Aug 13, 1994 11:15:02 From book:mc54f Document:mc74f299rev5 Last saved on:Fri, Aug 12, 1994 13:38:16 MC74F299 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS The MC74F299 is an 8-Bit Universal Shift/Storage Register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. FAST SCHOTTKY TTL • Common I/O for Reduced Pin Count • Four Operation Modes: Shift left, Shift Right, Load and Store • Separate Shift Right Serial Input and Shift Left Serial Input for Easy Cascading • 3-State Outputs for Bus Oriented Applications • Input Clamp Diodes Limit High-Speed Termination Effects J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 CONNECTION DIAGRAM V CC S 1 DS 7 Q 7 20 19 18 17 I/O 7 I/O 5 I/O 3 I/O 1 CP DS 0 15 14 13 12 11 16 20 1 DW SUFFIX SOIC CASE 751D-03 20 1 1 2 3 4 5 6 7 8 9 10 S 0 OE 1 OE 2 I/O 6 I/O 4 I/O 2 I/O 0 Q 0 MR GND ORDERING INFORMATION MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current — High 74 –1.0/– 3.0 mA IOL Output Current — Low 74 20/24 mA FAST AND LS TTL DATA 4-242 MC74F299 FUNCTION TABLE Inputs MR L H H H H S1 X H L H L S0 X H H L L CP Response X ↑ ↑ ↑ X Asynchronous Reset: Q0–Q7 = LOW Parallel Load: I/On º Qn Shift Right: DS0 º Q0, Q0 º Q1, etc. Shift Left: DS7 º Q7, Q7 º Q6, etc. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW-to-HIGH clock transition. FUNCTIONAL DESCRIPTION The MC74F299 is an 8-bit universal shift/storage register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-LOW Master Reset is used to reset the register. The MC74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified) Limits Symbol Parameter VIH VIL Input HIGH Voltage Input LOW Voltage VIK Input Clamp Diode Voltage Min Q0/Q7 VOH Output HIGH Voltage I/O VOL IIH Output LOW Voltage Input HIGH Current IIL Input LOW Current IOZH Off-State Output Current, High-Level Voltage Applied IOZL Off-State Output Current, Low-Level Voltage Applied IOS ICC Typ Max 2.0 74 2.5 74 2.7 74 2.7 74 2.4 Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V VCC = MIN, IIN = –18 mA VCC = 4.5 V IOH = –1.0 mA VCC = 4.75 V V 3.4 Q0/Q7 0.5 I/O 0.5 Q0/Q7 20 I/O 70 Q0/Q7 0.1 I/O 1.0 –1.2 – 0.6 – 60 Total Supply Current Test Conditions V S0, S1 Other Inputs Output Short Circuit Current (Note 2) Unit V IOH = – 3.0 mA VCC = 4.75 V VCC = 4.5 V V IOL = 20 mA IOL = 24 mA VCC = MIN µA VCC = MAX, VIN = 2.7 V mA VCC = MAX mA VCC = MAX, VIN = 0.5 V 70 µA 1.0 mA – 0.6 mA –150 mA 95 mA VCC = MAX VIN = 7.0 V VIN = 5.5 V VOUT = 2.7 V VOUT = 5.5 V VCC = MAX, VOUT = 0.5 V VCC = MAX VOUT = 0 V OE = HIGH, CP = HIGH NOTES: 1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at one time, nor for more than 1 second. FAST AND LS TTL DATA 4-243 MC74F299 AC ELECTRICAL CHARACTERISTICS Symbol 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF Min Parameter Max Min Max 70 Unit fMAX Maximum Clock Frequency 70 MHz tPLH tPHL Propagation Delay CP to Q0 or Q7 3.5 4.5 7.5 8.0 3.5 4.5 8.5 8.5 ns tPLH tPHL Propagation Delay CP to I/On 3.5 4.0 9.0 9.0 3.5 4.0 10 10 ns tPHL Propagation Delay MR to Q0 or Q7 5.5 9.5 5.5 10.5 ns tPHL Propagation Delay MR to I/On 5.5 10 5.5 10.5 ns tPZH tPZL Output Enable Time to HIGH or LOW Level 3.5 4.0 8.0 10 3.5 4.0 9.0 11 ns tPHZ tPLZ Output Disable Time to HIGH or LOW Level 2.0 1.0 7.0 5.5 2.0 1.0 8.0 6.5 ns AC SETUP REQUIREMENTS Parameter Min Symbol ts(H) ts(L) Set-Up Time, HIGH or LOW S0 or S1 to CP th(H) th(L) Hold Time, HIGH or LOW S0 or S1 to CP ts(H) ts(L) 74F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF Typ Max Min Max Unit 6.5 6.5 7.5 7.5 ns 0 0 0 0 ns Set-Up Time, HIGH or LOW I/On, DS0, DS7 to CP 3.5 3.5 4.0 4.0 ns th(H) th(L) Hold Time, HIGH or LOW I/On, DS0, DS7 to CP 0 1.0 0 1.0 ns tw(H) tw(L) CP Pulse Width, HIGH or LOW 5.0 4.5 5.0 4.5 ns tw(L) MR Pulse Width LOW 4.5 4.5 ns trec Recovery Time MR to CP 4.0 4.0 ns FAST AND LS TTL DATA 4-244 Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) "! ! " -A11 1 10 ! " # P C -T- " #! D J F K ! #! * * !" $ !" M * R X 45° " " %# G ! " ! -B- ! " 20 & ! ! ° ° ° ° ) ) ) ! Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line "! ! $" '' " # !" " !" " %# 20 " 11 1 10 B L C F N H G D J M K Case 738-03 N Suffix 20-Pin Plastic ! ! ° ° ° ° ! " " ! ( " " B ! ! $ ! ( ! " # ! C -T- L K G ! & 11 E ! 10 1 #! !#! "! -A20 ! $ A " " " N M F J D " " FAST AND LS TTL DATA 4-245 * !" $ !" * ! ! ! ! ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 4-246