MOTOROLA MC74HC132A

SEMICONDUCTOR TECHNICAL DATA
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High–Performance Silicon–Gate CMOS
The MC54/74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
LOGIC DIAGRAM
A1
1
3
B1
A2
PIN ASSIGNMENT
Y1
2
4
6
B2
Y2
5
Y = AB
A3
A1
1
14
VCC
B1
2
13
B4
Y1
3
12
A4
A2
4
11
Y4
B2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
9
8
B3
Y3
FUNCTION TABLE
10
Inputs
A4 12
11
B4
Y4
13
PIN 14 = VCC
PIN 7 = GND
10/95
 Motorola, Inc. 1995
Ceramic
Plastic
SOIC
1
REV 6
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
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MC54/74HC132A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
—
no
limit*
ns
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
* When Vin
Min
0.5 VCC, ICC >> quiescent current.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
25_C
– 40_C to
+ 85_C
– 55_C to
+ 125_C
Unit
VT+ max
Maximum Positive–Going
Input Threshold Voltage
(Figure 3)
Vout = 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VT+ min
Minimum Positive–Going
Input Threshold Voltage
(Figure 3)
Vout = 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
V
VT– max
Maximum Negative–Going
Input Threshold Voltage
(Figure 3)
Vout = VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
V
VT– min
Minimum Negative–Going
Input Threshold Voltage
(Figure 3)
Vout = VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VHmax
Note 2
Maximum Hysteresis Voltage
(Figure 3)
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
V
VHmin
Note 2
Minimum Hysteresis Voltage
(Figure 3)
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
V
NOTE: 1. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) + (VT– min).
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC132A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOH
– 55 to
25_C
85_C
125_C
Vin VT– min or VT+ max
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Vin –VT– min or VT+ max
|Iout|
4.0 mA
|Iout|
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Test Conditions
Minimum High–Level Output
Voltage
VOL
VCC
V
Parameter
Vin ≥VT+ max
|Iout|
20 µA
Maximum Low–Level Output
Voltage
Vin≥VT+ max
Iin
ICC
|Iout|
|Iout|
4.0 mA
5.2 mA
Unit
V
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
1.0
10
40
µA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
pF
24
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
tr
tf
TEST POINT
VCC
90%
50%
10%
INPUT
A OR B
tPHL
90%
50%
10%
Y
OUTPUT
GND
DEVICE
UNDER
TEST
tPLH
tTHL
CL*
tTLH
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms
High–Speed CMOS Logic Data
DL129 — Rev 6
Figure 2. Test Circuit
3
MOTOROLA
VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)
MC54/74HC132A
4
3
VHtyp
2
1
2
3
4
5
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT + typ) – (VT – typ)
6
Figure 3. Typical Input Threshold, VT+, VT–
Versus Power Supply Voltage
VCC
Vout
Vin
(a) A SCHMITT TRIGGER SQUARES UP INPUTS
(a) WITH SLOW RISE AND FALL TIMES
(b) A SCHMITT TRIGGER OFFERS MAXIMUM NOISE
(b) IMMUNITY
VCC
VCC
VH
VH
Vin
VT +
VT –
Vin
VT +
VT –
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
Figure 4. Typical Schmitt–Trigger Applications
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC132A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
-A14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-B-
C
-T-
L
DIM
A
B
C
D
F
G
J
K
L
M
N
K
SEATING
PLANE
F
G
D 14 PL
0.25 (0.010)
M
N
T A
M
J 14 PL
0.25 (0.010)
S
M
T
B
S
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
B
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
P 7 PL
0.25 (0.010)
7
G
D
0.25 (0.010)
High–Speed CMOS Logic Data
DL129 — Rev 6
M
T
F
J
M
K
14 PL
B
S
M
R X 45°
C
SEATING
PLANE
B
M
A
S
5
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
MILLIMETERS
MIN
MAX
19.05 19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0°
15°
0.51
1.01
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
1
INCHES
MIN
MAX
0.750 0.785
0.245 0.280
0.155 0.200
0.015 0.020
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
0°
15°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
MOTOROLA
MC54/74HC132A
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA
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*MC54/74HC132A/D*
MC54/74HC132A/D
High–Speed CMOS Logic Data
DL129 — Rev 6