74FST3253 Dual 4:1 Multiplexer/ Demultiplexer Bus Switch The ON Semiconductor 74FST3253 is a dual 4:1, high performance multiplexer/demultiplexer bus switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. http://onsemi.com MARKING DIAGRAMS Features • • • • • • • • RON t 4 W Typical Less Than 0.25 ns−Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin−For−Pin Compatible With QS3253, FST3253, CBT3253 Popular Packages: TSSOP−16, SOIC−16 All Devices in Package TSSOP are Inherently Pb−Free* OE1 S1 1B4 1B3 1B2 1B1 1A GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 16 1 SOIC−16 D SUFFIX CASE 751B 16 A L, WL Y W, WW Pin OE1, OE2 X X L L H H X X L H L H H X L L L L X H L L L L 1 Assembly Location Wafer Lot Year Work Week Function Disconnect 1A Disconnect 2A A = B1 A = B2 A = B3 A = B4 Description Bus Switch Enables Select Inputs S0, S1 S0 OE1 OE2 = = = = FST 3253 ALYW PIN NAMES Figure 1. 16−Lead Pinout S1 1 16 1 TSSOP−16 DT SUFFIX CASE 948F VCC OE2 S0 2B4 2B3 2B2 2B1 2A FST3253 AWLYWW A Bus A B1, B2, B3, B4 Bus B ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Figure 2. Truth Table *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 4 1 Publication Order Number: 74FST3253/D 74FST3253 1A 1B1 1B2 1B3 1B4 2B1 2A 2B2 2B3 2B4 FLOW CONTROL OE1 OE2 S0 S1 Figure 3. Logic Diagram ORDERING INFORMATION Package Shipping † 74FST3253D SOIC−16 48 Units / Rail 74FST3253DR2 SOIC−16 2500 Units / Tape & Reel 74FST3253DT TSSOP−16* (Pb−Free) 96 Units / Rail 74FST3253DTR2 TSSOP−16* (Pb−Free) 2500 Units / Tape & Reel Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 74FST3253 MAXIMUM RATINGS Symbol Value Unit DC Supply Voltage *0.5 to )7.0 V VI DC Input Voltage *0.5 to )7.0 V VO DC Output Voltage *0.5 to )7.0 V VI t GND *50 mA VO t GND *50 mA 128 mA VCC Parameter IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Sink Current ICC DC Supply Current per Supply Pin $100 mA IGND DC Ground Current per Ground Pin $100 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup SOIC TSSOP _C _C 125 170 _C/W Level 1 Oxygen Index: 28 to 34 ESD Withstand Voltage Latchup Performance 260 )150 UL 94 V−0 @ 0.125 in Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) u2000 u200 N/A V Above VCC and Below GND at 85_C (Note 4) $500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate Switch I/O Min Max Unit 4.0 5.5 V (Note ) 0 5.5 V (HIGH or LOW State) 0 5.5 V *40 )85 _C DC 5 ns/V 0 Operating, Data Retention Only Switch Control Input VCC = 5.0 V $ 0.5 V 5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. http://onsemi.com 3 74FST3253 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIK Clamp Diode Resistance VIH High−Level Input Voltage VIL Low−Level Input Voltage Conditions IIN = *18mA VCC TA = *40_C to )85_C (V) Min Typ* 4.5 4.0 to 5.5 Max Unit *1.2 V 2.0 V 4.0 to 5.5 0.8 V Input Leakage Current 0 v VIN v 5.5 V 5.5 $1.0 mA IOZ OFF−STATE Leakage Current 0 v A, B v VCC 5.5 $1.0 mA RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 W VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 II VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 mA DICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25_C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. AC ELECTRICAL CHARACTERISTICS TA = *40_C to )85_C CL = 50 pF, RU = RD = 500 W VCC = 4.5−5.5 V Symbol tPHL, tPLH Parameter Prop Delay Bus to Bus (Note 7) Conditions Min Prop Delay, Select to Bus A tPZH, tPZL tPHZ, tPLZ Max Unit 0.25 0.25 ns 1.0 5.3 6.3 VI = OPEN Max VCC = 4.0 V Min Output Enable Time, Select to Bus B VI = 7 V for tPZL 1.0 5.3 6.0 Output Enable Time, IOE to Bus A, B VI = OPEN for tPZH 1.0 5.3 6.2 Output Disable Time, Select to Bus B VI = 7 V for tPLZ 1.0 5.8 6.2 Output Disable Time, IOE to Bus A, B VI = OPEN for tPHZ 1.0 5.5 6.2 ns ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF CI/O A Port Input/Output Capacitance VCC, OE = 5.0 V 13 pF CI/O B Port Input/Output Capacitance VCC, OE = 5.0 V 5 pF 8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested. http://onsemi.com 4 74FST3253 AC Loading and Waveforms VI 500 W FROM OUTPUT UNDER TEST CL* 500 W NOTES: 1. Input driven by 50 W source terminated in 50 W. 2. CL includes load and stray capacitance. *CL = 50 pF Figure 4. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 90 % 1.5 V 3.0 V 1.5 V 10 % 10 % tPLH GND tPLH VOH 1.5 V OUTPUT 1.5 V VOL Figure 5. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % tPZL OUTPUT 3.0 V GND tPZL 1.5 V tPZH VOL + 0.3 V VOL tPHZL VOH 1.5 V OUTPUT Figure 6. Enable/Disable Delays http://onsemi.com 5 VOH − 0.3 V 74FST3253 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 6 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 74FST3253 PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S ÇÇÇ ÉÉ ÇÇÇ ÉÉ ÇÇÇ K K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E H ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 74FST3253/D