74FST3345 8−Bit Bus Switch The ON Semiconductor 74FST3345 is an 8−bit, high performance switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. The device consists of an 8−bit switch with two Output/Enable pins (OE and OE). MARKING DIAGRAMS 20 Features • • • • • • • • http://onsemi.com RON 4 Typical Less Than 0.25 ns−Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin−For−Pin Compatible with QS3345, FST3345, CBT3345 All Popular Packages: QSOP−20, TSSOP−20, SOIC−20 All Devices in Package TSSOP are Inherently Pb−Free* 1 2 3 4 5 6 7 8 9 10 OE A0 A1 A2 A3 A4 A5 A6 A7 GND 20 19 18 17 16 15 14 13 12 11 2 1 20 20 20 20 11 FST3345 AWLYWW 1 QSOP−20 QS SUFFIX CASE 492A B0 A L, WL Y W, WW 1 = = = = Assembly Location Wafer Lot Year Work Week B7 PIN NAMES Pin 19 OE FST 3345 ALYW 1 1 OE FST3345 AWLYYWW TSSOP−20 DT SUFFIX CASE 948E 18 9 A7 1 SOIC−20 DW SUFFIX CASE 751D 1 VCC OE B0 B1 B2 B3 B4 B5 B6 B7 Figure 1. 20−Lead Pinout A0 20 OE1, OE2 Figure 2. Logic Diagram TRUTH TABLE Inputs Description Bus Switch Enables 1A, 2A Bus A 1B, 2B Bus B Function ORDERING INFORMATION OE OE X L Connect H X Connect L H Disconnect See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 January, 2005 − Rev. 1 1 Publication Order Number: 74FST3345/D 74FST3345 MAXIMUM RATINGS Symbol Value Unit DC Supply Voltage 0.5 to 7.0 V VI DC Input Voltage 0.5 to 7.0 V VO DC Output Voltage 0.5 to 7.0 V VI GND 50 mA VO GND 50 mA 128 mA VCC Parameter IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Sink Current ICC DC Supply Current per Supply Pin 100 mA IGND DC Ground Current per Ground Pin 100 mA TSTG Storage Temperature Range 65 to 150 C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias JA Thermal Resistance (Note 1) MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup SOIC TSSOP QSOP C C 96 128 200 C/W Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) 2000 200 V Above VCC and Below GND at 85C (Note 4) 500 mA ESD Withstand Voltage Latchup Performance 260 150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free−Air Temperature t/V Input Transition Rise or Fall Rate Min Max Unit 4.0 5.5 V (Note ) 0 5.5 V (HIGH or LOW State) 0 VCC V 40 85 C 0 0 5 DC ns/V Operating, Data Retention Only Switch Control Input Switch I/O 5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. http://onsemi.com 2 74FST3345 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIK Clamp Diode Resistance VIH High−Level Input Voltage VIL Low−Level Input Voltage Conditions IIN = 18mA VCC TA = 40C to 85C (V) Min Typ* 4.5 4.0 to 5.5 Max Unit 1.2 V 2.0 V 4.0 to 5.5 0.8 V Input Leakage Current 0 VIN 5.5 V 5.5 1.0 A IOZ OFF−STATE Leakage Current 0 A, B VCC 5.5 1.0 A RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 II VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 A ICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. AC ELECTRICAL CHARACTERISTICS Limits TA = 40C to 85C VCC = 4.5 to 5.5 V Symbol Parameter Conditions Figures Min Max VCC = 4.0 V Min Max Unit 0.25 0.25 ns tPHL, tPLH Prop Delay Bus to Bus (Note 7) VI = OPEN 3 and 4 tPZH, tPZL Output Enable Time VI = 7 V for tPZL VI = OPEN for tPZH 3 and 4 1.5 6.5 7.0 ns tPHZ, tPLZ Output Disable Time VI = 7 V for tPLZ VI = OPEN for tPHZ 3 and 4 1.0 8.0 8.2 ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF CI/O Input/Output Capacitance VCC, OE = 5.0 V 5 pF 8. TA = 25C, f = 1 MHz, Capacitance is characterized but not tested. ORDERING INFORMATION mber Device Order N Number Package Shipping† 74FST3345DW SOIC−20 38 Units / Rail 74FST3345DWR2 SOIC−20 1000 Units / Tape & Reel 74FST3345DT TSSOP−20* (Pb−Free) 75 Units / Rail 74FST3345DTR2 TSSOP−20* (Pb−Free) 2500 Units / Tape & Reel 74FST3345QS QSOP−20 55 Units / Rail 74FST3345QSR QSOP−20 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 3 74FST3345 AC Loading and Waveforms VI 500 FROM OUTPUT UNDER TEST CL * 500 NOTES: 1. Input driven by 50 source terminated in 50 . 2. CL includes load and stray capacitance. *CL = 50 pF Figure 3. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 3.0 V 90 % 1.5 V 1.5 V 10 % 10 % tPLH GND tPLH VOH 1.5 V 1.5 V OUTPUT VOL Figure 4. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % tPZL OUTPUT 3.0 V GND tPZL 1.5 V tPZH VOL + 0.3 V VOL tPHZL VOH 1.5 V OUTPUT Figure 5. Enable/Disable Delays http://onsemi.com 4 VOH − 0.3 V 74FST3345 PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 h 1 10 20X DIM A A1 B C D E e H h L B B 0.25 M T A B S S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. A B M D e 18X MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 SEATING PLANE A1 C T TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 J J1 B L −U− PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 5 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 −−− 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 −−− 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 74FST3345 PACKAGE DIMENSIONS QSOP−20 QS SUFFIX CASE 492A−01 ISSUE O −A− Q R H x 45 U 0.25 (0.010) RAD. 0.005−0.010 TYP G P L MOLD PIN MARK RAD. 0.013 X 0.005 DP. MAX −B− DETAIL E T M V N 8 PL J K M −T− C 20 PL D 0.25 (0.010) SEATING PLANE M T B S A F S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MAX MIN A 0.337 0.344 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0 8 N 0 7 P 0.052 0.062 Q 0.035 DIA R 0.035 0.045 U 0.035 0.045 V 0 8 MILLIMETERS MAX MIN 8.56 8.74 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0 8 0 7 1.32 1.58 0.89 DIA 0.89 1.14 0.89 1.14 0 8 DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 6 For additional information, please contact your local Sales Representative. 74FST3345/D