ECLTSSOP20EVB Evaluation Board Manual for High Frequency TSSOP20 http://onsemi.com EVALUATION BOARD MANUAL INTRODUCTION ON Semiconductor has developed an evaluation board for the devices in 20-lead TSSOP package. These evaluation boards are offered as a convenience for the customers interested in performing their own engineering assessment on the general performance of the 20-lead TSSOP device samples. The board provides a high bandwidth 50 controlled impedance environment. Figures 1 and 2 show the top and bottom view of the evaluation board, which can be configured in several different ways, depending on device under test (see Table 1. Configuration List). This evaluation board manual contains: • • • • This manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation. Board Lay-Up The 20-lead TSSOP evaluation board is implemented in four layers with split (dual) power supplies (see Figure 3. Evaluation Board Lay-Up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008″ thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is the power plane (VCC & VEE) and a portion of this layer is a ground plane. The fourth layer is the secondary trace layer. Information on 20-lead TSSOP Evaluation Board Assembly Instructions Appropriate Lab Setup Bill of Materials Figure 1. Top View of the 20-lead TSSOP Evaluation Board Semiconductor Components Industries, LLC, 2003 May, 2003 - Rev. 1 1 Publication Order Number: ECLTSSOP20EVB/D ECLTSSOP20EVB Bottom View Expanded Bottom View Figure 2. Bottom View of the 20-lead TSSOP Evaluation Board LAY-UP DETAIL 4 LAYER SILKSCREEN (TOP SIDE) LAYER 1 (TOP SIDE) 1 OZ ROGERS 4003 0.008 in LAYER 2 (GROUND PLANE P1) 1 OZ FR-4 0.020 in LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ FR-4 0.025 in LAYER 4 (BOTTOM SIDE) 1 OZ 0.062 0.007 Figure 3. Evaluation Board Lay-up Board Layout board. Lists of components and simple schematics are located in Figures 6 through 12. Place SMA connectors on J1 through J20, 50 chip resistors between ground pad and Pin 1 pad through Pin 20 pad, and chip capacitors C1 through C5 according to configuration figures. (C4 and C5 are 0.01 F and C1, C2, and C3 are 0.1F); (See Figure 5). The 20-lead TSSOP evaluation board was designed to be versatile and accommodate several different configurations. The input, output, and power pin layout of the evaluation board is shown in Figures 4 and 5. The evaluation board has at least eight possible configurable options. Table 1, list the devices and the relevant configuration that utilizes this PCB http://onsemi.com 2 ECLTSSOP20EVB Top View Bottom View Figure 4. Evaluation Board Layout http://onsemi.com 3 ECLTSSOP20EVB VEE VCC Pin 20 Pin 1 Ground Pin 19 Pin 2 Pin 18 Pin 3 Pin 17 Pin 4 Pin 16 Pin 5 Pin 15 Pin 6 Pin 14 Pin 7 Pin 13 Pin 8 Pin 12 Pin 9 Pin 10 Pin 11 C5 C4 Figure 5. Enlarged Bottom View of the Evaluation Board Table 1. Configuration List Configuration Comments 1 See Figure 6 EP14, LVEP14 2 See Figure 7 EP17, LVEP17 3 See Figure 8 EP29 4 See Figure 9 EP40 5 See Figure 10 EP56, LVEP56 6 See Figure 11 EP57 7 See Figure 12 EP139 http://onsemi.com 4 Device ECLTSSOP20EVB It is recommended to solder 0.01 F capacitors to C4 and C5 to reduce the unwanted noise from the power supplies. C1, C2, and C3 pads are provided for 0.1 F capacitor to further diminish the noise from the power supplies. Adding capacitors can improve edge rates, reduce overshoot and undershoot. Evaluation Board Assembly Instructions The 20-lead TSSOP evaluation board is designed for characterizing devices in a 50 laboratory environment using high bandwidth equipment. Each signal trace on the board has a via, which has an option of placing a termination resistor depending on the input/output configuration (see Table 1, Configuration List). Table 11 contains the Bill of Materials for this evaluation board. Termination All ECL outputs need to be terminated to VTT (VTT = VCC –2.0 V = GND) via a 50 resistor. 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver (More information on termination is provided in AN8020). Solder the chip resistors to the bottom side of the board between the appropriate input of the device pin pads and the ground pads. For ease of assembly, it is advised to place and solder termination resistors on its vertical (side) position, instead of its original or flat position. Solder the Device on the Evaluation Board The soldering can be accomplished by hand soldering or soldering re-flow techniques. Make sure pin 1 of the device is located next to the white dotted mark and all the pins are aligned to the footprint pads. Solder the 20-lead TSSOP device to the evaluation board. Connecting Power and Ground Planes For standard ECL lab setup and test, a split (dual) power supply is required enabling the 50 internal impedance in the oscilloscope to be used as a termination of the ECL signals (VTT = VCC – 2.0 V, in split power supply setup, VTT is the system ground, VCC is 2.0 V, and VEE is –3.0 V or –1.3 V; see Table 2, Power Supply Levels). Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given configuration. Each input and output requires one SMA connector. Attach all the required SMA connectors onto the board and solder the connectors to the board on J1 through J20. Please note that alignment of the signal connector pin of the SMA can influence the lab results. The reflection and launch of the signals are largely influenced by imperfect alignment and soldering of the SMA connector. Table 2. Power Supply Levels Power Supply VCC VEE GND 5.0 V 2.0 V -3.0 V 0.0 V 3.3 V 2.0 V -1.3 V 0.0 V 2.5 V 2.0 V -0.5 V 0.0 V Validating the Assembled Board After assembling the evaluation board, it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process. Time Domain Reflectometry (TDR) is another highly recommended validation test. Connect three banana jack sockets to VCC, VEE, and GND labeled holes. Wire bond the appropriate device pin pad on the bottom side of the board to VCC and VEE power stripes. (Device specific, please see configuration for each desired device. See Figure 5) http://onsemi.com 5 ECLTSSOP20EVB CONFIGURATIONS SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J1 J2 J3 J19 J17 J4 BANANA JACK PLUG J5 J16 J6 J7 J14 J8 J13 J12 J9 J10 NORMAL TOP VIEW EP14 / LVEP14 0603 CHIP CAPACITOR 0.01 F PIN 1 VEE VCC WIRE 0402 CHIP RESISTOR 50 0805 CHIP CAPACITOR 0.01 F EXPANDED BOTTOM VIEW EP14 / LVEP14 Figure 6. Configuration 1 Table 3. Configuration 1 (Device EP14 and LVEP14) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes No Yes No Resistor No No No No No No No No No No No Yes Yes Yes No Yes Yes No Yes No Power No No No No No No No No No No VEE No No No No No No VCC No VCC http://onsemi.com 6 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J2 J3 J19 J18 J17 J4 BANANA JACK PLUG J5 J16 J6 J15 J7 J14 J8 J13 J12 J9 NORMAL TOP VIEW EP17 / LVEP17 0603 CHIP CAPACITOR 0.01 F PIN 1 VEE VCC 0402 CHIP RESISTOR 50 WIRE 0805 CHIP CAPACITOR 0.01 F EXPANDED BOTTOM VIEW EP17 / LVEP17 Figure 7. Configuration 2 Table 4. Configuration 2 (Device EP17 and LVEP17) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No Power VCC No No No No No No No No No VEE No No No No No No No No VCC http://onsemi.com 7 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J1 J2 J3 J19 J18 J17 J4 BANANA JACK PLUG J5 J16 J6 J15 J7 J14 J8 J13 J12 J9 NORMAL TOP VIEW EP29 0603 CHIP CAPACITOR 0.01 F PIN 1 VEE VCC 0402 CHIP RESISTOR 50 WIRE 0805 CHIP CAPACITOR 0.01 F EXPANDED BOTTOM VIEW EP29 Figure 8. Configuration 3 Table 5. Configuration 3 (Device EP29) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes No Resistor Yes No Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No No No No Yes Yes No Power No No No No No No No No No VCC VEE No No No No No No No No VCC http://onsemi.com 8 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J2 J3 J19 J17 J4 BANANA JACK PLUG J5 J16 J6 J15 J7 J14 J8 J9 J10 0603 CHIP CAPACITOR 0.01 F PIN 1 0603 CHIP CAPACITOR 0.01 F NORMAL TOP VIEW EP40 VEE VEE VCC VCC WIRE PIN 1 0402 CHIP RESISTOR 50 WIRE 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW EP40 0.01 F (Option 1 Internal Termination Resistor) 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW EP40 0.01 F (Option 2 External Termination Resistor) Figure 9. Configuration 4 Table 6. Configuration 4 (Device EP40) (Options 1 & 2) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Option 1 Internal Termination Resistor Configuration Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes No Yes No Resistor No No No No No No No No No No No No No No No No No No No No Power VEE Gnd Gnd No No No No Gnd Gnd No VEE No VCC No No No No VCC No VCC No No No Yes Yes Yes Yes No Yes No Option 2 External Termination Resistor Configuration Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes Resistor No No No Yes Yes Yes Yes No No No No No No No No No No No No No Power VEE No No No No No No No No No VEE No VCC No No No No VCC No VCC http://onsemi.com 9 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J1 J2 J19 J18 J17 J4 BANANA JACK PLUG J5 J16 J6 J15 J7 J13 J12 J9 J10 NORMAL TOP VIEW EP56 / LVEP56 PIN 1 VEE VCC 0603 CHIP CAPACITOR 0.01 F 0402 CHIP RESISTOR 50 WIRE 0805 CHIP CAPACITOR 0.01 F EXPANDED BOTTOM VIEW EP56 / LVEP56 Figure 10. Configuration 5 Table 7. Configuration 5 (Device EP56 and LVEP56) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes No Resistor Yes Yes No Yes Yes Yes Yes No Yes Yes No No No No Yes Yes Yes No No No Power No No No No No No No No No No VEE No No VCC No No No No No VCC http://onsemi.com 10 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J2 J3 J19 J18 J4 BANANA JACK PLUG J5 J16 J6 J15 J7 J8 J13 J12 J9 NORMAL TOP VIEW EP57 PIN 1 VEE VCC 0603 CHIP CAPACITOR 0.01 F 0402 CHIP RESISTOR 50 WIRE 0805 CHIP CAPACITOR 0.01 F EXPANDED BOTTOM VIEW EP57 Figure 11. Configuration 6 Table 8. Configuration 6 (Device EP57) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector No Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No Yes Yes No Yes Yes No Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes No Power VCC No No No No No No No No VEE VEE No No VCC No No VCC No No VCC http://onsemi.com 11 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP CAPACITOR 0.1 F J2 J3 J19 J18 J17 J4 BANANA JACK PLUG J5 J16 J6 J15 J7 J14 J13 J12 J9 J10 NORMAL TOP VIEW EP139 0603 CHIP CAPACITOR 0.01 F PIN 1 VEE VCC WIRE 0402 CHIP RESISTOR 50 0805 CHIP CAPACITOR 0.01 F EXPANDED BOTTOM VIEW EP139 Figure 12. Configuration 7 Table 9. Configuration 7 (Device EP139) Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 No Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No Resistor No Yes Yes Yes Yes No Yes No Yes Yes No No No No No No No No No No Power VCC No No No No No No VCC No No VEE No No No No No No No No VCC Connector http://onsemi.com 12 ECLTSSOP20EVB LAB SETUP Power Supply VCC GND VEE Test Measuring Equipment Differential Signal Generator Channel 1 J1 J2 Channel 2 Channel 3 J3 Channel 4 J4 Channel 5 J5 Channel 6 Channel 7 D U T J13 Out1 J12 Out1 J6 J7 J8 Channel 8 Trigger Trigger Figure 13. Example of Standard Lab Setup (Configuration 1) 2. Connect a signal generator to the input SMA connectors. Setup input signal according to the device data sheet. 3. Connect a test measurement device on the device output SMA connectors. NOTE: The test measurement device must contain 50 termination. 1. Connect appropriate power supplies to VCC, VEE, and GND. For standard ECL lab setup and test, a split (dual) power supply is required enabling the 50 internal impedance in the oscilloscope to be used as a termination of the ECL signals (VTT = VCC – 2.0 V, in split power supply setup, VTT is the system ground, VCC is 2.0 V, and VEE is –3.0 V or –1.3 V; see Table 10). Table 10. Power Supply Levels Power Supply VCC VEE GND 5.0 V 2.0 V -3.0 V 0.0 V 3.3 V 2.0 V -1.3 V 0.0 V 2.5 V 2.0 V -0.5 V 0.0 V http://onsemi.com 13 ECLTSSOP20EVB Table 11. Bill of Materials Components Manufacturer Description Part Number SMA Connector Johnson Components* SMA Connector, Side Launch, Gold Plated 142-0701-851 Banana Jack Chip Capacitor Chip Resistor Keystone* Johanson Dielectric* Panasonic* Web Site http://www.johnsoncomponents.com http://www.keyelco.com Standard Jack 6096 Miniature Jack 6090 0603 0.01 F 500R14Z100MV4E 0805 0.01 F 500R15Z100MV4E 0603 0.1 F 250R14Z101MV4E 0402 50 ± 1% Precision Think Film Chip Resistor ERJ-2RKF49R9X http://www.panasonic.com http://www.johansondielectrics.com Evaluation Board ON Semiconductor TSSOP 20 Evaluation Board ECLTSSOP20EVB http://www.onsemi.com Device Samples ON Semiconductor TSSOP 20 Package Device Various http://www.onsemi.com *Components are available through most distributors, i.e. www.newark.com, www.digikey.com. http://onsemi.com 14 ECLTSSOP20EVB Top View Second Layer (Ground Plane) Figure 14. Gerber Files http://onsemi.com 15 ECLTSSOP20EVB Third Layer (Power and Ground Plane) (Left side - VCC, Right side - VEE, Middle Box - Ground) Bottom Layer Figure 15. Gerber Files http://onsemi.com 16 ECLTSSOP20EVB Notes http://onsemi.com 17 ECLTSSOP20EVB ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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