NB4N855SMEVB
Evaluation Board User's
Manual for NB4N855S
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EVAL BOARD USER’S MANUAL
Description
Board Lay−Up
ON Semiconductor has developed an evaluation board for
the NB4N855S device as a convenience for the customers
interested in performing their own device engineering
assessment. This board provides a high bandwidth 50 W
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways.
This NB4N855S evaluation board manual contains:
• Appropriate Lab Setup
• Assembly Instructions
• Bill of Materials
This manual should be used in conjunction with the
NB4N855S device data sheet, which contains full technical
details on the device specifications and operation.
The NB4N855S evaluation board is implemented in four
layers with split (dual) power supplies (Figure 6, Evaluation
Board Lay−up). For standard lab setup, a split (dual) power
supply is essential to enable the 50 W internal impedance in
the oscilloscope as a devices termination. The first layer or
primary trace layer is 0.005″ thick Rogers RO4003 material,
which is designed to have equal electrical length on all signal
traces from the device under the test (DUT) to the sense
output. The second layer is the 1.0 oz copper ground plane.
The FR4 dielectric material is placed between second and
third layer and between third and fourth layer. The third
layer is also 1.0 oz copper ground plane. The fourth layer is
the secondary trace layer.
Top View
Bottom View
Figure 1. Top and Bottom View of the NB4N855S Evaluation Board
© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 2
1
Publication Order Number:
EVBUM2079/D
NB4N855SMEVB
Figure 2. Evaluation Board Lay−up
Connecting Power and Ground Planes
The side launch 9 pin power supply connector is wired as
shown in Figure 3. Test points can be soldered on the top of
the PCB to accommodated easier connections. Exact values
that need to be applied can be found in Table 1.
Table 1. Power Supply Levels
Power Supply Span
VCC
(Pin 10)
VEE / GND
(Pin 5)
DUT_GND
(PCB SMA Ground))
3.0 V
1.75 V
−1.25 V
0V
3.3 V
2.05 V
−1.25 V
0V
3.6 V
2.35 V
−1.25 V
0V
DUT_GND
NC
VCC
NC
VCC
VCC
VEE/GND
DUT_GND
VEE/GND
Figure 3. Power Supply Connector − 9 Pin Side
View (Left) and PCB Top View (Right)
Stimulus (Generator) Termination
bottom side of the evaluation board. Solder the chip resistors
to the bottom side of the board between the appropriate input
of the device pin pads and the ground pads as shown in
Figure 4 (for split power supply setup, PCB is assembled in
this configuration).
All ECL outputs need to be terminated to VTT (VTT = VCC
–2.0 V = GND) via a 50 W resistor. The current board design
utilizes the space for placement of the external termination
resistors. (More information on termination is provided in
AN8020). The 0402 chip resistor pads are provided on the
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NB4N855SMEVB
Figure 4. Expanded Bottom View
Likewise for CML outputs, CML stimulus signal need to
be terminated to VCC via a 50 W resistor. To accomplish this
configuration the external termination resistor has to be
moved from DUT_GND ring to VCC ring on the bottom of
the board.
For the LVDS configuration Input pin pads of the D0 or
D1 input has to be shorted using 100 W resistor across
differential lines.
oscilloscope to be used as a termination of the signals (in
split power supply setup DUT_GND is the system ground,
VCC is varied, and VEE is –1.25 V; see Table 1, Power
Supply Levels).
Board Components Configuration
The NB4N855SMEVB evaluation board requires eight
side SMA connectors. Placement locations are described in
the Table 2 below.
DUT Termination
For standard lab setup and test, a split (dual) power supply
is required enabling the 50 W internal impedance in the
Table 2. SMA Connectors and Jumpers Placement
J1/D0
J2/D0b
J3/D1
J4/D1b
J5
J6/Q1b
J7/Q1
J8/Q0
J9/Q0b
J10
1
2
3
4
5
6
7
8
9
10
Connector
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Resistor
(bottom)
0402
50 W
0402
50 W
0402
50 W
0402
50 W
0402
0.01 mF
No
No
No
No
0402
0.01 mF
No
No
No
No
to VEE/GND
No
No
No
No
to VCC
Device
Pin #
Wire
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NB4N855SMEVB
Z = 50 W
Z = 50 W
OUT1
OUT2
SIGNAL
GENERATOR
OUT3
OUT4
IN1
D0
Z = 50 W
PIN 1
D0
Q0
D1
Z = 50 W
Z = 50 W
IN2
Q0
Q1
D1
Z = 50 W
OSCILLOSCOPE
(50 W Scope Head)
Z = 50 W
IN3
Q1
Z = 50 W
IN4
Figure 5. Lab Setup
1. Connect appropriate power supplies to VCC, VEE/GND and DUT_GND (See Table 1)
2. Connect a signal generator to the input SMA connectors via matched cables. Setup input signal according to the
device data sheet.
3. Connect a test measurement device on the device output SMA connectors via matched cables.
NOTE: The test measurement device must contain 50 W termination.
SMA
10 mF
0.01 mF
VCC
Z = 50 W
D0
1
SMA
D0
10
2
Z = 50 W
SMA
Z = 50 W
9
Q0
SMA
8
Z = 50 W
7
6
Z = 50 W
Q0
NB4N855S
SMA
D1
SMA
3
4
Z = 50 W
5
SMA
D1
Q1
SMA
VEE/GND
Z = 50 W
50 W
50 W
50 W
Z = 50 W
50 W
10 mF
0.01 mF
Figure 6. Evaluation Board Schematic
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Q1
NB4N855SMEVB
Table 3. Bill of Materials
Components
Manufacturer
Description
Part Number
Qty.
Web Site
SMA
Connector
Johnson*
SMA Connector − Side
Launch
142−0701−851
8
http://www.johnsoncomponents.com
9 Pin D−Sub
Receptacle
Amphenol
Connector, Female,
9−Pin, Right Angle
788796−1
1
http://www.amphenol.com
Surface Mount
Test Points{
Keystone*
SMT Miniature Test
Point
5015
3
http://www.keyelco.com
SMT Compact Test
Point
5016
http://www.avxcorp.com
Chip
Capacitor
AVC
Corporation*
0402 0.01 mF " 10%
04025C103KAT2A
4
10 mF " 10%
T491C106K016AS
2
Chip Resistor
Panasonic*
0402 50 W " 1%
Precision Thick Film
Chip Resistor
ERJ−2RKF49R9X
4
http://www.panasonic.com
Evaluation
Board
ON
Semiconductor
Micro−10 Evaluation
Board
N/A
1
http://www.onsemi.com
Device
Samples
ON
Semiconductor
Micro−10 Package
Device
NB4N855SM
1
http://www.onsemi.com
*Components are available through most distributors, i.e. www.newark.com, www.Digikey.com
†Surface Mount Test Points can be used for power supply connection in place of power supply cable connector. See Figure 3 for test point
placement.
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5
NB4N855SMEVB
PACKAGE DIMENSIONS
Micro−10
CASE 846B−03
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−A−
−B−
K
D 8 PL
0.08 (0.003)
PIN 1 ID
G
0.038 (0.0015)
−T− SEATING
PLANE
M
T B
S
A
S
DIM
A
B
C
D
G
H
J
K
L
C
H
L
J
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.95
1.10
0.20
0.30
0.50 BSC
0.05
0.15
0.10
0.21
4.75
5.05
0.40
0.70
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.037
0.043
0.008
0.012
0.020 BSC
0.002
0.006
0.004
0.008
0.187
0.199
0.016
0.028
SOLDERING FOOTPRINT*
10X
1.04
0.041
0.32
0.0126
3.20
0.126
8X
10X
4.24
0.167
0.50
0.0196
SCALE 8:1
5.28
0.208
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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EVBUM2079/D