MC10188 Hex Buffer With Enable The MC10188 is a high–speed hex buffer with a common Enable input. When Enable is in the high state, all outputs are in the low state. When Enable is in the low state, the outputs take the same state as the inputs. • Power Dissipation = 180 mW typ/pkg (No Load) • Propagation Delay = 2.0 ns typ (B – Q) 2.5 ns typ (A – Q) http://onsemi.com MARKING DIAGRAMS LOGIC DIAGRAM 9 5 X Y 16 OUT CDIP–16 L SUFFIX CASE 620 2 3 6 1 16 4 7 PDIP–16 P SUFFIX CASE 648 13 10 MC10188L AWLYYWW MC10188P AWLYYWW 1 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 14 11 1 PLCC–20 FN SUFFIX CASE 775 15 12 10188 AWLYYWW DIP PIN ASSIGNMENT VCC1 1 16 VCC2 AOUT 2 15 FOUT BOUT 3 14 EOUT COUT 4 13 DOUT AIN 5 12 FIN BIN 6 11 EIN CIN 7 10 DIN VEE 8 9 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device COMMON Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Package Shipping MC10188L CDIP–16 25 Units / Rail MC10188P PDIP–16 25 Units / Rail MC10188FN PLCC–20 46 Units / Rail TRUTH TABLE Inputs X Y OUT L L L L H H H L L H H L Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 6 Output 1 Publication Order Number: MC10188/D MC10188 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Under Test IE 8 46 IinH 5 425 –30°C Min +25°C Max Min +85°C Max Unit 42 46 mAdc 265 265 µAdc Max Min IinH 9 290 µAdc Output Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 –1.080 Threshold Voltage Logic 0 VOLA 2 Switching Times 460 290 –0.980 –1.655 –0.910 Vdc –1.630 –1.595 (50Ω Load) Propagation Delay Rise/Fall Time Vdc ns Enable Data tPHL tPLH 2 2 1.1 1.0 3.9 3.3 1.1 1.0 3.5 2.9 1.1 1.0 3.9 3.3 (20 to 80%) tTLH tTHL 2 1.1 3.7 1.1 3.3 1.1 3.7 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test VILAmax VEE (VCC) Gnd 8 1, 16 5 5 8 1, 16 IinH 9 9 8 1, 16 5 8 1, 16 8 1, 16 8 1, 16 VOH 2 Logic 0 VOL 2 Threshold Voltage Logic 1 VOHA 2 Logic 0 VOLA 2 Rise/Fall Time VIHAmin 8 Logic 1 Propagation Delay VILmin IE Output Voltage Switching Times VIHmax IinH Output Voltage Threshold Voltage TEST VOLTAGE APPLIED TO PINS LISTED BELOW 9 5 (50Ω Load) 5 8 1, 16 Pulse In Pulse Out –3.2 V +2.0 V Enable Data tPHL tPLH 2 2 9 5 2 2 8 8 1, 16 1, 16 (20 to 80%) tTLH tTHL 2 5 2 8 1, 16 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 2 MC10188 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 G1 X V 0.010 (0.250) S T L–M S N S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S 0.007 (0.180) M T L–M H S N S Z K1 K C E F 0.007 (0.180) M T L–M S 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L–M S N S VIEW S SEATING PLANE NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 3 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– N S MC10188 –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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