MC10115 Quad Line Receiver The MC10115 is a quad differential amplifier designed for use in sensing differential signals over long lines. The base bias supply (VBB) is made available at pin 9 to make the device useful as a Schmitt trigger, or in other applications where a stable reference voltage is necessary. Active current sources provide the MC10115 with excellent common mode noise rejection. If any amplifier in a package is not used, one input of that amplifier must be connected to VBB (pin 9) to prevent upsetting the current source bias network. • PD = 110 mW typ/pkg (No Load) • tpd = 2.0 ns typ • tr, tf = 2.0 ns typ (20%–80%) http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 MC10115L AWLYYWW 1 LOGIC DIAGRAM 16 4 5 2 7 6 3 10 11 14 13 12 15 VBB* 9 PDIP–16 P SUFFIX CASE 648 MC10115P AWLYYWW 1 1 PLCC–20 FN SUFFIX CASE 775 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 A WL YY WW * VBB to be used to supply bias to the MC10115 only and bypassed (when used) with 0.01 µF to 0.1 µF capacitor to ground (0 V). VBB can source < 1.0 mA. When the input pin with the bubble goes positive, the output goes negative. DIP PIN ASSIGNMENT 10115 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Package Shipping MC10115L CDIP–16 25 Units / Rail COUT MC10115P PDIP–16 25 Units / Rail 13 DIN MC10115FN PLCC–20 46 Units / Rail 5 12 DIN BIN 6 11 CIN BIN 7 10 CIN VEE 8 9 VBB VCC1 1 16 VCC2 AOUT 2 15 DOUT BOUT 3 14 AIN 4 AIN Device Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10115/D MC10115 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Max Unit Power Supply Drain Current IE 8 29 26 29 mAdc IinH 4 150 95 95 µAdc Input Current –30°C Min +25°C Max Min +85°C Typ Max Min ICBO 4 1.0 µAdc Output Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 –1.080 Threshold Voltage Logic 0 VOLA 2 VBB 9 1.420 1.280 –1.350 –1.230 t4–2+ t4+2– 2 2 1.0 1.0 3.1 3.1 1.0 1.0 Reference Voltage 1.5 1.0 –0.980 –0.910 –1.655 Vdc –1.630 –1.595 Vdc 1.295 –1.150 Vdc 2.9 2.9 1.0 1.0 3.3 3.3 Switching Times (50Ω Load) Propagation Delay ns Rise Time (20 to 80%) t2+ 2 1.1 3.6 1.1 3.3 1.1 3.7 Fall Time (20 to 80%) t2– 2 1.1 3.6 1.1 3.3 1.1 3.7 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax –30°C –0.890 –1.890 –1.205 –1.500 +25°C –0.810 –1.850 –1.105 –1.475 +85°C –0.700 –1.825 –1.035 –1.440 Symbol Pin Under Test IE 8 IinH 4 ICBO 4 VBB VEE –5.2 From Pin 9 –5.2 –5.2 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VBB VEE (VCC) Gnd 4,7,10,13 5,6,11,12 8 1, 16 7,10,13 5,6,11,12 8 1, 16 7,10,13 5,6,11,12 8,4 1, 16 VIHmax VILmin 4 VIHAmin VILAmax Output Voltage Logic 1 VOH 2 7,10,13 4 5,6,11,12 8 1, 16 Output Voltage Logic 0 VOL 2 4 7,10,13 5,6,11,12 8 1, 16 Threshold Voltage Logic 1 VOHA 2 7,10,13 5,6,11,12 8 1, 16 Threshold Voltage Logic 0 VOLA 2 7,10,13 5,6,11,12 8 1, 16 VBB 9 5,6,11,12 8 1, 16 –3.2 V +2.0 V Reference Voltage Switching Times (50Ω Load) Propagation Delay 4 4 Pulse In Pulse Out t4–2+ t4+2– 2 2 4 4 2 2 5,6,11,12 5,6,11,12 8 8 1, 16 1, 16 Rise Time (20 to 80%) t2+ 2 4 2 5,6,11,12 8 1, 16 Fall Time (20 to 80%) t2– 2 4 2 5,6,11,12 8 1, 16 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 2 MC10115 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D –L– –M– Z W 20 D 1 X V S T L-M S N S VIEW D–D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z 0.007 (0.180) H M T L-M S N S K1 K C E F 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L-M S N S 0.007 (0.180) M T L-M S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 3 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 7.88 8.38 1.02 --- N S MC10115 –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M S T A M INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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