ONSEMI MC74LVX157MELG

MC74LVX157
Quad 2−Channel Multiplexer
With 5 V−Tolerant Inputs
The MC74LVX157 is an advanced high speed CMOS quad
2−channel multiplexer. The inputs tolerate voltages up to 7.0 V,
allowing the interface of 5.0 V systems to 3.0 V systems.
It consists of four 2−input digital multiplexers with common select
(S) and enable (E) inputs. When E is held High, selection of data is
inhibited and all the outputs go Low.
The select decoding determines whether the I0 n or I1 n inputs get
routed to the corresponding Z n outputs.
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MARKING
DIAGRAMS
16
Features
•
•
•
•
•
•
•
•
•
High Speed: tPD = 5.1 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 A (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.5 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Pb−Free Packages are Available*
SOIC−16
D SUFFIX
CASE 751B
LVX157
AWLYWW
1
16
LVX
157
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
1
16
SOEIAJ−16
M SUFFIX
CASE 966
LVX157
ALYW
1
A
WL or L
Y
WW or W
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 2
1
Publication Order Number:
MC74LVX157/D
MC74LVX157
VCC
E
I0c
I1c
Zc
I0d
I1d
Zd
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
S
I0a
I1a
Za
I0b
I1b
Zb
GND
PIN NAMES
Pins
Function
I0n
I1n
E
S
Zn
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Outputs
TRUTH TABLE
Figure 1. 16−Lead Pinout (Top View)
S
E
I0a
I1a
I0b
I1b
I0c
I1c
I0d
I1d
INPUTS
1
15
OUTPUT
E
S
I0n
I1n
Zn
H
L
L
L
L
X
H
H
L
L
X
X
X
L
H
X
L
H
X
X
L
L
H
L
H
H = High Voltage Level; L = Low Voltage Level; X = High or Low
Voltage Level ; For ICC Reasons DO NOT FLOAT Inputs
2
4
3
5
7
6
14
12
13
11
9
10
Za
Zb
Zc
Zd
Figure 2. Logic Diagram
ORDERING INFORMATION
Package
Shipping†
MC74LVX157DR2
SOIC−16
2500 Tape & Reel
MC74LVX157DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVX157DTR2
TSSOP−16*
2500 Tape & Reel
MC74LVX157M
SOEIAJ−16
50 Units / Rail
MC74LVX157MG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74LVX157MEL
SOEIAJ−16
2000 Tape & Reel
MC74LVX157MELG
SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVX157
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−40
+85
C
0
100
ns/V
TA
t/V
Operating Temperature, All Package Types
Input Rise and Fall Time
DC ELECTRICAL CHARACTERISTICS
VCC
V
TA = 25°C
TA = − 40 to 85°C
Min
Typ
Max
Min
Max
Unit
VIH
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
−
−
−
−
−
−
1.5
2.0
2.4
−
−
−
V
VIL
Low−Level Input Voltage
2.0
3.0
3.6
−
−
−
−
−
−
0.5
0.8
0.8
−
−
−
0.5
0.8
0.8
V
VOH
High−Level Output Voltage
(Vin = VIH or VIL)
IOH = −50A
IOH = −50A
IOH = −4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
−
−
−
1.9
2.9
2.48
−
−
−
V
VOL
Low−Level Output Voltage
(Vin = VIH or VIL)
IOL = 50A
IOL = 50A
IOL = 4mA
2.0
3.0
3.0
−
−
−
0.0
0.0
−
0.1
0.1
0.36
−
−
−
0.1
0.1
0.44
V
Iin
Input Leakage Current
Vin = 5.5V or GND
3.6
−
−
±0.1
−
±1.0
A
ICC
Quiescent Supply Current
Vin = VCC or GND
3.6
−
−
4.0
−
40.0
A
Symbol
Parameter
Test Conditions
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3
MC74LVX157
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Test Conditions
Propagation Delay, Input to
Output
tPLH,
tPHL
Propagation Delay, S to Zn
tPLH,
tPHL
Propagation Delay, E to Zn
tPLH,
tPHL
tOSHL
tOSLH
Output−to−Output Skew (Note 1)
TA = − 40 to 85°C
Min
Typ
Max
Min
Max
Unit
ns
VCC = 2.7V
CL = 15pF
CL = 50pF
−
−
6.6
9.1
12.5
16.0
1.0
1.0
15.5
19.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
−
−
5.1
7.6
7.9
11.4
1.0
1.0
9.5
13.0
VCC = 2.7V
CL = 15pF
CL = 50pF
−
−
8.9
11.4
16.9
20.4
1.0
1.0
20.5
24.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
−
−
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
VCC = 2.7V
CL = 15pF
CL = 50pF
−
−
9.1
11.6
17.6
21.1
1.0
1.0
20.5
24.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
−
−
7.2
9.7
11.5
15.0
1.0
1.0
13.5
17.0
VCC = 2.7V
VCC = 3.3 ±0.3V
CL = 50pF
CL = 50pF
−
−
−
−
1.5
1.5
−
−
1.5
1.5
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
Min
Parameter
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
Cin
Input Capacitance
−
4
10
−
10
pF
CPD
Power Dissipation Capacitance (Note 2)
−
20
−
−
−
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.5
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.3
−0.5
V
VIHD
Minimum High Level Dynamic Input Voltage
−
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
−
0.8
V
VCC
In or S
Zn
50%
GND
tPHL
tPLH
VCC
E
50%
GND
tPHL
50% VCC
Zn
Figure 3.
tPLH
50% VCC
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
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4
MC74LVX157
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
S
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
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5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
8
MC74LVX157
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
16
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.031
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MC74LVX157/D