bq2013H Gas Gauge IC for PowerAssist Applications Features General Description ➤ Accurate measurement of available charge in rechargeable batteries The bq2013H Gas Gauge IC is intended for battery-pack installation to maintain an accurate record of a battery’s available charge. The IC monitors a voltage drop across a sense resistor connected in series between the negative battery terminal and ground to determine charge and discharge activity of the battery. The bq2013H is designed for high cpaacity battery packs used in high-discharge rate systems. ➤ Designed for electric assist bicycles and other applications ➤ Measures a wide dynamic current range ➤ Supports NiCd, NiMH or lead acid ➤ Designed for battery pack integration - 120µA typical standby current (self-discharge estimation mode) Small size enables implementations in as little as 1 2 square inch of PCB ➤ 16-pin narrow SOIC Battery self-discharge is estimated based on an internal timer and temperature sensor. Compensations for battery temperature, rate of charge, and self-discharge are applied to the charge counter to provide available capacity information across a wide range of operating conditions. Initial battery capacity, self-discharge rate, display mode, and charge compensation are set using the PROG1-6 pins. Actual battery capacity is automatically “learned” in the course of a discharge cycle from full to empty. Pin Connections Pin Names - ➤ Direct drive of LEDs for capacity display ➤ A u t o m a ti c char g e and s e l f discharge compensation using internal temperature sensor ➤ Simple single-wire serial communications port for subassembly testing LCOM 1 16 VCC SEG1/PROG1 2 15 REF SEG2/PROG2 3 14 DONE SEG3/PROG3 4 13 HDQ SEG4/PROG4 5 12 RBI SEG5PROG5 6 11 SB PROG6 7 10 DISP VSS 8 9 Nominal available charge may be directly indicated using a five-segment LED display. These segments are used to graphically indicate nominal available charge. The bq2013H supports a simple single-line bi-directional serial link to an external processor (common ground). The bq2013H outputs battery information in response to external commands over the serial link. To support battery pack testing, the outputs may also be controlled by command. The external processor may also overwrite some of the bq2013H gas gauge data registers. The bq2013H may operate directly from four nickel cells or three lead acid. With the REF output and an external transistor, a simple, inexpensive regulator can be built to provide VCC from a greater number of cells. Internal registers include available charge, temperature, capacity, battery ID, and battery status. LCOM LED common output REF Voltage reference output SEG1/PROG1 LED segment 1/ Program 1 input DONE Fast charge complete input SEG2/PROG2 LED segment 2 / Program 2 input HDQ Serial communications input/output SEG3/PROG3 LED segment 3/ Program 3 input RBI Register backup input SEG4/PROG4 LED segment 4/ Program 4 input SB Battery sense input DISP Display control input SEG5/PROG5 LED segment 5/ Program 5 input SR Sense resistor input PROG6 Program 6 input VCC Supply voltage SR 16-Pin Narrow SOIC PN2013.eps SLUS120–MAY 1999 B 1 bq2013H DISP Pin Descriptions LCOM DISP pulled high disables the display. DISP floating allows the LED display to be active during certain charge and discharge conditions. Transitioning DISP low activates the display. LED common This open-drain output switches VCC to source current for the LEDs. The switch is off during initialization to allow reading of PROG1-5 pull-up or pull-down program resistors. LCOM is also high impedance when the display is off. SEG1– SEG5 SB RBI Programmed full count selection inputs (dual function with SEG1 - SEG5) HDQ Serial I/O pin This is an open-drain bidirectional communications port. Sense resistor input REF The voltage drop (VSR) across the sense resistor RS is monitored and integrated over time to interpret charge and discharge activity. The SR input (see Figure 1) is connected between the negative terminal of the battery and ground. VSR > VSS indicates charge, and VSR < VSS indicates discharge. The effective voltage drop, VSRO, as seen by the bq2013H is VSR + VOS. DONE Register backup input This input is used to provide backup potential to the bq2013H registers during periods when VCC < 3V. A storage capacitor can be connected to RBI. These three-level input pins define the programmed full-count (PFC), display mode, self-discharge rate, offset compensation, overload threshold, and charge compensation. SR Secondary battery input This input monitors the scaled battery voltage through a high-impedance resistive divider network for the end-of-discharge voltage (EDV) thresholds. LED display segment outputs (dual function with PROG1–PROG5 Each output may activate an LED to sink the current sourced from LCOM. PROG1– PROG6 Display control input Voltage reference output for regulator REF provides a voltage reference output for an optional micro-regulator. Charge complete input This input/output is used to communicate the status of an external charge controller to the bq2013H. 2 VCC Supply voltage input VSS Ground bq2013H Figure 1 shows a typical battery pack application of the bq2013H using the LED display. The bq2013H can be configured to display capacity in either a relative or an absolute display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery “full” reference. The absolute display mode uses the programmed full count (PFC) as the full reference, forcing each segment of the display to represent a fixed amount of charge. A push-button display feature is available for enabling the LED display. Functional Description General Operation The bq2013H determines battery capacity by monitoring the amount of charge input to or removed from a rechargeable battery. The bq2013H measures discharge and charge currents, estimates self-discharge, monitors the battery for low-battery voltage thresholds, and compensates for temperature and charge rates. The charge measurement is made by monitoring the voltage across a small-value series sense resistor between the battery’s negative terminal and ground. The available battery charge is determined by monitoring this voltage over time and correcting the measurement for the environmental and operating conditions. The bq2013H monitors the charge and discharge currents as a voltage across a sense resistor (see RS in Figure 1). A filter between the negative battery terminal and the SR pin is required. R1 bq2013H Gas Gauge IC Q1 ZVNL110A REF C1 LCOM SEG1/PROG1 RB1 VCC SB SEG2/PROG2 RB2 SEG3/PROG3 DISP SEG4/PROG4 SR 100K 0.1µF SEG5/PROG5 H, Z, or L To µC To µC or Fast Charger PROG6 HDQ RBI DONE Charger Notes: 1. RS VSS Indicates optional. 2. The battery stack voltage can be directly connect to VCC across 4 nickel cells (4.8V nominal and should not exceed 6.5V) with a resistor and a zener diode to limit voltage during charge. Otherwise, R1and Q1 are needed for regulation of > 4 nickel cells. Load 3. Programming resistors and ESD-protection diodes are not shown. FG2013H1.eps 4. R-C on SR is required. Figure 1. Application Diagram: LED Display 3 bq2013H Register Backup Temperature The bq2013H RBI input pin is intended to be used with a storage capacitor to provide backup potential to the internal bq2013H registers when VCC momentarily drops below 3.0V. VCC is output on RBI when VCC is above 3.0V. The bq2013H internally determines the temperature in 10°C steps centered from -35°C to +85°C. The temperature steps are used to adapt charge rate compensations and self-discharge counting. The temperature range is available over the serial port in 10°C increments as shown in the following table: After VCC rises above 3.0V, the bq2013H checks the internal registers for data loss or corruption. If data has changed, then the NAC register is cleared, and the LMD register is loaded with the initial PFC. TMPGG (hex) Temperature Range 0x < -30°C 1x -30°C to -20°C In conjunction with monitoring VSR for charge/discharge currents, the bq2013H monitors the battery potential through the SB pin for the end-of-discharge voltage (EDV) thresholds. 2x -20°C to -10°C 3x -10°C to 0°C 4x 0°C to 10°C The EDV threshold levels are used to determine when the battery has reached an “empty” state. 5x 10°C to 20°C 6x 20°C to 30°C The EDV thresholds for the bq2013H are set as follows: 7x 30°C to 40°C EDV1 (first) = 1.00V 8x 40°C to 50°C EDVF (final) = EDV1 - 100mV 9x 50°C to 60°C Ax 60°C to 70°C Bx 70°C to 80°C Cx > 80°C Voltage Thresholds The battery voltage divider (RB1 and RB2 in Figure 1) is used to scale these values to the desired threshold. If VSB is below either of the two EDV thresholds for the specified delay times in Table 1, the associated flag is latched and remains latched, independent of VSB, until the next valid charge. EDV monitoring is disabled if the OVLD bit in FLGS2 is set. Layout Considerations The bq2013H measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally: Table 1. Delay Time in Seconds Capacity > 40% 20% to 40% < 20% Temperature < 10°C 7 4 2 10°C to 30°C 6 3 2 > 30°C 5 2 2 ■ The capacitors should be placed as close as possible to the SB and VCC pins and their paths to VSS should be as short as possible. A high-quality ceramic capacitor of 0.1µf is recommended for VCC. ■ The sense resistor (RS) should be as close as possible to the bq2013H. ■ The R-C on the SR pin should be located as close as possible to the SR pin. The maximum R should not exceed 100K. Reset The bq2013H can be reset by removing VCC and grounding the RBI pin for 15 seconds or with a command over the serial port. The serial port reset command sequence requires writing 00h to register PPFC (address = leh) and the writing 00h to register LMD (address = 05h.) Gas Gauge Operation The operational overview diagram in Figure 2 illustrates the operation of the bq2013H. The bq2013H accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. The bq2013H compensates charge current for charge rate and tem- 4 bq2013H perature. Discharge current is load compensated based on the value stored in location LCOMP (address = 0eh). LCOMP allows the bq2013H to automatically adjust for continuous small discharge currents. The bq2013H compensates self discharge for the load value as well as temperature. 1. Last Measured Discharge (LMD) or learned battery capacity: LMD is the last measured discharge capacity of the battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent discharges, the LMD is updated with the latest measured capacity in the Discharge Count Register (DCR) representing a discharge from full to below EDV. The maximum decrease in LMD because of a DCR update is 25% of LMD. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register. The LMD also serves as the 100% reference threshold used by the relative display mode. The main counter, Nominal Available Capacity (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging, self-discharge decrement the NAC register and increment the DCR (Discharge Count Register). NAC is also corrected automatically for offset error based on the value in the offset location OFFSET (address = 0bh.) The Discharge Count Register (DCR) is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2013H adapts its capacity determination based on the actual conditions of discharge. 2. Programmed Full Count (PFC) or initial battery capacity: The initial LMD and gas gauge rate values are programmed by using PFC. The PFC also provides the 100% reference for the absolute display mode. The bq2013H is configured for a given application by selecting a PFC value from Table 2. The correct PFC may be determined by multiplying the rated battery capacity in mAh by the sense resistor value: The battery’s initial capacity is equal to the Programmed Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime. Battery capacity (mAh) * sense resistor (Ω) = PFC (mVh) Selecting a PFC slightly less than the rated capacity for absolute mode provides capacity above the full reference for much of the battery’s life. Inputs Charge Current Discharge Current Self-Discharge Timer Rate and Temperature Compensation Load Compensation Load and Temperature Compensation Main Counters and Capacity Reference (LMD) + - + Nominal Available Charge (NAC) (offset corrected) < Last Measured Discharged (LMD) Temperature Step, Other Data Temperature Translation Outputs Chip-Controlled Available Charge LED Display + Discharge Count Qualified Register (DCR) Transfer Serial Port FG2013H2.eps Figure 2. Operational Overview 5 bq2013H Therefore: Example: Selecting a PFC Value Given: 5000mAh * 0.0075Ω = 37.5mVh Select: Sense resistor = 0.0075Ω Number of cells = 14 Capacity = 5000mAh, NiCd cells Current range = 1A to 30A Relative display mode with 4 second timer Self-discharge = 1% per day Trickle charge compensation = 0.85 Typical offset = -75µV Voltage drop across sense resistor = 5mV to 150mV PFC = 448000 counts or 35mVh PROG1, PROG2 = Z, L PROG3 = Z PROG4 = H PROG5 = L PROG6 = Z Table 2. bq2013H Programmed Full Count mVh Selections Programmed Full Count (PFC) mVh 27136 84.8 1 24064 75.2 1 41472 64.8 1 35072 54.8 1 28672 44.8 1 44800 35 1 30720 24 1 38400 15 1 12800 5 1 Scale PROG1 PROG2 320 H H 320 H Z 640 H L 640 Z H 640 Z Z 1280 Z L 1280 L H 2560 L Z 2560 L L Table 3. Programmed Self-Discharge PROG3 Self-Discharge H 1.6% per day Z 0.8% per day L 0.2% per day 6 bq2013H Table 4. Programmed Display Mode PROG4 Overload Threshold Display Mode H VOVLD = -75mV Relative/4s timer after push-button release Z VOVLD = -75mV Relative/4s timer after push-button release L VOVLD = -25mV Absolute/4s timer after push-button release Table 5. Programmed Charge Compensation Trickle Fast PROG5 <30°C 30°C—50°C >50°C <30°C 30°C—50°C >50°C H 0.80 0.75 0.70 0.95 0.90 0.85 Z 1.00 1.00 1.00 1.00 1.00 1.00 L 0.85 0.80 0.75 0.95 0.90 0.85 Table 6. Programmed Discharge Offset Adjustment PROG6 Offset H -150µV Z -75µV L 0µV 7 bq2013H The initial full battery capacity is 35mVh (4667mAh) until the bq2013H “learns” a new capacity with a qualified discharge from full to EDV1. 3. Discharge Counting All discharge counts where VSRO < -250µV cause the NAC register to decrement and the DCR to increment. If enabled, the display is activated when VSRO < -2mV. The display remains active for 10 seconds after VSRO rises above - 2mV. Nominal Available Capacity (NAC): NAC counts up during charge to a maximum value of LMD and down during discharge and self discharge to 0. NAC is reset to 0 on initialization and on the first valid charge following discharge to EDV1. To prevent overstatement of charge during periods of overcharge, NAC stops incrementing when NAC = LMD. When the DONE input is asserted high, indicating full charge completion, NAC is set to LMD. 4. Self-Discharge Estimation The bq2013H decrements NAC and increments DCR for self-discharge based on time and temperature. The selfdischarge count rate is programmed per Table 3. This is the rate for a battery temperature between 20–30°C. The NAC register cannot be decremented below 0. Discharge Count Register (DCR): Count Compensations The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0. Prior to NAC = 0 (empty battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches FFFFh. The bq2013H determines fast charge when the NAC updates at a rate of ≥ 2 counts/s. Charge activity is compensated for temperature and rate before updating NAC. Self-discharge estimation is compensated for temperature before updating NAC or DCR. Charge Compensation The DCR value becomes the new LMD value on the first charge after a valid discharge to EDV1 if all of the following conditions are met: ■ ■ ■ ■ Charge efficiency factors are selected using Table 5 for trickle charge and fast charge. Fast charge is defined as a rate of charge resulting in ≥ 2 NAC counts/s (0.16C to 0.6C, depending on PFC selections; see Table 2). No valid charge initiations (charges greater than 2 NAC updates) occurred during the period between NAC = LMD and EDV1. Temperature adapts the charge rate compensation factors over three ranges between nominal, warm, and hot temperatures. Program pin 5 is used to select one of three compensation programs. These values are shown in Table 5. The self-discharge count is less than 6% of NAC. The temperature is ≥ 0°C when the EDV1 level is reached during discharge. VDQ is set. Charge Counting Charge activity is detected based on a positive voltage on the VSR input. If charge activity is detected, the bq2013H increments NAC at a rate proportional to VSRO (VSR + VOS) and, if enabled, activates an LED display if VSRO > 500µV. Charge actions increment the NAC after compensation for charge rate and temperature. The bq2013H detects charge activity with VSRO > 250µV. A valid charge equates to a sustained charge activity greater than 2 NAC updates. Once a valid charge is detected, charge counting continues until VSRO drops below 250µV. 8 bq2013H fast-charge completion, the bq2013H sets NAC = LMD and VDQ = 1. The DONE input should be maintained h ig h a s lon g a s t h e f a s t - c h a r g e c on t r oller o r microcontroller keeps the batteries full; otherwise the pin should be held low. Self-Discharge Compensation The self-discharge compensation can be programmed for three different rates. The rates vary across 8 ranges from <10°C to >70°C, doubling with each higher temperature step (10°C). See Table 7. Communicating With the bq2013 Table 7. Self-Discharge Compensation The bq2013H includes a simple single-pin (HDQ plus return) serial data interface. A host processor uses the interface to access various bq2013H registers. Battery characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain HDQ pin on the bq2013H should be pulled up by the host system, or may be left floating if the serial interface is not used. Self-Discharge Compensation Typical Rate/Day Temperature PROG3 = H Range < 10°C NAC 10–20°C NAC 20–30°C NAC 30–40°C NAC 40–50°C NAC 50–60°C NAC 60–70°C NAC > 70°C NAC 256 128 64 32 16 8 4 2 PROG3 = Z NAC NAC NAC 512 256 128 NAC NAC NAC 64 32 16 NAC NAC 8 4 PROG3 = L NAC NAC 2048 The interface uses a command-based protocol, where the host processor sends a command byte to the bq2013H. The command directs the bq2013H to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte. (See Figure 3.) 1024 NAC NAC NAC 512 256 128 NAC NAC NAC The communication protocol is asynchronous return-to-one. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/s. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2013H may be sampled using the pulse-width capture timers available on some microcontrollers. 64 32 16 Offset Compensation The bq2013H uses a voltage to frequency converter to measure the voltage across a resistor used to monitor the current into and out of the battery. This converter has an offset value that can be influenced by the VCC supply and the bypassing of this supply. The typical value found on a well designed PCB is about -75µV. Program pin 6 can be used to compensate for this offset, reducing the effective VOS. Offset compensation occurs when VSRO < -250µV or VSRO > 250µV. If a communication error occurs, e.g., tCYCB > 250µs, the bq2013H should be sent a BREAK to reinitiate the serial interface. A BREAK is detected when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2013H is now ready to receive a command from the host processor. Error Summary The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2013H taking the HDQ pin to a logic-low state for a period, tSTRH;B. The next section is the actual data transmission, where the data should be valid by a period, tDSU;B, after the negative edge used to start communication. The data should be held for a period, tDH;DV, to allow the host or bq2013H to sample the data bit. The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value includes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description in the “Layout Considerations” section). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual battery capacity. The final section is used to stop the transmission by returning the HDQ pin to a logic-high state by at least a period, tSSU;B, after the negative edge used to start communication. The final logic-high state should be until a period tCYCH;B, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial com- DONE Input A fast-charge controller IC or micro-controller uses the DONE input to communicate charge status to the bq2013H. When the DONE input is asserted high on 9 bq2013H Table 8. bq2013H Current-Sensing Errors Symbol Parameter Typical Maximum Units Notes INL Integrated non-linearity error ±2 ±4 % Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. INR Integrated nonrepeatability error ±1 ±2 % Measurement repeatability given similar operating conditions. munication timing specification and illustration sections. The W/R location is: Command Code Bits Communication with the bq2013H is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication sequence to read the bq2013H NACH register. 7 6 5 4 3 2 1 0 W/R - - - - - - - Where W/R is: bq2013H Command Code and Registers The bq2013H status registers are listed in Table 9 and described below. 0 The bq2013H outputs the requested register contents specified by the address portion of command code. 1 The following eight bits should be written to the register specified by the address portion of command code. Command Code The lower seven-bit field of command code contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored. The bq2013H latches the command code when eight valid command bits have been received by the bq2013H. The command code register contains two fields: ■ W/R bit ■ Command address Command Code Bits 7 The W/R bit of the command code is used to select whether the received command is for a read or a write function. Written by Host to bq2013H CMDR = 03h LSB - 6 5 AD6 AD5 4 3 2 1 0 AD4 AD3 AD2 AD1 AD0 (LSB) Received by Host from bq2013H NAC = 65h MSB LSB Break 1 1 0 0 0 0 0 0 MSB 1 0 1 0 0 11 0 DQ tRSPS TD2013H.eps Figure 3. Typical Communication With the bq2013H 10 bq2013H Table 9. bq2013H Command and Status Registers Symbol Register Name Primary status FLGS1 flags register Loc. Read/ (hex) Write 7(MSB) Control Field 6 5 4 3 2 1 0(LSB) 01h R CHGS BRP RSVD RSVD VDQ RSVD EDV1 EDVF R TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0 TMPGG Temperature and gas gauge register 02h NACH Nominal available capacity high byte register 03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0 NACL Nominal available capacity low byte register 17h R/W NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0 04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0 05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0 06h R CR RSVD RSVD RSVD RSVD RSVD RSVD OVLD Battery BATID identification register LMD Last measured discharge register status FLGS2 Secondary flags register PPD Program pull down register 07h R RSVD RSVD PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 PPU Program pull up register 08h R RSVD RSVD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 OCTL Output control register 0ah R/W 1 OC5 OC4 OC3 OC2 OC1 OCE OCC adjustment OFFSET Offset regisiter 0bh R/W OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 SDR Self discharge rate 0ch R/W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 DMF Digital magnitude filter 0dh R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0 0eh R/W LC7 LC6 LC5 LC4 LC3 LC2 LC1 LC0 compensaLCOMP Load tion CCOMP Fast charge compensation 0fh R/W CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 PPFC Program pin data leh R/W RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSB Battery voltage register 7eh R VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 Notes: RSVD = reserved. All other registers not documented are reserved. 11 bq2013H The VDQ location is: Primary Status Flags Register (FLGS1) The FLGS1 register (address=01h) contains the primary bq2013H flags. FLGS1 Bits The charge status flag (CHGS) is asserted when a valid charge rate is detected. The bq2013H deems the charge valid if it results in two NAC updates with VSRO > 250µV. A VSRO of less than 250µV or discharge activity clears CHGS. 7 6 5 4 3 2 1 0 - - - - VDQ - - - where VDQ is 0 Self-discharge reduces NAC by 6%, valid charge action detected, EDV1 asserted with the temperature less than 0°C, or reset 1 On first discharge after NAC = LMD The CHGS location is: FLGS1 Bits 7 6 5 4 3 2 1 0 CHGS - - - - - - - The first end-of-discharge warning flag (EDV1) warns the user that the battery is empty. SEG1 blinks at a 4Hz rate and DONE is asserted low. EDV1 detection is disabled if OVLD = 1. The EDV flag is latched until a valid charge has been detected. where CHGS is 0 Either discharge activity detected or VSRO < 250µV 1 Two NAC updates with VSRO > 250µV The EDV1 location is: FLGS1 Bits The battery replaced flag (BRP) is asserted whenever the bq2013H is reset by application of VCC or by a serial port command. BRP is reset when either a valid charge action increments NAC to be equal to LMD, or when a valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset. 6 5 4 3 2 1 0 BRP - - - - - - where BRP is 0 1 The valid discharge flag (VDQ) is asserted when the bq2013H is discharged from NAC=LMD. The flag remains set until either LMD is updated or until one of three actions that can clear VDQ occurs: ■ A valid charge action sustained at VSRO > VSRQ for at least two NAC updates ■ The EDV1 flag was set at a temperature below 0°C. 3 2 1 0 - - - - - - EDV1 - 0 Valid charge action detected or VSB ≥ VEDV1 1 VSB < VEDV1 for the delay time, provided that the OVLD bit is not set FLGS1 Bits bq2013H is reset NAC has been reduced by more than 6% during because of self-discharge since VDQ was set 4 The EDVF location is: bq2013H is charged until NAC = LMD or on the first charge after or a discharge which sets the EDV1 flag ■ 5 The final end-of-discharge warning flag (EDVF) flag is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EDVF threshold is set 100mV below the EDV1 threshold. FLGS1 Bits - 6 where EDV1 is The BRP location is: 7 7 7 6 5 4 3 2 1 0 - - - - - - - EDVF Where EDVF is: 12 0 Valid charge action detected or VSB ≥ VEDVF 1 VSB < VEDVF, providing the OVLD bit is not set bq2013H TMPGG Gas Gauge Bits Table 10. Temperature Register Contents 7 6 5 4 3 2 1 0 - - - - GG3 GG2 GG1 GG0 TMP3 TMP2 TMP1 TMP0 Temperature 0 0 0 0 T < -30°C 0 0 0 1 -30°C < T < -20°C 0 0 1 0 -20°C < T < -10°C 0 0 1 1 -10°C < T < 0°C 0 1 0 0 0°C < T < 10°C 0 1 0 1 10°C < T < 20°C 0 1 1 0 20°C < T < 30°C 0 1 1 1 30°C < T < 40°C 1 0 0 0 40°C < T < 50°C 1 0 0 1 50°C < T < 60°C 1 0 1 0 60°C < T < 70°C Last Measured Discharge Register (LMD) 1 0 1 1 70°C < T < 80°C 1 1 0 0 T > 80°C LMD is a read/write register (address=05h) that the bq2013H uses as a measured full reference. The bq2013H adjusts LMD based on the measured discharge capacity of the battery from full to empty. In this way the bq2013H updates the capacity of the battery. LMD is set to PFC during a bq2013H reset. Nominal Available Charge Register (NAC) The NACH register (address=03h) and the NACL register (address=17h) are the main gas gauging registers for the bq2013H. The NAC registers are incremented during charge actions and decremented during discharge and self-discharge actions. The correction factors for charge/discharge efficiency are applied automatically to NAC. NACH and NACL are set to 0 during a bq2013H reset. Battery Identification Register (BATID) The read/write BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as VRBI is greater than 2V. The contents of BATID have no effect on the operation of the bq2013H. There is no default setting for this register. Temperature and Gas Gauge Register (TMPGG) Secondary Status Flags Register (FLGS2) TMPGG Temperature Bits 7 6 TMP3 TMP2 5 4 TMP1 TMP0 3 2 1 - - - The read-only FLGS2 register (address=06h) contains the secondary bq2013H flags. 0 The charge rate flag (CR) is used to denote the fast charge regime. Fast charge is assumed whenever a charge action is initiated. The CR flag remains asserted if the charge rate does not fall below 2 NAC counts/s. The read-only TMPGG register (address=02h) contains two data fields. The first field contains the battery temperature. The second field contains the available charge from the battery. The CR location is: The bq2013H contains an internal temperature sensor. The temperature is used to set charge efficiency factors as well as to adjust the self-discharge coefficient. The temperature register contents may be translated as shown in Table 10. FLGS2 Bits 7 6 5 4 3 2 1 0 CR - - - - - - - Where CR is: The bq2013H calculates the available charge as a function of NAC and a full reference, either LMD or PFC. The results of the calculation are available via the display port or the gas gauge field of the TMPGG register. The register is used to give available capacity in 1 16 increments from 0 to 15 16. 0 When charge rate falls below 2 counts/sec 1 When charge rate is above 2 counts/sec The fast charge regime efficiency factors are used when CR = 1. When CR = 0, the trickle charge efficiency fac- 13 bq2013H tors are used. The time to change CR varies due to the user-selectable count rates. tion. OCE may be cleared by either writing the bit to a logic zero via the serial port or by resetting the bq2013H. The overload flag (OVLD) is asserted when a discharge overload is detected. PROG4 defines the overload threshold, as defined in Table 4. OVLD remains asserted as long as the condition is valid. Offset Adjustment Register The value in this register (address = 0bh) is used to correct NAC for the offset of the VFC. This register is initialized from the state of PROG6. The following are the initial values: The OVLD location is: FLGS2 Bits 7 6 5 4 3 2 1 0 - - - - - - - OVLD 0 If VSRO > VOVLD 1 If VSRO < VOVLD ■ 46 = -75µV correction ■ 23 = -150µV correcton Offset = Self-Discharge Rate Compensation The PPD register (address=07h) contains some of the programming pin information for the bq2013H. The program pins have a corresponding PPD bit location, PPD1–6. A given location is set if a pull-down resistor has been detected on its corresponding segment driver. For example, if PROG1 and PROG4 have pull-down resistors, the contents of PPD are xx001001. This register contains the value used to correct for the self-discharge compensation. This value is initialized from the state of PROG3. The following are the initial values: PPD/PPU Bits 5 4 3 2 1 1 289∗ VCOS where VCOS is the desired offset correction in volts. Program Pin Pull-Down Register (PPD) 6 0 = no offset correction The value is set by the equation: Where OVLD is: 7 ■ ■ 1 235 = 1.6% per day 64 ■ 1 214 = 0.8% per day 128 ■ 1 88 = 0.2% per day 512 0 RSVD RSVD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 RSVD RSVD PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 The value is set by the equation: Program Pin Pull-Up Register (PPU) 0.3296 SDR = 256 − CSD The PPU register (address=08h) contains the rest of the programming pin information for the bq2013H. The program pins have a corresponding PPU bit location, PPU1–6. A given location is set if a pull-up resistor has been detected on its corresponding segment driver. For example, if PROG3 and PROG5 have pull-up resistors, the contents of PPU are xx010100. where CSD is the self-discharge rate per day. Digital Magnitude Filter (DMF) The read-write DMF register (address=0dh) provides the system with a means to change the default settings of the digital magnitude filter. By writing different values into this register, the limits of VSRD and VSRQ can be adjusted. The default value for the DMF is 250µV. The value is set by the equation: Output Control Register (OCTL) The write-only OCTL register (address=0ah) provides the system with a means to check the display connections for the bq2013H. The segment drivers may be overwritten by data from OCTL when bit 1 of OCTL, OCE, is set. The data in bits OC5–1 of the OCTL register (see Table 9 for details) is output onto the segment pins, SEG5–1, respectively if OCE=1. Whenever OCE is written to 1, the MSB of OCTL should be set to a 1. The OCE register location must be cleared to return the bq2013H to normal opera- DMF = 45 VSRD, Q where VSRD,Q is the desired filter threshold in mV. Note: Care should be taken when writing to this register. A VSRD and VSRQ below the specified VOS may adversely affect the accuracy of the bq2013H. 14 bq2013H VSB VSB = 1.2V ∗ 256 Load Compensation The load compensation value (address = 0eh) allows the bq2013H to compensate for small discharge loads that are below the digital filter. Each increment in the LCOMP register represents 2µVh. The value in LCOMP represents the additional amount of discharge applied to NAC and DCR at a constant rate when VSRO < VSRQ. LCOMP compensation is applied in addition to selfdischarge. LCOMP is set to 0 on a full reset. The value is set by the equation: Display The bq2013H can directly display capacity information using low-power LEDs. If LEDs are used, the segment pins should be tied to VCC, the battery, or the LCOM pin through resistors for programming the bq2013H. The bq2013H displays the battery charge state in either absolute or relative mode. In relative mode, the battery charge is represented as a percentage of the LMD. Each LED segment represents 20% of the LMD. 1 LCOMP = 289∗ VCLD where VCLD is the desired load correction in volts. In absolute mode, each segment represents a fixed amount of charge, based on the initial PFC. In absolute mode, each segment represents 20% of the PFC. As the battery wears out over time, it is possible for the LMD to be below the initial PFC. In this case, all of the LEDs may not turn on, representing the reduction in the actual battery capacity. Charge Compensation The charge-compensation value (address = 0fh) allows the bq2013H to compensate for battery charge inefficiencies. This value is initialized from the state of PROG5 and represents the fast-charge compensation factor for < 30°C. The value can be overwritten via the serial port and is stored in percent. The bq2013H scales the value in 0fh to determine the compensation at other rates and temperatures. For example, if PROG5 = H, the applied efficiency drops by 5% for each temperature range, and the trickle rates are 15% below the fastcharge rates. If the value 55h (85%) is written to CCOMP, the compensation for trickle charge at > 50°C is 60%. When DISP is tied to VCC, the SEG1–5 outputs are inactive. When DISP is left floating, the display becomes active during charge if the NAC registers are counting at a rate equivalent to VSRO > 500µV or fast discharge if the NAC registers are counting at a rate equivalent to VSRO < -2mV. When DISP is pulled low and held, the segment outputs become active continuously. When released to high Z, the segment outputs will remain active for 4 seconds. The segment outputs are modulated as two banks, with segments 1, 3, and 5 alternating with segments 2 and 4. The segment outputs are modulated at approximately 320Hz, with each bank active for 30% of the period. Program Pin Data (PPFC) The PPFC register provides the means to perform a software controlled reset of the device. The recommended reset method for the bq2013H is: ■ Write PPFC to zero ■ Write LMD to zero SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 to indicate a low-battery condition or NAC is less than 10% of the LMD or PFC, depending on the display mode. After these operations, a software reset occurs. Microregulator Resetting the bq2013H sets the following: ■ LMD = PFC ■ VDQ, OCE, LCOMP, and NAC = 0 ■ BRP = 1 The bq2013H can operate directly from 4 nickel or 3 lead acid cells. To facilitate the power supply requirements of the bq2013H, an REF output is provided to regulate an external low-threshold n-FET. A micropower source for the bq2013H can be inexpensively built using the FET and an external resistor. Battery Voltage Register (VSB) The battery voltage register is used to read the battery voltage on the SB pin. The VSB register (address = 7eh) is updated approximately once per second with the present value of the battery voltage. The battery voltage on the SB pin is determined by the equation: 15 bq2013H Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Notes VCC Relative to VSS -0.3 +7.0 V All other pins Relative to VSS -0.3 +7.0 V REF Relative to VSS -0.3 +8.5 V Current limited by R1 (see Figure 1) VSR Relative to VSS -0.3 Vcc+0.7 V 100kΩ series resistor should be used to protect SR in case of a shorted battery. TOPR Operating temperature 0 +70 °C Commercial Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V) Symbol Parameter Minimum Typical Maximum Unit 0.96 ∗ VEDV VEDV 1.04 ∗ VEDV V Notes VEDV End-of-discharge warning VSRO SR sense range -300 - +500 mV SR, VSR + VOS VSRQ Valid charge 250 - - µV VSR + VOS VSRD Valid discharge - - -250 µV VSR + VOS Note: SB VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance. See “LayoutConsiderations.” 16 bq2013H DC Electrical Characteristics (TA = TOPR) Symbol VCC VOS VREF RREF ICC Parameter Supply voltage Minimum Typical Maximum Unit Notes VCC excursion from < 2.0V to ≥ 3.0V initializes the unit. 3.0 4.25 6.5 V - ±50 ±150 µV DISP = VCC Reference at 25°C 5.7 6.0 6.3 V IREF = 5µA Reference at -40°C to +85°C 4.5 - 7.5 V IREF = 5µA Reference input impedance 2.0 5.0 - MΩ VREF = 3V - 90 135 µA VCC = 3.0V, HDQ = 0 - 120 180 µA VCC = 4.25V, HDQ = 0 - 170 250 µA VCC = 6.5V, HDQ = 0 Offset referred to VSR Normal operation VSB Battery input 0 - VCC V RSBmax SB input impedance 10 - - MΩ 0 < VSB < VCC IDISP DISP input leakage - - 5 µA VDISP = VSS ILCOM LCOM input leakage -0.2 - 0.2 µA DISP = VCC IRBI RBI data-retention current - - 100 nA VRBI > VCC < 3V RHDQ Internal pulldown 500 - - KΩ RSR SR input impedance 10 - - MΩ VIHPFC PROG logic input high VCC - 0.2 - - V VILPFC PROG logic input low VIZPFC PROG logic input Z VOLSL -200mV < VSR < VCC PROG1-6 - - VSS + 0.2 V PROG1-6 float - float V PROG1-6 SEG output low, low VCC - 0.1 - V VCC = 3V, IOLS ≤ 1.75mA SEG1–SEG5, DONE VOLSH SEG output low, high VCC - 0.4 - V VCC = 6.5V, IOLS ≤ 11.0mA SEG1–SEG5, DONE VCC = 3V, IOHLCOM = -5.25mA VOHML LCOM output high, low VCC VCC - 0.3 - - V VOHMH LCOM output high, high VCC VCC - 0.6 - - V IOLS SEG sink current 11.0 - - mA At VOLSH = 0.4V, VCC = 6.5V IOL Open-drain sink current 5.0 - - mA At VOL = VSS + 0.3V, HDQ VOL Open-drain output low - - 0.3 V IOL ≤ 5mA, HDQ VIHDQ HDQ input high 2.5 - - V HDQ VILDQ HDQ input low - - 0.8 V HDQ VIH DONE input high 2.5 - - V DONE VIL DONE input low - - 0.5 V DONE RPROG Soft pull-up or pull-down resistor value (for programming) - - 200 kΩ PROG1–6 RFLOAT Float state external impedance - 5 - MΩ PROG1-6 Note: All voltages relative to VSS. 17 VCC > 3.5V, IOHLCOM = -33.0mA bq2013H High-Speed Serial Communication Timing Specification (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tCYCH Cycle time, host to bq2013H (write) 190 - - µs tCYCB Cycle time, bq2013H to host (read) 190 205 250 µs tSTRH Start hold, host to bq2013H (write) 5 - - ns tSTRB Start hold, bq2013H to host (read) 32 - - µs tDSU Data setup - - 50 µs tDSUB Data setup - - 50 µs tDH Data hold 90 - - µs tDV Data valid - - 80 µs tSSU Stop setup - - 145 µs tSSUB Stop setup - - 145 µs tRSPS Response time, bq2013H to host 190 - 320 µs tB Break 190 - - µs tBR Break recovery 40 - - µs Note: Notes See note The open-drain HDQ pin should be pulled to at least VCC by the host system for proper HDQ operation. HDQ may be left floating if the serial interface is not used. 18 bq2013H Break Timing tBR tB TD201803.eps Host to bq2013H Write "1" Write "0" tSTRH tDSU tDH tSSU tCYCH bq2013H to Host Read "1" Read "0" tSTRB tDSUB tDV tSSUB tCYCB 19 bq2013H 16-Pin SOIC Narrow (SN) 16-Pin SN (SOIC Narrow) D e Dimension Minimum A 0.060 A1 0.004 B 0.013 C 0.007 D 0.385 E 0.150 e 0.045 H 0.225 L 0.015 All dimensions are in inches. B E H A C A1 .004 L 20 Maximum 0.070 0.010 0.020 0.010 0.400 0.160 0.055 0.245 0.035 bq2013H Data Sheet Revision History ChangeNo. Page No. 1 All 2 3 Updated application diagram 2 8 Changed charge/discharge default threshold from 200µV to 250µV. 2 9 Changed offset compensation window range from ±200µV to ±250µV 2 11 Designated appropriate locations from “R/W” to “R” 2 12 Changed charge threshold from 200µV to 250µV 2 14 Changed default DMF from 200µV to 250µV 2 16 Added REF absolute maximum rating 2 16 Changed charge/discharge default threshold from 200µV to 250µV 2 16 Added VSRO parameter 2 17 Changed DQ designation to HDQ 2 17 Changed VOL from 0.5V to 0.3V (max.) 2 17 Added RPROG Note: Description of Change “Final” changes from “Preliminary” version Change 1 = Dec. 1998 changes from July 1998 “Preliminary.” Change 2 = May 1999 B changes from Dec. 1998. 21 bq2013H Ordering Information bq2013H Temperature Range: blank = Commercial (0 to +70°C) Package Option: SN = 16-pin narrow SOIC Device: bq2013H Gas Gauge IC 22 Notes 23 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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