ONSEMI NLAST4051DR2

NLAST4051
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
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The NLAST4051 is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology
for lower RDS(on) resistance and improved linearity with low current.
This device may be operated either with a single supply or dual supply up
to ±3 V to pass a 6 VPP signal without coupling capacitors.
When operating in single supply mode, it is only necessary to tie
VEE, pin 7 to ground. For dual supply operation, VEE is tied to a
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit are standard TTL level
compatible. For CMOS compatibility see NLAS4051. Pin for pin
compatible with all industry standard versions of ‘4051.’
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
1
16
• Improved RDS(on) Specifications
• Pin for Pin Replacement for MAX4051 and MAX4051A
•
•
•
•
1
− One Half the Resistance Operating at 5.0 V
Single or Dual Supply Operation
− Single 3.0 − 5.0 V Operation, or Dual ±3 V Operation
− With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
− No Translators Needed
− Address and Inhibit Logic are Over−Voltage Tolerant and May Be
− Driven Up +6 V Regardless of VCC
Address and Inhibit Pins Standard TTL Compatible
− Greatly Improved Noise Margin Over MAX4051 and MAX4051A
− True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V
Improved Linearity Over Standard HC4051 Devices
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
Pb−Free Packages are Available*
VCC
16
1
NO1
NO2
NO4
NO0
NO6 ADDC ADDB ADDA
15
14
13
12
2
3
NO3 COM
4
5
NO7
NO5
11
10
6
7
Inhibit VEE
AST
4051
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
Features
•
NLAST4051
AWLYWW
1
16
QSOP−16
QS SUFFIX
CASE 492
NLAST
4051
ALYW
1
1
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
9
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
8
GND
Figure 1. Pin Connection
(Top View)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 4
1
Publication Order Number:
NLAST4051/D
NLAST4051
TRUTH TABLE
Address
Inhibit
C
B
A
X
don’t care
X
don’t care
X
don’t care
All switches open
0
0
0
0
COM−NO0
0
0
0
1
COM−NO1
0
0
1
0
COM−NO2
0
0
1
1
COM−NO3
0
1
0
0
COM−NO4
0
1
0
1
COM−NO5
0
1
1
0
COM−NO6
0
1
1
1
COM−NO7
1
NO0
ON SWITCHES*
NO1
NO2
NO3
COM
NO4
NO5
NO6
NO7
ADDC
ADDB
ADDA
*NO and COM pins are identical and interchangeable. Either may be considered
an input or output; signals pass equally well in either direction.
LOGIC
Inhibit
Figure 2. Logic Diagram
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VEE
Negative DC Supply Voltage
(Referenced to GND)
−7.0 to )0.5
V
VCC
Positive DC Supply Voltage (Note 1)
(Referenced to GND)
(Referenced to VEE)
−0.5 to )7.0
−0.5 to )7.0
V
VIS
Analog Input Voltage
VEE −0.5 to VCC )0.5
V
VIN
Digital Input Voltage
−0.5 to 7.0
V
$50
mA
−65 to )150
°C
I
TSTG
(Referenced to GND)
DC Current, Into or Out of Any Pin
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature under Bias
JA
Thermal Resistance
PD
Power Dissipation in Still Air
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILATCHUP
ESD Withstand Voltage
Latchup Performance
260
°C
)150
°C
SOIC
TSSOP
QSOP
143
164
164
°C/W
SOIC
TSSOP
QSOP
500
450
450
mW
Level 1
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
u1000
V
Above VCC and Below GND at 125°C (Note 5)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of VCC $|VEE| ≤ 7.0.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
NLAST4051
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Min
Max
Unit
VEE
Negative DC Supply Voltage
Parameter
(Referenced to GND)
−5.5
GND
V
VCC
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
2.5
2.5
5.5
6.6
V
VIS
Analog Input Voltage
VEE
VCC
V
VIN
Digital Input Voltage
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Channel Select or Enable Inputs)
(Note 6) (Referenced to GND)
VCC = 3.0 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
0
5.5
V
−55
125
°C
0
0
100
20
ns/V
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Condition
Guaranteed Limit
VCC
V
−55 to 25°C
v85°C
v125°C
Unit
Symbol
Parameter
VIH
Minimum High−Level Input Voltage,
Address or Inhibit Inputs
3.0
4.5
5.5
1.6
2.0
2.0
1.6
2.0
2.0
1.6
2.0
2.0
V
VIL
Maximum Low−Level Input Voltage,
Address or Inhibit Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
IIN
Maximum Input Leakage Current,
Address or Inhibit Inputs
VIN = 6.0 or GND
0 V to 6.0 V
$0.1
$1.0
$1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Address or Inhibit and
VIS = VCC or GND
6.0
4.0
40
80
A
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ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
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DC ELECTRICAL CHARACTERISTICS − Analog Section
Symbol
RON
RON
Rflat(ON)
Parameter
VEE
V
−55 to 25°C
v85°C
v125°C
Unit
3.0
4.5
3.0
0
0
−3.0
86
37
26
108
46
33
120
55
37
3.0
4.5
3.0
0
0
−3.0
15
13
10
20
18
15
20
18
15
VCOM = 1, 2, 3.5 V
VCOM = 2, 0, 2 V
4.5
3.0
4
2
4
2
5
3
3.0
Test Conditions
Maximum “ON” Resistance
VIN = VIL or VIH
VIS = (VEE to VCC)
|IS| = 10 mA
(Figures 4 thru 9)
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
VIN = VIL or VIH,
ON Resistance Flatness
Guaranteed Limit
VCC
V
|IS| = 10 mA,
VIS= 2.0 V
VIS= 3.0 V
VIS= 2.0 V
INC(OFF)
INO(OFF)
Maximum Off−Channel
Leakage Current
Switch Off
VIN = VIL or VIH
VIO = VCC −1.0 V or VEE +1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
ICOM(ON)
Maximum On−Channel
Leakage Current,
Channel−to−Channel
Switch On
VIO = VCC −1.0 V or VEE +1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
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NLAST4051
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎ
ÎÎ
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ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
AC CHARACTERISTICS (Input tr = tf = 3 ns)
Guaranteed Limit
Symbol
tBBM
Parameter
Test Conditions
Minimum Break−Before−Make Time
VIN = VIL or VIH
VIS = VCC
RL = 300 CL = 35 pF
(Figure 19)
VCC
V
VEE
V
3.0
4.5
3.0
0.0
0.0
−3.0
−55 to 25°C
Min
Typ*
v85°C
v125°C
Unit
1.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
*Typical Characteristics are at 25°C.
AC CHARACTERISTICS (CL = 35 pF, Input tr = tf = 3 ns)
Guaranteed Limit
v85°C
−55 to 25°C
VCC
V
VEE
V
Transition Time
(Address Selection Time)
(Figure 18)
2.5
3.0
4.5
3.0
0
0
0
−3.0
40
28
23
23
tON
Turn−on Time
(Figures 14, 15, 20, and 21)
Enable to NO or NC
2.5
3.0
4.5
3.0
0
0
0
−3.0
tOFF
Turn−off Time
(Figures 14, 15, 20, and 21)
Enable to NO or NC
2.5
3.0
4.5
3.0
0
0
0
−3.0
Symbol
tTRANS
Parameter
Min
Typ
Max
Min
v125°C
Max
Min
Max
Unit
45
30
25
25
50
35
30
28
ns
40
28
23
23
45
30
25
25
50
35
30
28
ns
40
28
23
23
45
30
25
25
50
35
30
28
ns
Typical @ 25°C, VCC = 5.0 V
CIN
Maximum Input Capacitance,Select Inputs
8
CNO or CNC
Analog I/O
10
CCOM
Common I/O
10
C(ON)
Feedthrough
1.0
pF
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
Condition
Typ
VCC
V
VEE
V
25°C
Unit
0.0
0.0
0.0
−3.0
80
90
95
95
MHz
BW
Maximum On−Channel
Bandwidth or Minimum
Frequency Response
VIS = ½ (VCC − VEE)
Source Amplitude = 0 dBm
(Figures 10 and 22)
3.0
4.5
6.0
3.0
VISO
Off−Channel Feedthrough
Isolation
f = 100 kHz; VIS = ½ (VCC − VEE)
Source = 0 dBm
(Figures 12 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−93
−93
−93
−93
dB
VONL
Maximum Feedthrough
On Loss
VIS = ½ (VCC − VEE)
Source = 0 dBm
(Figures 10 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−2
−2
−2
−2
dB
Charge Injection
VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns
RIS = 0 , CL= 1000 pF, Q = CL * VOUT
(Figures 16 and 23)
5.0
3.0
0.0
−3.0
9.0
12
pC
Total Harmonic Distortion
THD + Noise
fIS = 1 MHz, RL = 10 K, CL = 50 pF,
VIS = 5.0 VPP sine wave
VIS = 6.0 VPP sine wave
(Figure 13)
6.0
3.0
0.0
−3.0
0.10
0.05
Q
THD
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4
%
NLAST4051
100
100
10
2.0 V
80
RON ()
ICC (nA)
1
0.1
0.01
40
VCC = 3.0 V
0.001
3.0 V
$3.3 V
4.5 V
5.5 V
20
0.0001
VCC = 5.0 V
0.00001
−40
−20
0
20
60
80
100
0
−4.0
120
−2.0
0
2.0
4.0
6.0
Temperature (°C)
VIS (VDC)
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 255C
50
100
125°C
90
125°C
85°C
40
80
25°C
70
60
RON ()
RON ()
60
50
85°C
40
25°C
30
20
−55°C
30
10
20
−55°C
10
0
0
0.5
1.0
1.5
0
2.0
1.0
1.5
2.0
2.5
VCom (V)
Figure 5. Typical On Resistance
VCC = 2.0 V, VEE = 0 V
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
25
3.0
25
125°C
125°C
85°C
85°C
20
20
15
RON ()
RON ()
0.5
VCom (V)
10
25°C
15
25°C
10
−55°C
−55°C
5
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VCom (V)
VCom (V)
Figure 7. Typical On Resistance
VCC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
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5
5
5.5
NLAST4051
25
125°C
85°C
RON ()
20
15
10
−55°C
25°C
5
0
−4
−2
0
VCom (V)
2
4
Figure 9. Typical On Resistance
VCC = 3.3 V, VEE = −3.3 V
90
40
72
PHASE SHIFT 18%/DIV (dB)
50
BANDWIDTH (dB)
30
20
10
0
−10
BANDWIDTH (ON−RESPONSE)
−20
−30
−40
54
36
18
0
PHASE SHIFT
−18
−36
−54
−72
−50
−90
0.1
1.0
10
100
0.1
FREQUENCY (mHz)
1.0
10
100
FREQUENCY (mHz)
Figure 10. Bandwidth
Figure 11. Phase Shift
0
0
−20
−30
DISTORTION (%)
OFF ISOLATION 10 dB/DIV
−10
−40
−50
−60
−70
3.0
5.5
4.5
0.1
$3.3
−80
−90
−100
0.01
0.1
1.0
10
100
10
FREQUENCY (mHz)
100
1000
10000
10000
FREQUENCY (mHz)
Figure 12. Off Isolation
Figure 13. Total Harmonic Distortion
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6
NLAST4051
30
30
VCC = 4.5 V
25
20
20
TIME (ns)
TIME (ns)
TA = 25°C
25
15
tON (ns)
10
tOFF (ns)
5
0
2.5
3
3.5
4
4.5
15
10
tON
5
tOFF
0
−55
5
−40
25
85
125
VCC (VOLTS)
Temperature (°C)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
100
2.5
10
VCC = 5 V
LEAKAGE (nA)
Q (pC)
2.0
1.5
1.0
0.5
1
ICOM(ON)
0.1
ICOM(OFF)
VCC = 3 V
0.01
0
VCC = 5.0 V
INO(OFF)
−0.5
0.001
0
1
2
3
4
5
−55
−20
25
70
85
125
VCOM (V)
TEMPERATURE (°C)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
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7
NLAST4051
VCC
0.1 F
VCC
Output
VOUT
VEE
300 50%
Input
50%
0V
35 pF
VCC
90%
Output
Address Select Pin
10%
VEE
ttrans
ttrans
Figure 18. Channel Selection Propagation Delay
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
300 tBMM
35 pF
90%
90% of VOH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break−Before−Make)
VCC
DUT
VCC
0.1 F
Input
50%
0V
Output
VOUT
Open
300 50%
VOH
35 pF
90%
90%
Output
Input
GND
Enable
tON
Figure 20. tON/tOFF
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8
tOFF
NLAST4051
VCC
VCC
Input
DUT
VOUT
Open
50%
0V
300 Output
50%
VCC
35 pF
Output
Input
10%
VOL
Enable
tOFF
Figure 21. tON/tOFF
50 Reference
DUT
Transmitted
Input
Output
50 Generator
50 Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off
channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input
signal direction.
VISO = Off Channel Isolation = 20 Log
VONL = On Channel Loss = 20 Log
ǒVVOUT
Ǔ for VIN at 100 kHz
IN
ǒVVOUT
Ǔ for VIN at 100 kHz to 50 MHz
IN
Bandwidth (BW) = the frequency 3 dB below VONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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9
10%
tON
NLAST4051
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
VIN
Off
On
VOUT
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
16
VEE
GND
+3.0 V
VCC
16
VEE
7
8
GND
VCC
7
8
−3.0 V
Figure 24. 5.0 Volts Single Supply
VCC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = −3.0 V
ORDERING INFORMATION
Package
Shipping†
SOIC−16
48 Units / Rail
NLAST4051DT
TSSOP−16*
96 Units / Rail
NLAST4051DTR2
TSSOP−16*
2500 Tape & Reel
NLAST4051DTR2G
TSSOP−16*
2500 Tape & Reel
NLAST4051QSR
SOEIAJ−16
2000 Tape & Reel
Device
NLAST4051DR2
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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10
NLAST4051
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
1
8
−B−
P
8 PL
0.25 (0.010)
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
S
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
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11
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
NLAST4051
PACKAGE DIMENSIONS
QSOP−16
QS SUFFIX
CASE 492−01
ISSUE O
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
Q
R
H x 45_
U
RAD.
0.013 X 0.005
DP. MAX
−B−
MOLD PIN
MARK
RAD.
0.005−0.010
TYP
G
L
0.25 (0.010)
M
P
T
DETAIL E
V
K
C
N 8 PL
INCHES
DIM
MIN
MAX
A
0.189
0.196
B
0.150
0.157
C
0.061
0.068
D
0.008
0.012
F
0.016
0.035
G
0.025 BSC
H
0.008
0.018
J 0.0098 0.0075
K
0.004
0.010
L
0.230
0.244
M
0_
8_
N
0_
7_
P
0.007
0.011
Q
0.020 DIA
R
0.025
0.035
U
0.025
0.035
V
0_
8_
MILLIMETERS
MIN
MAX
4.80
4.98
3.81
3.99
1.55
1.73
0.20
0.31
0.41
0.89
0.64 BSC
0.20
0.46
0.249
0.191
0.10
0.25
5.84
6.20
0_
8_
0_
7_
0.18
0.28
0.51 DIA
0.64
0.89
0.64
0.89
0_
8_
−T−
D 16 PL
0.25 (0.010)
SEATING
PLANE
M
T B
S
A
S
J
M
F
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
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12
For additional information, please contact your
local Sales Representative.
NLAST4051/D