ONSEMI MC74VHCT157AD

MC74VHCT157A
Quad 2-Channel Multiplexer
The MC74VHCT157A is an advanced high speed CMOS quad
2–channel multiplexer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
It consists of four 2–input digital multiplexers with common select (S)
and enable (E) inputs. When E is held High, selection of data is inhibited
and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed to
the corresponding Y outputs.
The VHCT inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V because it has full
5 V CMOS level output swings.
The VHCT157A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage. The
output structures also provide protection when VCC = 0 V. These input and
output structures help prevent device destruction caused by supply
voltage—input/output voltage mismatch, battery backup, hot insertion, etc.
The inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 4.1ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 82 FETs or 20 Equivalent Gates
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MARKING DIAGRAMS
16
9
VHCT157A
AWLYWW
SO–16
D SUFFIX
CASE 751B
1
8
16
9
VHCT157A
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
1
8
9
16
VHCT157A
ALYW
EIAJ SO–16
M SUFFIX
CASE 966
A
L, WL
Y
W, WW
8
1
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74VHCT157AD
SO–16
48 Units/Rail
MC74VHCT157ADR2
SO–16
2500 Tape & Reel
TSSOP–16
96 Units/Rail
MC74VHCT157ADT
MC74VHCT157ADTR2 TSSOP–16 2500 Tape & Reel
MC74VHCT157AM
EIAJ–SO–16
50 Units/Rail
MC74VHCT157AMEL EIAJ–SO–16 2000 Tape & Reel
 Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 1
1
Publication Order Number:
MC74VHCT157A/D
MC74VHCT157A
A0
B0
A1
S
1
16
VCC
A0
2
15
E
B1
NIBBLE
INPUTS
A2
B2
B0
3
14
A3
Y0
4
13
B3
A1
5
12
Y3
B1
6
11
A2
E
Y1
7
10
B2
S
GND
8
9
Y2
A3
B3
2
A0
B0
A1
B1
A2
B2
A3
B3
15
1
2
3
5
6
7
6
MUX
11
10
14
13
Y1
11
9 Y2
10
14
12 Y3
13
15
1
Figure 2. Expanded Logic Diagram
EN
G1
1
1
Y0
5
Figure 1. Pin Assignment
E
S
4
3
4
7
9
12
Y0
FUNCTION TABLE
Y1
Inputs
Y2
Y3
E
S
Outputs
Y0 – Y3
H
L
L
X
L
H
L
A0–A3
B0–B3
A0 – A3, B0 – B3 = the levels
of the respective Data–Word
Inputs.
Figure 3. IEC Logic Symbol
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
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2
DATA
OUTPUTS
MC74VHCT157A
MAXIMUM RATINGS (Note 1.)
Value
Unit
VCC
Symbol
Positive DC Supply Voltage
Parameter
–0.5 to +7.0
V
VIN
Digital Input Voltage
–0.5 to +7.0
V
VOUT
DC Output Voltage
–0.5 to +7.0
–0.5 to VCC +0.5
V
IIK
Input Diode Current
–20
mA
IOK
Output Diode Current
20
mA
IOUT
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air
200
180
mW
TSTG
Storage Temperature Range
–65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 2.)
Machine Model (Note 3.)
Charged Device Model (Note 4.)
>2000
>200
>2000
V
ILATCH–UP
Latch–Up Performance
Above VCC and Below GND at 125°C (Note 5.)
300
mA
JA
Thermal Resistance, Junction to Ambient
143
164
°C/W
Output in 3–State
High or Low State
SOIC Package
TSSOP
SOIC Package
TSSOP
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
TA
Operating Temperature Range, all Package Types
tr, tf
Input Rise or Fall Time
Output in 3–State
High or Low State
VCC = 5.0 V + 0.5 V
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
VCC
V
–55
125
°C
0
20
ns/V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHCT157A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Condition
(V)
Min
2
VIH
Minimum High–Level
Input Voltage
4.5 to 5.5
VIL
Maximum Low–Level
Input Voltage
4.5 to 5.5
VOH
Maximum High–Level
Output
Ou
u Voltage
o age
VOL
Maximum Low–Level
Output
Ou
u Voltage
o age
TA ≤ 85°C
TA = 25°C
Typ
Max
Min
Max
Min
2
0.8
2
0.8
VIN = VIH or VIL
IOH = –50 µA
4.5
4.4
VIN = VIH or VIL
IOH = –8 mA
4.5
3.94
VIN = VIH or VIL
IOL = 50 µA
4.5
–55°C ≤ TA ≤ 125°C
0.8
Max
Unit
V
0.8
V
V
4.5
4.4
4.4
3.8
3.66
V
VIN = VIH or VIL
IOH = 8 mA
0.0
0.1
0.1
0.1
4.5
0.36
0.44
0.52
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to 5.5
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
4.0
40.0
40.0
µA
ICCT
Additional Quiescent
Supply Current
(per Pin)
Any one input:
VIN = 3.4 V
All other inputs:
VIN = VCC or GND
5.5
1.35
1.5
1.5
µA
IOPD
Output Leakage
Current
VOUT = 5.5 V
0
0.5
5
5
µA
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = ≤ 85°C
TA = 25°C
Symbol
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
CIN
Parameter
Min
Test Conditions
–55°C ≤ TA ≤ 125°C
Typ
Max
Min
Max
Min
Max
Unit
ns
Maximum Propagation
Delay
A to B to Y
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
5.6
8.0
7.0
10.0
1.0
1.0
7.7
11.0
1.0
1.0
7.7
11.0
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
4.1
5.6
6.4
8.4
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
Maximum Propagation
Delay
S to Y
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
6.1
8.5
7.5
10.5
1.0
1.0
8.2
11.5
1.0
1.0
8.2
11.5
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
5.3
6.8
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
Maximum Propagation
Delay
E to Y
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
6.1
8.5
7.5
10.5
1.0
1.0
8.2
11.5
1.0
1.0
8.2
11.5
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
5.6
7.1
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
10.0
12.0
4
10
Maximum Input
Capacitance
10
10
ns
ns
pF
Typical @ 25°C, VCC = 5.0 V
CPD
20
Power Dissipation Capacitance (Note 6.)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no–load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74VHCT157A
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
– 0.3
– 0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
VCC
A, B or S
50%
tPLH
Y
VCC
50%
A, B or S
GND
tPHL
tPLH
50% VCC
tPHL
50% VCC
Y
Figure 5. Switching Waveform
Figure 6. Inverting Switching
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
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5
GND
MC74VHCT157A
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
–V–
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
G
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC74VHCT157A
PACKAGE DIMENSIONS
SOIC EIAJ–16
M SUFFIX
CASE 966–01
ISSUE O
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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7
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
--0.031
MC74VHCT157A
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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