TI TPIC6C596D

SLIS093C − MARCH 2000 − REVISED APRIL 2005
D Low rDS(on) . . . 7 Ω Typ
D Avalanche Energy . . . 30 mJ
D Eight Power DMOS Transistor Outputs of
D
D
D
D
D
D
D, N, OR PW PACKAGE
(TOP VIEW)
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
100-mA Continuous Current
250-mA Current Limit Capability
ESD Protection . . . 2500 V
Output Clamp Voltage . . . 33 V
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
logic symbol†
description
The TPIC6C596 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
G
RCK
CLR
SRCK
SER IN
8
EN3
10
7
R
15
2
C2
SRG8
C1
1D
2
3
4
5
DRAIN0
DRAIN1
DRAIN2
This device contains an 8-bit serial-in, parallel-out
6
DRAIN3
shift register that feeds an 8-bit D-type storage
11
DRAIN4
register. Data transfers through both the shift and
12
DRAIN5
storage registers on the rising edge of the shift
13
register clock (SRCK) and the register clock
DRAIN6
14
(RCK), respectively. The storage register transDRAIN7
2
fers data to the output buffer when shift register
9
SER OUT
clear (CLR) is high. When CLR is low, all registers
in the device are cleared. When output enable (G)
† This symbol is in accordance with ANSI/IEEE Std 91-1984
is held high, all data in the output buffers is held
and IEC Publication 617-12.
low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000–2005, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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1
SLIS093C − MARCH 2000 − REVISED APRIL 2005
description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous
sink-current capability. Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit
decreases as the junction temperature increases for additional device protection. The device also provides up
to 2500 V of ESD protection when tested using the human-body model and the 200-V machine model.
The TPIC6C596 is characterized for operation over the operating case temperature range of −40°C to 125°C.
logic diagram (positive logic)
G 8
10
RCK
7
CLR
SRCK
SER IN
15
2
3
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
C1
D
C2
CLR
CLR
D
D
C2
CLR
C1
CLR
4
5
6
11
12
13
14
16
D
C1
9
CLR
2
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SER OUT
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
GND
SLIS093C − MARCH 2000 − REVISED APRIL 2005
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
VCC
DRAIN
33 V
Input
25 V
20 V
12 V
GND
GND
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)†
Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 250 mA
Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ
Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE
TC ≤ 25°C
POWER RATING
D
1087 mW
8.7 mW/°C
217 mW
N
1470 mW
11.7 mW/°C
294 mW
PW
1372 mW
10.976 mW/°C
274 mW
DERATING FACTOR
ABOVE TC = 25°C
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TC = 125°C
POWER RATING
3
SLIS093C − MARCH 2000 − REVISED APRIL 2005
recommended operating conditions
Logic supply voltage, VCC
High-level input voltage, VIH
MIN
MAX
UNIT
4.5
5.5
V
0.85 VCC
Low-level input voltage, VIL
V
0.15 VCC
V
250
mA
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (see Notes 3 and 5 and Figure 11)
Setup time, SER IN high before SRCK↑, tsu (see Figure 2)
15
ns
Hold time, SER IN high after SRCK↑, th (see Figure 2)
15
ns
Pulse duration, tw (see Figure 2)
40
Operating case temperature, TC
−40
ns
°C
125
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ − TC to 10°C maximum.
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER
V(BR)DSX
VSD
TEST CONDITIONS
Drain-to-source breakdown voltage
Source-to-drain diode forward voltage
ID = 1 mA
IF = 100 mA
MIN
33
TYP
MAX
37
0.85
V
1.2
VOH
High-level output voltage, SER OUT
IOH = − 20 µA,
IOH = − 4 mA,
VOL
Low-level output voltage, SER OUT
IOL = 20 µA,
IOL = 4 mA,
VCC = 4.5 V
VCC = 4.5 V
IIH
IIL
High-level input current
Low-level input current
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC
VI = 0
All outputs off
20
200
ICC
Logic supply current
VCC = 5.5 V
All outputs on
150
500
ICC(FRQ)
Logic supply current at frequency
fSRCK = 5 MHz,
All outputs off,
CL = 30 pF,
See Figures 2 and 6
1.2
5
IN
Nominal current
VDS(on) = 0.5 V,
TC = 85°C,
VDS = 30 V,
IN = ID,
See Notes 5, 6 and 7
90
IDSX
Off-state drain current
VDS = 30 V,
TC = 125°C
VCC = 4.5 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 5.5 V,
ID = 50 mA,
VCC = 4.5 V
rDS(on)
Static drain-source on-state resistance
ID = 50 mA,
TC = 125°C,
VCC = 4.5 V
See Notes 5 and 6
and Figures 7 and 8
ID = 100 mA,
VCC = 4.5 V
4.4
4.49
4
4.2
UNIT
V
V
0.005
0.1
0.3
0.5
V
1
µA
−1
µA
µA
A
mA
mA
0.1
0.2
0.15
0.3
6.5
9
9.9
12
6.8
10
µA
Ω
NOTES: 5. Technique should limit TJ − TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
4
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output from G
tr
tf
Rise time, drain output
Propagation delay time, high-to-low-level output from G
MIN
TYP
CL = 30 pF,
ID = 75 mA,
See Figures 1, 2, and 9
tpd
Propagation delay time, SRCK↓ to SEROUT
f(SRCK)
Serial clock frequency
CL = 30 pF,
See Note 8
ta
trr
Reverse-recovery-current rise time
ID = 75 mA,
ID = 75 mA,
ns
50
ns
100
ns
80
ns
15
ns
10
MHz
100
IF = 100 mA,
di/dt = 10 A/µs,
See Notes 5 and 6 and Figure 3
Reverse-recovery time
UNIT
80
Fall time, drain output
CL = 30 pF,
See Figure 2
MAX
ns
120
NOTES: 5. Technique should limit TJ − TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
D package
RθJA
UNIT
115
N package
Thermal resistance, junction-to-ambient
MAX
85
All 8 outputs with equal power
PW package
°C/W
C/W
108
PARAMETER MEASUREMENT INFORMATION
5V
15 V
7
1
7
15
Word
Generator
(see Note A)
2
10
8
CLR
SRCK
5
4
3
2
1
0
DRAIN
3 −6,
11 −14
Output
G
0V
5V
SER IN
CL = 30 pF
(see Note B)
RCK
5V
G
RL = 200 Ω
DUT
5V
0V
ID
VCC
SER IN
6
SRCK
0V
5V
RCK
0V
5V
CLR
0V
GND
16
15 V
DRAIN1
0.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
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5
SLIS093C − MARCH 2000 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
5V
G
50%
50%
0V
5V
15 V
tPLH
1
7
15
Word
Generator
(see Note A)
2
10
8
Output
VCC
CLR
SRCK
ID
3 −6,
11 −14
DUT
24 V
90%
10%
10%
RL = 200 Ω
tr
Output
0.5 V
tf
SWITCHING TIMES
5V
CL = 30 pF
(see Note B)
RCK
G
90%
DRAIN
SER IN
tPHL
50%
SRCK
0V
GND
tsu
th
16
5V
SER IN
50%
50%
TEST CIRCUIT
0V
tw
INPUT SETUP AND HOLD WAVEFORMS
SRCK
50%
50%
tpd
SER OUT
50%
tpd
50%
SER OUT PROPAGATION DELAY WAVEFORM
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION
TP K
DRAIN
Circuit
Under
Test
0.1 A
2500 µF
250 V
di/dt = 10 A/µs
+
L = 0.85 mH
IF
(see Note A)
IF
15 V
−
0
TP A
25% of IRM
t2
t1
t3
Driver
IRM
RG
VGG
(see Note B)
ta
50 Ω
trr
TEST CIRCUIT
CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 10 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
5V
15 V
tw
1
7
CLR
VCC
30 Ω
Word
Generator
(see Note A)
2
10
8
DUT
3 −6,
11 −14
DRAIN
RCK
See Note B
1.5 H
SER IN
G
5V
Input
ID
15 SRCK
tav
0V
IAS = 200 mA
ID
VDS
GND
V(BR)DSX = 33 V
MIN
VDS
16
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
VOLTAGE AND CURRENT WAVEFORMS
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 200 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
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7
SLIS093C − MARCH 2000 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
SUPPLY CURRENT
vs
FREQUENCY
6
1
VCC = 5 V
TC = −40C° to 125°C
ICC − Supply Current − mA
5
0.1
0.01
0.1
rDS(on) − Drain-to-Source On-State Resistance − Ω
4
3
2
1
1
0
0.1
10
10
100
f − Frequency − MHz
Figure 5
Figure 6
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
STATIC
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
30
VCC = 5 V
See Note A
25
TC = 125°C
20
15
10
TC = 25°C
5
TC = − 40°C
0
50
70
90
110
130
150
170
190
210
250
12
ID = 50 mA
See Note A
TC = 125°C
10
8
TC = 25°C
6
4
TC = − 40°C
2
0
4.0
4.5
5.0
5.5
6.0
6.5
ID − Drain Current − mA
VCC − Logic Supply Voltage − V
Figure 7
Figure 8
NOTE A: Technique should limit TJ − TC to 10°C maximum.
8
1
tav − Time Duration of Avalanche − ms
rDS(on) − Static Drain-to-Source On-State Resistance − Ω
IAS − Peak Avalanche Current − A
TC = 25°C
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7.0
SLIS093C − MARCH 2000 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
SWITCHING TIME
vs
CASE TEMPERATURE
140
ID = 75 mA
See Note A
tr
Switching Time − ns
120
100
tf
80
tPLH
60
tPHL
40
20
0
−50
−25
0
25
50
75
100
125
TC − Case Temperature − °C
Figure 9
NOTE A: Technique should limit TJ − TC to 10°C maximum.
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
10
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.25
VCC = 5 V
0.20
0.15
TC = 25°C
0.10
TC = 100°C
TC = 125°C
0.05
0.00
1
2
3
4
5
6
7
8
ID − Maximum Peak Drain Current of Each Output − A
ID − Maximum Continuous Drain Current of Each Output − A
THERMAL INFORMATION
0.30
d = 10%
0.25
d = 20%
0.20
d = 50%
0.15
d = 80%
0.10
VCC = 5 V
TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
0.05
0.00
1
2
3
4
5
6
7
8
N − Number of Outputs Conducting Simultaneously
N − Number of Outputs Conducting Simultaneously
Figure 10
Figure 11
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THERMAL INFORMATION
D PACKAGE†
NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.01
0.1
tw − Pulse Duration − s
1
10
† Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 12
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11
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPIC6C596D
ACTIVE
SOIC
D
16
40
TBD
CU NIPDAU
Level-1-220C-UNLIM
TPIC6C596DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
TPIC6C596DR
ACTIVE
SOIC
D
16
2500
CU NIPDAU
Level-1-220C-UNLIM
TPIC6C596DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC6C596DRQ1
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC6C596N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPIC6C596PW
ACTIVE
TSSOP
PW
16
90
TBD
CU NIPDAU
Level-1-220C-UNLIM
TPIC6C596PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPIC6C596PWR
ACTIVE
TSSOP
PW
16
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
TPIC6C596PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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