SLRS013A − MAY 1988 − REVISED NOVEMBER 1989 • • • • • • • • • • NE PACKAGE (TOP VIEW) 1.3-A Current Capability Each Channel Saturating Outputs With Low On-State Resistance Two Inverting and Two Noninverting Driver Channels With Common Active-Low Enable Input Key Application Is as a Complete Full-Step 4-Phase DC Stepper Motor Driver Using Only Three Directly Connected Logic Control Signal Lines From Standard Microprocessors High-Impedance Inputs Compatible With TTL or CMOS Levels Very Low Standby Power . . . 10 mW Typ 50-V Noninductive Switching Voltage Capability 40-V Inductive Switching Voltage Capability Output Clamp Diodes for Inductive Transient Protection 2-W Power Package 1Y 1, 2D 2Y HEAT SINK AND GND 1 16 2 15 3 14 4 13 5 12 3Y 3, 4D 4Y 6 11 7 10 8 9 1A 2A G HEAT SINK AND GND VCC 3A 4A logic symbol† G 1A 2A 3A description The SN75439 quadruple peripheral driver is designed for use in systems requiring high current, high voltage, and high load power. The device features two inverting and two noninverting open-collector outputs with a common-enable input that, when taken high, disables all four outputs. By pairing each inverting channel with a corresponding noninverting channel (such as channel 1 paired with channel 2 and channel 3 paired with channel 4), the device may be used as a complete full-step 4-phase dc stepper-motor driver using only two input logic control signals plus the enable signal, as shown in Figure 3. Other applications include driving relays, lamps, solenoids, motors, LEDs, transmission lines, hammers, and other high-power-demand loads. 4A 14 EN 1 16 CLAMP 3 15 2 6 10 8 9 7 1Y 2Y 1, 2D 3Y 4Y 3, 4D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC publication 617-12. Function Tables EACH CHANNEL 1 OR CHANNEL 4 DRIVER INPUTS A G OUTPUT Y H L X L X H L H H H = high level, L = low level EACH CHANNEL 2 OR CHANNEL 3 DRIVER INPUTS A G OUTPUT Y L H X L X H L H H X = irrelevant The SN75439 is characterized for operation from 0°C to 70°C. Copyright 1989, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 3−1 SLRS013A − MAY 1988 − REVISED NOVEMBER 1989 logic diagram (positive logic) G 1A schematics of inputs and outputs 14 16 1 2 2A 3A 15 10 3 6 7 4A 9 8 4,5,12,13 EQUIVALENT OF EACH INPUT 1Y VCC 1,2D TYPICAL OF ALL OUTPUTS Clamp Output 2Y Input 3Y GND 3,4D 4Y GND absolute maximum ratings over operating temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 52 V Output voltage, VO (inductive load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 V Output clamp-diode terminal voltage range, VOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 52 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 mA Peak sink output current, IOM (nonrepetitive, tw ≤ 0.1 ms) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A (repetitive, tw ≤ 10 ms, duty cycle ≤ 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A Continuous sink output current, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 A Peak output clamp diode current, IOKM (nonrepetitive, tw ≤ 0.1 ms) (see Note 2) . . . . . . . . . . . . . . . . . . 1.5 A (repetitive, tw ≤ 10 ms, duty cycle ≤ 50%) . . . . . . . . . . . . . . . . . . 1.3 A Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3) . . . . . . . . . . . . . . 2075 mW Continuous total dissipation at (or below) 65°C case temperature (see Note 3) . . . . . . . . . . . . . . . . 5000 mW Operating case or virtual junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. All voltage values are with respect to the network GND (unless otherwise specified). 2. All four channels of this device may conduct rated current simultaneously; however, power dissipation average over a short time interval must fall within the continuous dissipation range. 3. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mW/°C. For operation above 65°C case temperature, derate linearly at the rate of 59 mW/°C. To avoid exceeding the design maximum virtual junction temperature, these ratings should not be exceeded. 3−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SLRS013A − MAY 1988 − REVISED NOVEMBER 1989 recommended operating conditions Supply voltage, VCC MIN NOM MAX UNIT 4.75 5 5.25 V Output supply voltage in inductive switching circuit, VS (see Figure 2) High-level input voltage, VIH 2 −0.3† Low-level input voltage, VIL Low-level output current, IOL 40 V 5.25 V 0.8 V 1.3 A Operating free-air temperature, TA 0 25 70 °C † The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels. electrical characteristics over recommended ranges of operating free-air temperature and supply voltages (unless otherwise noted) PARAMETER VIK VOL VF(K) Input clamp voltage IOL = 1 A IOL = 1.3 A IIL IR(K) Low-level input current See Note 4 IF = 0.5 A IF = 1 A IF = 1.3 A Output clamp-diode forward voltage High-level output current MIN II = − 12 mA IOL = 0.5 A Low-level output voltage IOH IIH ICC TEST CONDITIONS See Note 4 VOH = 50 V, VI = VIH High-level input current Output clamp-diode reverse current (at Y output) MAX UNIT −0.9 −1.5 V 0.2 0.35 0.4 0.7 0.5 0.9 1.1 1.9 1.3 2.2 1.4 2.4 VOK = 50 V VI = 0 to 0.8 V VR = 50 V, VO = 0 All outputs at high level (off) All outputs at low level (on) Supply current TYP† Two outputs at high level (off) and two outputs at low level (on) V V 100 µA 10 µA −10 µA 100 µA 2 8 140 200 70 110 TYP MAX mA † All typical values are at VCC = 5 V, TA = 25°C. NOTE 4: These parameters must be measured using pulse techniques, tw = 1 ms, duty cycle ≤ 10%. switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tTLH tTHL Transition time, low-to-high-level output VOH Propagation delay time, high-to-low-level output IOL ≈ 1 A, RL = 30 Ω,, CL = 30 pF, See Figure 1 VS = 40 V, RL = 31 Ω, IO ≈ 1.3 A, See Figure 2 MIN Transition time, high-to-low-level output High-level output voltage (after switching inductive load) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • VS − 100 UNIT 1500 ns 100 ns 170 ns 50 ns mV 3−3 SLRS013A − MAY 1988 − REVISED NOVEMBER 1989 PARAMETER MEASUREMENT INFORMATION Input 5V VCC Input Under Test Pulse Generator (see Note A) 30 V Open D RL = 30 Ω Channel Under Test Y Output CL = 30 pF (see Note C) Other Input (see Note B) GND SUB TEST CIRCUIT ≤ 10 ns ≤ 10 ns 3V 90% Input (2A, 3A, G) 90% 1.5 V 1.5 V 10% 10% 0V ≤ 10 ns ≤ 10 ns 3V 90% Input (1A, 4A) 90% 1.5 V 10% 1.5 V 10% 5 µs 0V tPHL tPLH 90% Output 90% 50% VOH 50% 10% 10% tTHL tTLH VOL VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: duty cycle ≤ 1 %, ZO = 50 Ω. B. Enable input G is at 0 V if input A is used as the switching input. When G is used as the switching input, the corresponding A input is at 0 V if testing channel 2 or channel 3 or at 3 V if testing channel 1 or channel 4. C. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms, Switching Characteristics 3−4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SLRS013A − MAY 1988 − REVISED NOVEMBER 1989 PARAMETER MEASUREMENT INFORMATION VS = 40 V Input 5V VCC Pulse Generator (see Note A) A 0.4 V 2 mH D RL = 31 Ω Channel Under Test Y Output G CL = 30 pF (see Note B) SUB GND TEST CIRCUIT ≤ 10 ns ≤ 10 ns 3V 90% Input (2A, 3A) 90% 1.5 V 1.5 V 10% 10% 0V 400 µs ≤ 10 ns ≤ 10 ns 3V 90% Input (1A, 4A) 90% 1.5 V 1.5 V 10% 10% 0V VOH Output VOL VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: duty cycle ≤ 1 %, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Output Latch-Up Test Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3−5 SLRS013A − MAY 1988 − REVISED NOVEMBER 1989 APPLICATION INFORMATION VS SN75439 DM DN Data Lines From Microprocessor G 14 1A 16 2A 15 3A 10 DK 4A 9 1 1Y 2 1,2D 3 2Y 6 3Y 7 3,4D 8 4Y 4, 5, 12, 13 GND Waveforms DN DK Figure 3. Full-Step Four-Phase Stepper-Motor Driver 3−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Four-Phase Stepper Motor PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN75439NE OBSOLETE PDIP NE Pins Package Eco Plan (2) Qty 16 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI003 – OCTOBER 1994 NE (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 20 PIN SHOWN 0.070 (1,78) MAX 11 20 PINS ** DIM A C 1 20 0.914 (23,22) MIN MAX B 16 0.780 (19,80) 0.975 (24,77) MIN 0.930 (23,62) MAX 1.000 (25,40) 10 C MIN 0.240 (6,10) 0.260 (6,61) MAX 0.260 (6,60) 0.280 (7,11) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN B 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 4040054 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (16 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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