SCLS394G − APRIL 1998 − REVISED DECEMBER 2004
D 2-V to 5.5-V VCC Operation
D Max tpd of 9 ns at 5 V
D Typical VOLP (Output Ground Bounce)
D
D
D
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
SN54LV132A . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
VCC
4B
D
SN54LV132A . . . J OR W PACKAGE
SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
1Y
NC
2A
NC
2B
The
’LV132A
devices
are
quadruple
positive-NAND gates designed for 2-V to 5.5-V
VCC operation.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
The ’LV132A devices perform the Boolean
function Y = A • B or Y = A + B in positive logic.
4
Each circuit functions as a NAND gate, but
because of the Schmitt action, it has different input
threshold levels for positive- and negative-going
signals.
NC − No internal connection
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube of 25
SN74LV132AD
Reel of 2500
SN74LV132ADR
SOP − NS
Reel of 2000
SN74LV132ANSR
74LV132A
SSOP − DB
Reel of 2000
SN74LV132ADBR
LV132A
Tube of 90
SN74LV132APW
Reel of 2000
SN74LV132APWR
Reel of 250
SN74LV132APWT
TVSOP − DGV
Reel of 2000
SN74LV132ADGVR
LV132A
CDIP − J
Tube of 25
SNJ54LV132AJ
SNJ54LV132AJ
CFP − W
Tube of 150
SNJ54LV132AW
SNJ54LV132AW
SOIC − D
−40°C to 85°C
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV132A
LV132A
LCCC - FK
Tube of 55
SNJ54LV132AFK
SNJ54LV132AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(&. *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &/( '*$%&' ('!(*! 0(**('1.
*"!$#"' +*"#&'2 !"& '" '&#&(*-1 '#-$!& &'2 ") (-+(*(%&&*.
POST OFFICE BOX 655303
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1
SCLS394G − APRIL 1998 − REVISED DECEMBER 2004
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
logic diagram (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS394G − APRIL 1998 − REVISED DECEMBER 2004
recommended operating conditions (see Note 4)
SN54LV132A
SN74LV132A
MIN
MAX
MIN
MAX
UNIT
VCC
VI
Supply voltage
2
5.5
2
5.5
V
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
−50
0
VCC
−50
µA
IOH
IOL
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level output current
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
V
−2
−6
−6
−12
−12
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
6
12
12
mA
µA
mA
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV132A
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
SN74LV132A
MAX
MIN
TYP
MAX
VT+
Positive-going
input threshold voltage
2.5 V
1.75
1.75
3.3 V
2.31
2.31
5V
3.5
3.5
VT−
Negative-going
input threshold voltage
2.5 V
0.75
0.75
3.3 V
0.99
0.99
5V
1.5
1.5
2.5 V
0.25
1
0.25
1
3.3 V
0.33
1.32
0.33
1.32
5V
0.5
2
0.5
2
∆VT
Hysteresis (VT+ − VT−)
VOH
VOL
IOH = −50 µA
IOH = −2 mA
2 V to 5.5 V
IOH = −6 mA
IOH = −12 mA
IOL = 50 µA
IOL = 2 mA
VI = 5.5 V or GND
VI = VCC or GND,
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
VCC − 0.1
2
VCC − 0.1
2
3V
2.48
2.48
4.5 V
3.8
IO = 0
V
V
V
V
3.8
2 V to 5.5 V
IOL = 6 mA
IOL = 12 mA
II
ICC
2.3 V
UNIT
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
0.55
0.55
V
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
5
µA
0
3.3 V
5
1.9
1.9
pF
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS394G − APRIL 1998 − REVISED DECEMBER 2004
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A or B
Y
CL = 15 pF
7.9*
tpd
A or B
Y
CL = 50 pF
10.8
MIN
free-air
temperature
SN54LV132A
range,
SN74LV132A
UNIT
MIN
MAX
MIN
MAX
16.5*
1*
18.5*
1
18.5
ns
20.2
1
23
1
23
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
free-air
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
MAX
tpd
A or B
Y
CL = 15 pF
5.6*
tpd
A or B
Y
CL = 50 pF
7.6
temperature
SN54LV132A
range,
SN74LV132A
UNIT
MIN
MAX
MIN
MAX
11.9*
1*
14*
1
14
ns
15.4
1
17.5
1
17.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tpd
A or B
Y
CL = 15 pF
3.9*
tpd
A or B
Y
CL = 50 pF
5.3
MIN
free-air
temperature
SN54LV132A
range,
SN74LV132A
UNIT
MIN
MAX
MIN
MAX
7.7*
1*
9*
1
9
ns
9.7
1
11
1
11
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV132A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.21
0.8
V
Quiet output, minimum dynamic VOL
−0.09
−0.8
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
3.12
High-level dynamic input voltage
V
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
11.2
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 10 MHz
7.5
pF
SCLS394G − APRIL 1998 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLZ
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
50% VCC
tPZL
tPHL
tPHL
Out-of-Phase
Output
0V
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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