TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 1.6 MHz, 3-V TO 6-V INPUT, 3-A SYNCHRONOUS STEP-DOWN SWIFT™ CONVERTER FEATURES • • • • • • • • • DESCRIPTION 60-mΩ MOSFET Switches for High Efficiency at 3-A Continuous Output Current Adjustable Output Voltage Down to 0.9 V With 1% Accuracy Switching Frequency: Adjustable From 280 kHz to 1600 kHz Externally Compensated for Design Flexibility Fast Transient Response Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost Spacing Saving 4mm x 5mm QFN Packaging For SWIFT Documentation, Application Notes, and Design Software, see the TI website at www.ti.com/swift APPLICATIONS • • • As members of the SWIFT™ family of dc/dc regulators, the TPS54317 low-input-voltage high-output-current synchronous-buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that provides high performance under transient conditions; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. The TPS54317 device is available in a thermally enhanced 24-pin QFN (RHF) PowerPAD™ package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in achieving high-performance power supply designs to meet aggressive equipment development cycles. Low-Voltage, High-Density Systems With Power Distributed at 5 V or 3.3 V Point of Load Regulation for High Performance DSPs, FPGAs, ASICs, and Microprocessors Broadband, Networking and Optical Communications Infrastructure EFFICIENCY vs LOAD CURRENT Simplified Schematic Input VIN TPS54317 100 Output PH 95 BOOT 85 PWRGD SYNC RT VBIAS AGND 90 PGND VSENSE COMP Efficiency − % SS/ENA 80 75 70 65 o TA = 25 C, VI = 3.3 V, VO = 1.8 V, fs = 1.1 MHz 60 55 50 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current − A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TJ OUTPUT VOLTAGE PACKAGE PART NUMBER –40°C to 125°C Adjustable Down to 0.9 V QFN (RHF) (1) (2) TPS54317RHF For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The RHF package is available in two different tape and reel quantities. Add an R suffix to the device type (i.e. TPS54317RHFR) for a 3000 piece reel and add a T suffix (TPS54317RHFT) for a 250 piece reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VI VO Input voltage range Output voltage range VALUE UNIT VIN, SS/ENA, SYNC –0.3 to 7 V RT –0.3 to 6 V VSENSE –0.3 to 4 V BOOT –0.3 to 17 V VBIAS, PWRGD, COMP –0.3 to 7 V PH (steady state) –0.6 to 10 V –2 to 10 V PH (transient < 20 ns) IO Output current range Sink current PH Internally Limited COMP, VBIAS 6 PH 6 A COMP 6 mA 10 mA ±0.3 V SS/ENA, PWRGD Voltage differential AGND to PGND Continuous power dissipation mA See Power Dissipation Rating Table TJ Operating virtual junction temperature range –40 to 150 °C Tstg Storage temperature –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VI Input voltage range TJ Operating junction temperature 2 Submit Documentation Feedback NOM MAX UNIT 3 6 V –40 125 °C TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 PACKAGE DISSIPATION RATINGS (1) (2) (1) (2) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT THERMAL IMPEDANCE JUNCTION-TO-CASE 24-Pin RHF with solder 19.7°C/W 1.7°C/W Maximum power dissipation may be limited by overcurrent protection. Test board conditions: • 3 inch x 3 inch, 4 layers, thickness: 0.062 inch • 2 oz. copper traces located on the top of the PCB • 2 oz. copper ground plane on the bottom of the PCB • 2 oz. copper ground planes on the 2 internal layers • 6 thermal vias (see the Recommended land pattern, Figure 12) ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN VI Input voltage range, VIN Quiescent current 3 6 fs = 350 kHz, SYNC = 0.8 V, RT open 6.2 9.6 fs = 550 kHz, SYNC ≥ 2.5 V, RT open, phase pin open 8.4 12.8 1 1.4 2.95 3 Shutdown, SS/ENA = 0 V V mA UNDERVOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO Hysteresis voltage, UVLO V 2.7 2.8 0.14 0.16 V 2.5 µs Rising and falling edge deglitch, UVLO (1) BIAS VOLTAGE VO Output voltage, VBIAS Output current, VBIAS I(VBIAS) = 0 2.7 2.8 (2) 2.9 V 100 µA 0.900 V CUMULATIVE REFERENCE Vref Accuracy 0.882 0.891 REGULATION Line regulation (1) (3) Load regulation (1) (3) IL = 1.5 A, fs = 1.1 MHz, TJ = 25°C 0.04 %/V IL = 0 A to 3 A, fs = 1.1 MHz, TJ = 25°C 0.09 %/A OSCILLATOR Internally set free-running frequency range Externally set free-running frequency range SYNC ≤ 0.8 V, RT open 280 350 420 SYNC ≥ 2.5 V, RT open 440 550 660 RT = 100 kΩ (1% resistor to AGND) 460 500 540 RT = 43 kΩ (1% resistor to AGND) 995 1075 1155 High-level threshold voltage, SYNC 2.5 0.8 50 Frequency range, SYNC 330 Ramp valley (1) kHz V V 150 Maximum duty cycle (1) (2) (3) 1600 1 Minimum controllable on time V ns 0.75 Ramp amplitude (peak-to-peak) (1) kHz V Low-level threshold voltage, SYNC Pulse duration, SYNC (1) kHz ns 90% Specified by design Static resistive loads only Specified by the circuit used in Figure 10. Submit Documentation Feedback 3 TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1 kΩ COMP to AGND (4) 90 110 Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (4) 3 5 Error amplifier common-mode input voltage range Powered by internal LDO (4) 0 IIB Input bias current, VSENSE VSENSE = Vref VO Output voltage slew rate (symmetric), COMP 60 1 dB MHz VBIAS V 250 nA 1.4 V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) 10 mV overdrive (4) 70 85 ns 1.2 1.4 V SLOW-START/ENABLE Enable threshold voltage, SS/ENA Enable hysteresis voltage, SS/ENA Falling edge deglitch, SS/ENA 0.82 (4) (4) Internal slow-start time 2.6 Charge current, SS/ENA SS/ENA = 0 V Discharge current, SS/ENA SS/ENA = 0.2 V, VI = 2.7 V 0.03 V 2.5 µs 3.35 4.1 ms 3 5 8 µA 1.5 2.3 4 mA POWER GOOD Power good threshold voltage VSENSE falling Power good hysteresis voltage (4) Power good falling edge deglitch (4) 90 %Vref 3 %Vref 35 Output saturation voltage, PWRGD I(sink) = 2.5 mA Leakage current, PWRGD VI = 5.5 V 0.18 µs 0.3 V 1 µA CURRENT LIMIT Current limit trip point VI = 3 V, output shorted (4) 4 6.5 VI = 6 V, output shorted (4) 4.5 7.5 A Current limit leading edge blanking time (4) 100 ns (4) 200 ns Current limit total response time THERMAL SHUTDOWN Thermal shutdown trip point (4) Thermal shutdown hysteresis 135 (4) 150 165 °C °C 10 OUTPUT POWER MOSFETS rDS(on) (4) 4 Power MOSFET switches VI = 6 V 59 88 VI = 3 V 85 136 Specified by design Submit Documentation Feedback mΩ TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 PIN ASSIGNMENTS COMP PWRGD BOOT PH PH PH PH RHF PACKAGE (BOTTOM VIEW) 1 2 3 4 5 6 7 8 PH 9 PH 10 NC 21 11 PGND 20 12 PGND SYNC 19 18 17 16 15 14 13 PGND NC PGND 22 VIN RT Exposed Thermal Pad (Pin 25) VIN 23 VIN AGND VBIAS 24 SS/ENA VSNS TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. COMP 1 Error amplifier output. Connect compensation network from COMP to VSENSE. PWRGD 2 Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active. BOOT 3 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. PH 4-9 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor. PGND 11-14 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. VIN 15-17 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor. VBIAS 18 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor. SS/ENA 19 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. SYNC 20 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. RT 22 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. AGND 23, 25 VSNS 24 NC 10, 21 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Make PowerPAD connection to AGND. Error amplifier inverting input. Not connected internally. Submit Documentation Feedback 5 TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN Enable Comparator SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V VIN ILIM Comparator Thermal Shutdown o 150 C 2.5 ms REG VBIAS SHUTDOWN 3V−6V Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT 59 mW 2.5 ms SS_DIS SHUTDOWN PH Internal/External Slow-start (Internal Slow-start iTme = 3.35 ms + − R Q Error Amplifier Reference VREF = 0.891 V S PWM Comparator LOUT CO Adaptive Dead-Time and Control Logic VIN 59 mW OSC PGND Powergood Comparator PWRGD VSENSE Falling Edge Deglitch 0.90 Vref TPS54317 Hysteresis: 0.03 Vref VSENSE COMP RT SHUTDOWN 35 ms SYNC ADDITIONAL 3-A SWIFT DEVICES DEVICE OUTPUT VOLTAGE DEVICE TPS54310 Adjustable TPS54372 DDR/Adjustable TPS54380 Sequencing/Adjustable TPS54373 Prebias/Adjustable RELATED DC/DC PRODUCTS • • • 6 TPS40007 – dc/dc controller PTH0407W – 3-A plug-in module UC282-ADJ – 3-A low dropout regulator Submit Documentation Feedback OUTPUT VOLTAGE VO TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VI = 3.3 V 100 80 60 40 20 0 0 −40 25 85 125 VI = 5 V 80 60 40 20 0 −40 85 125 SYNC ≥ 2.5 V 550 450 SYNC ≤ 0.8 V 350 250 −40 0 25 85 Figure 3. EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE VOLTAGE REFERENCE vs JUNCTION TEMPERATURE RT = 43 kW 1150 1100 1050 1000 −40 0 25 85 125 0.895 600 RT = 100 kW Vref − Voltage Reference − V 1200 550 500 450 400 −40 25 85 0.891 0.889 0.887 0.885 −40 125 0 25 85 TJ − Junction Temperature − °C Figure 4. Figure 5. Figure 6. ERROR AMPLIFIER OPEN LOOP RESPONSE INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE DEVICE POWER LOSSES vs LOAD CURRENT o 0 −40 −60 80 Phase −80 −100 60 −120 40 Gain 20 −140 −160 0 −180 −20 −200 10 k 100 k 1 M 10 M 100 1k f − Frequency − Hz Figure 7. 1.2 3.65 1 Device Power Losses − W 100 Internal Slow-Start Time − ms 120 3.80 3.50 3.35 3.20 3.05 o 0.8 0.6 0.4 0.2 2.90 2.75 −40 125 TA = 25 C, fs = 700 kHz, VI = 5 V, VO = 3.3 V −20 Phase − Degrees RL= 10 kΩ, CL = 160 pF, TA = 25°C 10 0 0.893 TJ − Junction Temperature − C o 140 125 TJ − Junction Temperature − °C Figure 2. f − Externally Set Oscillator Frequency − kHz f − Externally Set Oscillator Frequency − kHz 25 650 Figure 1. TJ − Junction Temperature − C Gain − dB 0 750 TJ − Junction Temperature − °C TJ − Junction Temperature − °C 0 f − Internally Set Oscillator Frequency −kHz 100 Drain-Source On-State Resistance − mW Drain-Source On-State Resistance − mW 120 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 0 25 85 TJ − Junction Temperature − °C Figure 8. Submit Documentation Feedback 125 0 0 0.5 1.5 2.5 1 2 IO − Output Current − A 3 Figure 9. 7 TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 APPLICATION INFORMATION Figure 10 shows the schematic diagram for a typical TPS54317 application. The TPS54317 (U1) provides up to 3 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the power pad underneath the TPS54317 integrated circuit needs to be soldered well to the printed circuit board. R5 C8 442 W 2200 pF 1 + C1 150 mF 2 C7 150 pF R3 6.81 kW R1 R2 9.76 kW 10 kW C6 3300 pF U1 TPS54317 24 23 R4 41.2 kW 22 21 20 19 18 17 C5 C4 0.1 mF 16 15 14 13 C9 10 mF VSNS COMP AGND PWRGD RT BOOT NC PH SYNC PH SS/EN PH VBIAS PH VIN PH VIN PH VIN NC R6 10 kW 1 2 3 4 5 PWRGD C3 0.047 mF L1 1.5 mH 6 7 VOUT 8 9 C2 100 mF 10 C10 100 mF C11 1000 pF 11 PGND 12 PGND PGND PGND PwPd Open Figure 10. TPS54317 Schematic R(W) = INPUT VOLTAGE The input to the circuit is a nominal 3.3 VDC, applied at J1. The optional input filter (C1) is a 150-µF capacitor, with a maximum allowable ripple current of 3 A. C9 is the decoupling capacitor for the TPS54317 and must be located as close to the device as possible. 51 k - 4.7 k ƒ (MHz) (1) OUTPUT FILTER The output filter is composed of a 1.5-µH inductor and two capacitors. The inductor is a low dc resistance (0.017 Ω) type, Coilcraft DO1813P-122HC. The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz. FEEDBACK CIRCUIT The resistor divider network of R1 and R2 sets the output voltage for the circuit at 1.8 V. R1, along with R5, R3, C5, C7, and C8 forms the loop compensation network for the circuit. For this design, a Type 3 topology is used. OPERATING FREQUENCY In the application circuit, the 1.1-MHz operation is selected. Connecting a 41.2-kΩ between RT (pin 22) and analog ground can be used to set the switching frequency from 280 kHz to 1.6 MHz. To calculate the RT resistor, use the Equation 1: 8 PCB LAYOUT Figure 11 shows a generalized PCB layout guide for the TPS54317. The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54317 ground pins. The minimum recommended bypass capacitance is 10-µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins. Submit Documentation Feedback TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 The TPS54317 has two internal grounds (analog and power). Inside the TPS54317, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54317, particularly at higher output currents. Ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground traces are recommended. There should be an area of ground on the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the ground area under the device as shown. The only components that should tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54317. Use a separate wide trace for the analog ground signal path. This analog ground should be used for the voltage set point divider, timing resistor RT, slow start capacitor and bias capacitor grounds. Connect this trace directly to AGND (pin 1). The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching node, inductor should be located very close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, LO, CO and PGND as small as practical. Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC package and the device pinout, they must be routed close, but maintain as much separation as possible while still keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. The bias capacitor should be as close as possible to the VBIAS pin and analog ground . If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency, connect them to this trace. TOPSIDE GROUND AREA INPUT BYPASS CAPACITOR PH PGND VOUT PH PGND PH EXPOSED PowerPAD AREA VIN Vin BOOT CAPACITOR PH VIN PH VIN BOOT VBIAS PWRGD SS/ENA COMP COMPENSATION NETWORK AGND VSENSE RT NC SYNC BIAS CAPACITOR OUTPUT FILTER CAPACITOR OUTPUT INDUCTOR PH NC PGND PH PGND INPUT BULK FILTER SLOW START CAPACITOR FREQUENCY SET RESISTOR ANALOG GROUND TRACE VIA to Ground Plane Figure 11. TPS54317 PCB Layout Submit Documentation Feedback 9 TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area additional vias located under the device package may be added to enhance thermal performance. The vias under the package, but not in the exposed thermal pad area, can be increased in size to 0.018. 0.1250 0.0400 0.0400 6 x 0.013 DIA 0.0400 0.0900 PIN 1 0.0788 0.1220 EXPOSED POWERPAD AREA 24 x 0.0320 0.0197 24 x 0.0120 0.1182 0.1620 Figure 12. Recommended Land Pattern for 24-Pin QFN PowerPAD 10 Submit Documentation Feedback TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 PERFORMANCE GRAPHS TA = 25°C, fs = 1.1 MHz, VI = 3.3 V, VO = 1.8 V (unless otherwise specified) EFFICIENCY vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 0.3 180 60 50 VI = 4 V 90 85 VI = 5 V 80 0.1 0 -0.1 1 60 20 10 GAIN 0 0 −10 −60 −20 −30 −40 −120 −50 -0.3 0.5 120 30 -0.2 VI = 6 V 75 0 40 Gain − dB Output Regulation − % Efficiency − % 0.2 VI = 3 V 95 Phase Phase − Degrees 100 LOOP RESPONSE 1.5 2 2.5 3 3.5 0 0.5 1.5 1 2 2.5 3 −60 10 100 −180 1M 100 k f − Frequency − Hz IO − Output Current − A IO − Output Current − A 10 k 1k Figure 13. Figure 14. Figure 15. OUTPUT RIPPLE VOLTAGE LOAD TRANSIENT RESPONSE SLOW-START TIMING VO = 20 mV/div (AC Coupled) VO = 10 mV/div (AC Coupled) VI = 1 V/div VO = 1 V/div PH = 2 V/div IO = 1 A/div 0.75 A to 2.25 A / step 1 ms / div 500 ns / div Figure 16. Figure 17. Figure 18. AMBIENT TEMPERATURE vs LOAD CURRENT INPUT RIPPLE VOLTAGE LINE REGULATION vs INPUT VOLTAGE 0.3 VI = 50 mV/div (AC Coupled) 120 110 100 90 80 Safe Operating Area † 70 60 50 PH = 2 V/div fs = 700 kHz VI = 5 V VO = 3.3 V o TJ = 125 C 40 30 20 10 0 0 0.5 1 IO = 1.5 A 0.2 Output Regulation − % T A − Ambient Temperature − ° C 130 IO = 3 A 0.1 IO = 0 A 0 -0.1 -0.2 1.5 2 2.5 3 IL − Load Current − A † 500 ms / div -0.3 500 ns / div Figure 19. 3 5 4 6 VI − Input Voltage − V Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this data sheet. Figure 20. Submit Documentation Feedback Figure 21. 11 TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 VBIAS Regulator (VBIAS) DETAILED DESCRIPTION Undervoltage Lock Out (UVLO) The TPS54317 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. Slow-Start/Enable (SS/ENA) The slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: 1.2 V td C (SS) 5 A (2) Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: 0.7 V t C (SS) (SS) 5 A (3) Voltage Reference The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high precision regulation of the TPS54317, since it cancels offset errors in the scale and error amplifier circuits. Oscillator and PWM Ramp The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a static digital input. If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 kHz to 1600 kHz by connecting a resistor to the RT pin to ground and floating the SYNC pin. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: SWITCHING FREQUENCY (MHz) = (4) External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 1600 kHz by driving a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets the free-running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency selection configurations. The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal rate. 12 51 k R(W) + 4.7 k Submit Documentation Feedback TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 Table 1. Summary of the Frequency Selection Configurations SWITCHING FREQUENCY SYNC PIN RT PIN 350 kHz, internally set Float or AGND Float 550 kHz, internally set ≥ 2.5 V Float Externally set 280 kHz to 1600 kHz Float R = 27.4 k to 180 k Externally synchronized frequency Synchronization signal R = RT value for 80% of external synchronization frequency Error Amplifier The high performance, wide bandwidth, voltage error amplifier sets the TPS54317 apart from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3 compensation can be employed using external compensation components. PWM Control Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn off the high-side FET and turns on the low-side FET. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the pwm latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54317 is capable of sinking current continuously until the CO reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor, and consequently, the output current. This process is repeated each cycle in which the current limit comparator is tripped. Dead-Time Control and MOSFET Drivers Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver does not turn on until the gate drive voltage to the low-side FET is below 2 V. The low-side driver does not turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers are designed with a 300-mA source and sink capability to drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. Overcurrent Protection The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and differential amplifier, and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false tripping of the current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. Submit Documentation Feedback 13 TPS54317 www.ti.com SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 VOmax = 0.9 x VImin - IOmax [ (-0.016 x VImin + 0.184) + RL] Thermal Shutdown The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to 10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault, and then shutting down upon reaching the thermal shutdown point. Where: VImin = minimum input voltage IOmax = maximum load current RL = series resistance of the output inductor Equation 5 assumes maximum on resistance for the internal high-side and low-side FETs. The lower limit is constrained by the minimum controllable on time which may be as high as 150 ns. The approximate minimum output voltage for a given input voltage, operating frequency, and minimum load current is given in Equation 6: VOmin = (150E-9 x VImax x Fs x 1.08) - Iomin x Power Good (PWRGD) The power good circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold, SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise. OUTPUT VOLTAGE LIMITATIONS Due to the internal design of the TPS54317, there are both upper and lower output voltage limits for any given input voltage. Additionally, the lower boundary of the output voltage set point range is also dependent on operating frequency. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 90% and is given by Equation 5: 14 (5) [( ) -0.026 X Vimax + 0.111 + RL 3 ] (6) Where: VI = maximum input voltage Fs = programmed operating frequency IO = minimum load current RL = series resistance of the output inductor Equation 6 assumes nominal on resistance for the high-side and low-side FETs, and has an eight percent factor for variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checked to assure proper functionality. Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS54317RHFR ACTIVE QFN RHF 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54317RHFRG4 ACTIVE QFN RHF 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54317RHFT ACTIVE QFN RHF 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54317RHFTG4 ACTIVE QFN RHF 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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