KMM374S403CT PC100 SDRAM MODULE Revision History Revision .0 (Feb. 1998) - Input leakage Currents (Inputs / DQ) of Component level are changed. I IL(Inputs) : ± 5uA to ± 1uA, I IL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV. Revision .1 (Mar. 1998) •AC Operating Condition is changed as defined : - V IH(max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. V IL(min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE KMM374S403CT SDRAM DIMM 4Mx72 SDRAM DIMM with ECC based on 2Mx8, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM374S403CT is a 4M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM374S403CT consists of eighteen CMOS 2M x 8 bit Synchronous DRAMs in TSOP-II 400mil package and a 1K or 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parellel for each SDRAM. The KMM374S403CT is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Performance range • • • • • • • • Max Freq. (Speed) KMM374S403CT-G8 125MHz (8ns) KMM374S403CT-GH 100MHz (10ns) KMM374S403CT-GL 100MHz (10ns) Burst Mode Operation Auto & Self Refresh Capability (4096 cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst Length (1, 2, 4, 8 & Full page) Data Scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial Presence Detect with EEPROM PCB : Height(1,250mil), double sided component PIN NAMES PIN CONFIGURATIONS (Front Side / Back Side) Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 V DD DQ14 DQ15 CB0 CB1 VSS NC NC V DD WE DQM0 Front 29 DQM1 CS0 30 31 DU 32 V SS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10/AP 39 *BA1 40 VDD 41 VDD 42 CLK0 43 V SS 44 DU 45 CS2 46 DQM2 47 DQM3 48 DU 49 VDD 50 NC 51 NC 52 CB2 53 CB3 54 V SS 55 DQ16 56 DQ17 Pin Front Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VDD DQ20 NC *V REF CKE1 V SS DQ21 DQ22 DQ23 V SS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 V SS CLK2 NC WP **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 V DD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 V DD DQ46 DQ47 CB4 CB5 VSS NC NC V DD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 *A11 V DD CLK1 *A12 VSS CKE0 CS3 DQM6 DQM7 *A13 V DD NC NC CB6 CB7 VSS DQ48 DQ49 Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 V DD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 V DD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 V DD Pin Name Function A0 ~ A10/AP Address Input (multiplexed) BA0 Select Bank DQ0 ~ DQ63 Data Input / Output CB0 ~ 7 Check Bit (data-in / data-out) CLK0 ~ CLK3 Clock Input CKE0 ~ CKE1 Clock Enable Input CS0 ~ CS3 Chip Select Input RAS Row Address Storbe CAS Column Address Strobe WE Write Enable DQM0 ~ 7 DQM V DD Power Supply (3.3V) V SS Ground *V REF Power Supply for Reference SDA Serial Data I/O SCL Serial Clock SA0 ~ 2 Address in EEPROM WP Write Protection DU Don′t use NC No Connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. A0 ~ A10/AP Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA8 BA0 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data Input/Output Mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data Input/Output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. WP Write Protection VDD /V SS Power Supply/Ground RAS low. CAS low. WP pin is connected to V CC . When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write - protected. Power and ground for the input buffers and the core logic. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 • • DQM4 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U9 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS3 CS2 DQM2 • DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM5 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U10 CS DQM6 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 DQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 CAS SDRAM U0 ~ U17 WE SDRAM U0 ~ U17 CKE0 CS DQM7 • U12 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U6 Vss • U8 U17 CS U13 Serial PD SCL V DD SDA A0 A1 A2 SA0 SA1 SA2 • WP 47Ω 10KΩ CKE1 • SDRAM U9 ~ U17 • 10Ω • • CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1/U3/U0/U4 U6/U7/U5/U8 • Every DQpin of SDRAM Two 0.1uF Capacitors per each SDRAM U16 DQM CS U10/U12/U9/U13 10Ω • CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CLK0/1/2/3 VDD U15 DQM CS DQM SDRAM U0 ~ U8 DQn CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • SDRAM U0 ~ U17 RAS DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SDRAM U0 ~ U17 A0 ~ An, BA0 U14 • DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 • CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 DQM U11 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS • • • DQM CS 3.3pF *1 • U15/U16/U14/U17 • U2/U11 To all SDRAMs *1 : For 4 loads, CLK2 & CLK3 only. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN , V OUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss V DD , V DDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 18 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter SS = 0V, T A = 0 to 70 °C) Symbol Min Typ Max Unit VDD , VDDQ 3.0 3.3 3.6 V Input logic high votlage V IH 2.0 3.0 VDDQ +0.3 V 1 Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage Supply voltage Note VOL - - 0.4 V IOL = 2mA Input leakage current(Inputs) IIL -18 - 18 uA 3 Input leakage current (I/O pins) IIL -3 - 3 uA 3,4 Note : 1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ V DDQ . Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV) Pin Symbol Min Max Unit Address (A0 ~ A10/AP, BA0) C ADD 65 95 pF RAS, CAS, WE CIN 65 95 pF CKE (CKE0) CCKE 40 60 pF Clock (CLK0, CLK2) C CLK 30 40 pF CS (CS0, CS2) CCS 30 40 pF DQM (DQM0 ~ DQM7) C DQM 15 25 pF DQ (DQ0 ~ DQ63) COUT1 10 20 pF CB (CB0 ~ CB7) COUT2 10 20 pF REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T Parameter Operating Current (One Bank Active) Symbol ICC1 A = 0 to 70 °C) Test Condition CAS Latency Burst Length =1 t RC ≥tRC (min) I OL = 0 mA Version -8 -H -L 1,035 990 990 Unit Note mA 1 ICC2 P CKE≤VIL (max), t CC = 15ns 18 ICC2 PS CKE & CLK ≤VIL (max), t CC = ∞ 18 ICC2 N CKE≥VIH (min), CS≥V IH (min), t CC = 15ns Input signals are changed one time during 30ns 270 ICC2 NS CKE≥VIH (min), CLK ≤VIL (max), t CC = ∞ Input signals are stable 72 Active Standby Current in power-down mode ICC3 P CKE≤VIL (max), t CC = 15ns 36 ICC3 PS CKE & CLK ≤VIL (max), t CC = ∞ 18 Active Standby Current in non power-down mode (One Bank Active) ICC3 N CKE≥VIH (min), CS≥V IH (min), t CC = 15ns Input signals are changed one time during 30ns 450 mA ICC3 NS CKE≥VIH (min), CLK ≤VIL (max), t CC = ∞ Input signals are stable 270 mA Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode I OL = 0 mA Page Burst 2Banks Activated t CCD = 2CLKs Operating Current (Burst Mode) ICC4 Refresh Current ICC5 tRC ≥tRC (min) Self Refresh Current ICC6 CKE≤0.2V mA mA mA 3 1,215 1,110 1,110 2 990 1,110 990 mA 1 990 mA 2 18 mA Note : 1. Measured with outputs open. 2. Refresh period is 64ms. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70 °C) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4 / 0.4 V 1.4 V tr / tf = 1 / 1 ns 1.4 V See Fig. 2 3.3V Vtt=1.4V 1200Ω • Output 50Ω VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, I OL = 2mA • • Z0=50 Ω Output 50pF 870Ω 50pF • (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -8 -H -L Unit Note Row active to row active delay t RRD(min) 16 20 20 ns 1 RAS to CAS delay t RCD(min) 20 20 20 ns 1 Row precharge time t RP(min) 20 20 20 ns 1 t RAS(min) 48 50 50 ns 1 Row active time t RAS(max) Row cycle time t RC(min) Last data in to row precharge t RDL(min) Last data in to new col. address delay t CDL(min) Last data in to burst stop Col. address to col. address delay Number of valid output data 100 68 70 us ns 1 1 CLK 2 1 CLK 2 t BDL(min) 1 CLK 2 t CCD(min) 1 CLK 3 ea 4 CAS Latency=3 2 CAS Latency=2 1 70 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Refer to the individual componenet, not the whole module. Parameter -8 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 Output data hold time CAS Latency=3 8 -H Max 1000 12 tSAC CAS Latency=2 tOH CAS Latency=2 Min 10 -L Max 1000 10 Min 10 Unit Note ns 1 ns 1, 2 ns 2 Max 1000 12 6 6 6 6 6 7 3 3 3 3 3 3 CLK high pulse width tCH 3 3 3 ns 3 CLK low pulse width tCL 3 3 3 ns 3 Input setup time tSS 2 2 2 ns 3 Input hold time tSH 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 tSHZ 6 6 6 6 6 7 ns Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE KMM374S403CT-G8 (Unit : number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns 125MHz (8.0ns) 3 9 6 3 2 3 1 1 1 100MHz (10.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 4 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 6 4 2 2 2 1 1 1 Frequency KMM374S403CT-GH (Unit : number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (10.0ns) 2 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 Frequency KMM374S403CT-GL (Unit : number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (10.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 Frequency REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Write & Column Address CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X Entry Self Refresh Exit Auto Precharge Disable H BA0 A10/AP L H L H H H H X X X X H X L L H H X V H X L H L H X V H X L H L L X H X L H H L X H X L L H L X V Auto Precharge Enable Entry H L H L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V 3 Row Address L Column Address (A 0~A 8) Column Address (A 0~A 8) H Both Banks Exit 3 3 L Entry 1, 2 X Auto Precharge Disable Clock Suspend or Active Power Down Note 3 H Bank Selection A9 ~ A0 L Auto Precharge Enable Burst Stop Precharge CKEn H Bank Active & Row Addr. Read & Column Address CKEn-1 X V L X H 4 4, 5 4 4, 5 6 X X X X X Precharge Power Down Mode X Exit L DQM H No Operation Command H H X X H X X X L H H H X V X X X 7 (V=Valid, X=Don ′t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A 0 ~ A 10 /AP, BA 0 : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA 0 : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A 10 /AP is "High" at row precharge, BA 0 is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 1 Mar. '98 KMM374S403CT PC100 SDRAM MODULE PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.175 (4.45) 0.157 ± 0.004 (4.000 ± 0.100 ) 0.700 (17.780) 0.118 (3.000) B A .118DIA ± .004 (3.000DIA ± .100) 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.100Min (2.540Min) 1.375 (34.925) 0.387 ± 0.062 (9.84 ± 1.59) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.200 Min (5.08 Min) 0.150Max (3.81Max) 0.100 Min 0.250 (6.350 ) 0.250 (6.350 ) 0.123 ± .005 (3.125 ± .125) 0.079 ± .004 (2.000 ± .100) Detail A (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± .002 (1.000 ± .050) 0.123 ± .005 (3.125 ± .125) 0.079 ± .004 (2.000 ± .100) Detail B 0.010Max (0.250 Max) 0.050 (1.270 ) Detail C Tolerances : ± .005(.13) unless otherwise specified The used device is 2Mx8 SDRAM, TSOP SDRAM Part No. : KM48S2020CT REV. 1 Mar. '98