Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 M464S3323BN0 SDRAM SODIMM 32Mx64 SDRAM SODIMM based on sTSOP2 16Mx8, 4Banks, 4K Refresh, 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung M464S3323BN0 is a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S3323BN0 consists of sixteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in sTSOP2 package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S3323BN0 is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Performance range Part No. M464S3323BN0 - C1H/L1H M464S3323BN0 - C1L/L1L • • • • • Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,250mil), double sided component PIN CONFIGURATIONS (Front side/back side) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front Pin VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin Front 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 DQ14 DQ15 VSS NC NC Pin Back Pin DQ46 95 DQ47 97 VSS 99 NC 101 NC 103 105 107 Voltage Key 109 CLK0 62 CKE0 111 VDD VDD 113 64 RAS 66 CAS 115 68 CKE1 117 WE 70 *A12 119 CS0 72 *A13 121 CS1 74 CLK1 123 DU 76 VSS VSS 125 78 NC NC 127 80 NC NC 129 82 VDD VDD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 92 VSS VSS 141 DQ20 94 DQ52 143 52 54 56 58 60 Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD Max Freq. (Speed) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3) PIN NAMES Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK1 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground SDA Serial data I/O SCL Serial clock DU Don′t use NC No connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK0~1 System clock Active on the positive going edge to sample all inputs. CS0~1 Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE0~1 Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 • DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 • • DQM4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U0 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U8 DQM5 U1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U9 DQM6 U2 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U10 • DQM3 DQM7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS U3 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U11 A0 ~ An, BA0 & 1 SDRAM U0 ~ U15 RAS, CAS, WE SDRAM U0 ~ U15 CKE0 SDRAM U0 ~ U7 CKE1 SDRAM U8 ~ U15 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 CS U12 • DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 U13 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U6 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U14 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U7 U15 Serial PD SCL A0 A1 A2 SDA 10Ω DQn Every DQpin of SDRAM • VDD Vss • • • • Two 0.1uF Capacitors per each SDRAM CLK0/1 To all SDRAMs U0/U1/U8/U9 U4/U5/U12/U13 • • U2/U3/U10/U11 U6/U7/U14/U15 Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 16 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) CAPACITANCE Pin Address (A0 ~ A11, BA0 ~ BA1) RAS, CAS, WE Symbol Min Max Unit CADD 40 80 pF CIN 40 80 pF CKE (CKE0 ~ CKE1) CCKE 20 40 pF Clock (CLK0 ~ CLK1) CCLK 20 32 pF CS (CS0 ~ CS1) CCS 20 40 pF DQM (DQM0 ~ DQM7) CDQM 5 10 pF DQ (DQ0 ~ DQ63) COUT 8 13 pF Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Version Test Condition -1H Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICC3P ICC3PS ICC3N ICC3NS Burst length = 1 tRC ≥ tRC(min) IO = 0 mA Unit Note mA 1 -1L 1,120 CKE ≤ VIL(max), tCC = 10ns 16 CKE & CLK ≤ VIL(max), tCC = ∞ 16 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 320 mA mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 112 CKE ≤ VIL(max), tCC = 10ns 80 CKE & CLK ≤ VIL(max), tCC = ∞ 80 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 480 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 320 mA 1,240 mA 1 1,920 mA 2 C 24 mA L 12.8 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 CKE ≤ 0.2V Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) mA Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω • Output 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA • Output Z0 = 50Ω 50pF 50pF 870Ω • • (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -1H Unit Note -1L Row active to row active delay tRRD(min) 20 ns 1 RAS to CAS delay tRCD(min) 20 ns 1 tRP(min) 20 ns 1 tRAS(min) 50 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2,5 Last data in to Active delay tDAL(min) 2 CLK + 20 ns - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Row precharge time Row active time Number of valid output data CAS latency=3 2 CAS latency=2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns. Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter -1H Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 10 -1L Max 1000 10 tSAC CAS latency=2 tOH CAS latency=2 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 6 6 6 7 3 3 3 3 CLK high pulse width tCH 3 3 ns 3 CLK low pulse width tCL 3 3 ns 3 Input setup time tSS 2 2 ns 3 Input hold time tSH 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 6 6 6 7 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. ns Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh Write & column address CS RAS CAS WE DQM H X L L L L X OP code L L L H X X Entry Self refresh Exit Auto precharge disable H BA0,1 Auto precharge disable L H L H H H H X X X X Entry X L L H H X V H X L H L H X V 3 X L H L L L Column address (A0 ~ A9) X V L Column address (A0 ~ A9) H H X L H H L X H X L L H L X H L L H Entry H L Precharge power down mode L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Exit Exit 1,2 X H H Note 3 All banks Clock suspend or active power down A11, A 9 ~ A0 3 Auto precharge enable Bank selection A10/AP L Auto precharge enable Burst stop Precharge CKEn H Bank active & row addr. Read & column address CKEn-1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Shrink-TSOP 144pin SDRAM SODIMM M464S3323BN0 PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.66 (67.56) 2.50 (63.60) 1 59 61 0.91 (23.20) 0.13 (3.30) 143 1.25 2-φ 0.07 (1.80) 1.29 (32.80) 0.18 (4.60) 0.083 (2.10) 0.10 (2.50) 0.79 (20.00) 0.24 (6.0) 0.16 ± 0.039 (4.00 ± 0.10) (31.75) 2-R 0.078 Min (2.00 Min) Z Y 0.15 (3.70) 60 62 144 0.10 Min 0.157 Min (4.00 Min) 0.125 Min (3.20 Min) 0.150 Max (3.80 Max) 0.04 ± 0.0039 (1.00 ± 0.10) 0.16 ± 0.0039 (4.00 ± 0.10) 0.06 ± 0.0039 (1.50 ± 0.1) Detail Z Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx8 SDRAM, sTSOP2 SDRAM Part No. : K4S280832B-N (2.54 Min) 2 0.024 ± 0.001 (0.60 ± 0.05) 0.008 ± 0.006 (0.20 ± 0.15) 0.03 TYP (0.80 TYP) Detail Y