SPANSION LV033MU

Am29LV033MU
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not available for designs. For new and current designs,
S29GL032A supersedes Am29LV033MU and is the factory-recommended migration path. Please
refer to the S29GL032A datasheet for specifications and ordering information. Availability of this
document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 26519
Revision B
Amendment 4
Issue Date September 12, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV033MU
32 Megabit (4 M x 8-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
This product has been retired and is not available for designs. For new and current designs, S29GL032A supersedes Am29LV033M and is the factory-recommended migration path. Please
refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
„ Single power supply operation
— 3 volt read, erase, and program operations
„ VersatileI/O™ control
— Device generates and tolerates data voltages on CE#
and DQ inputs/outputs as determined by the voltage
on the VIO pin; operates from 1.65 to 3.6 V
„ Manufactured on 0.23 µm MirrorBit process
technology
„ SecSi™ (Secured Silicon) Sector region
— 256-byte sector for permanent, secure identification
through an 16-byte random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
„ Flexible sector architecture
— Sixty-four 64 Kbyte sectors
„ Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
„ Minimum 100,000 erase cycle guarantee per sector
„ 20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
„ High performance
— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 7.5 µs typical write buffer byte programming time:
32-byte write buffer reduces overall programming
time for multiple-byte updates
— 8-byte read page buffer
— 32-byte write buffer
„ Low power consumption (typical values at 3.0 V,
5 MHz)
— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
„ Package options
— 40-pin TSOP
— 48-ball FBGA
SOFTWARE & HARDWARE FEATURES
„ Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
„ Hardware features
— Sector Group Protection: hardware method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— ACC (high voltage) pin accelerates programming
time for higher throughput during system production
— Hardware reset pin (RESET#) resets device
— Ready/Busy# pin (RY/BY#) detects program or erase
cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 26519
Rev: B Amendment/4
Issue Date: September 12, 2006
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29LV033MU is a 32 Mbit, 3.0 volt single power
supply flash memory devices organized as 4,194,304
bytes. The device has an 8-bit wide data bus, and can
be programmed either in the host system or in standard EPROM programmers.
The device is available with an access time of 90, 100,
110, or 120 ns. Note that each device has a specific
operating voltage range (V CC ) and an I/O voltage
range (VIO), as specified in the Product Selector Guide
and the Ordering Information sections. The device is
offered in a 40-pin TSOP or 48-ball FBGA package.
Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a V CC input, a high-voltage accelerated program
(ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write
cycles to program data instead of four.
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the VIO pin.
Refer to the Ordering Information section for valid VIO
options.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The SecSi™ (Secured Silicon) Sector provides a 256
byte area for code or data that can be permanently
protected. Once this sector is protected, no further
changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates
2
Am29LV033MU
September 12, 2006
D A T A
S H E E T
MIRRORBIT 32 MBIT DEVICE FAMILY
Device
Bus
Sector Architecture
Packages
VIO
RY/BY#
WP#, ACC
WP# Protection
x8
Uniform (64 Kbyte)
40-pin TSOP (std. & rev. pinout),
48-ball FBGA
Yes
Yes
ACC only
No WP#
LV320MT/B
x8/x16
Boot (8 x 8 Kbyte
at top & bottom)
48-pin TSOP, 48-ball Fine-pitch BGA,
64-ball Fortified BGA
No
Yes
WP#/ACC pin
2 x 8 Kbyte
top or bottom
LV320MH/L
x8/x16
Uniform (64 Kbyte)
56-pin TSOP (std. & rev. pinout),
64-ball Fortified BGA
Yes
Yes
WP#/ACC pin
1 x 64 Kbyte
high or low
LV033MU
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com→Flash Memory→Product Information→MirrorBit→Flash Information→Technical Documentation.
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
September 12, 2006
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
AMD MirrorBit™ White Paper
Am29LV033MU
3
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Command Definitions ............................................................. 32
Table 10. Command Definitions...................................................... 32
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 33
DQ7: Data# Polling ................................................................. 33
Figure 8. Data# Polling Algorithm .................................................. 33
RY/BY#: Ready/Busy#............................................................ 34
DQ6: Toggle Bit I .................................................................... 34
Table 1. Device Bus Operations .....................................................10
Figure 9. Toggle Bit Algorithm........................................................ 35
VersatileIO™ (VIO) Control ..................................................... 10
Requirements for Reading Array Data ................................... 10
Page Mode Read .................................................................... 11
Writing Commands/Command Sequences ............................ 11
Write Buffer ............................................................................. 11
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
DQ2: Toggle Bit II ................................................................... 35
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 36
DQ3: Sector Erase Timer ....................................................... 36
DQ1: Write-to-Buffer Abort ..................................................... 36
Table 2. Sector Address Table ........................................................13
Autoselect Mode..................................................................... 15
Table 3. Autoselect Codes, (High Voltage Method) .......................15
Sector Group Protection and Unprotection ............................. 16
Table 4. Sector Group Protection/Unprotection Address Table .....16
Temporary Sector Group Unprotect ....................................... 17
Figure 1. Temporary Sector Group Unprotect Operation................ 17
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18
SecSi (Secured Silicon) Sector Flash Memory Region .......... 19
Table 5. SecSi Sector Contents ......................................................19
Figure 3. SecSi Sector Protect Verify.............................................. 20
Hardware Data Protection ...................................................... 20
Low VCC Write Inhibit ............................................................ 20
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Common Flash Memory Interface (CFI) . . . . . . . 20
Table 6. CFI Query Identification String .............................. 21
Table 7. System Interface String......................................................21
Table 8. Device Geometry Definition................................... 22
Table 9. Primary Vendor-Specific Extended Query............. 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24
Byte Program Command Sequence ....................................... 24
Unlock Bypass Command Sequence ..................................... 25
Write Buffer Programming ...................................................... 25
Accelerated Program .............................................................. 26
Figure 4. Write Buffer Programming Operation............................... 27
Figure 5. Program Operation .......................................................... 28
Program Suspend/Program Resume Command Sequence ... 28
Figure 6. Program Suspend/Program Resume............................... 29
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Table 11. Write Operation Status ................................................... 36
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 37
Figure 10. Maximum Negative Overshoot Waveform ................... 37
Figure 11. Maximum Positive Overshoot Waveform..................... 37
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Test Setup.................................................................... 39
Table 12. Test Specifications ......................................................... 39
Key to Switching Waveforms. . . . . . . . . . . . . . . . 39
Figure 13. Input Waveforms and
Measurement Levels...................................................................... 39
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
Read-Only Operations ........................................................... 40
Figure 14. Read Operation Timings ............................................... 40
Figure 15. Page Read Timings ...................................................... 41
Hardware Reset (RESET#) .................................................... 42
Figure 16. Reset Timings ............................................................... 42
Erase and Program Operations .............................................. 43
Figure 17. Program Operation Timings..........................................
Figure 18. Accelerated Program Timing Diagram..........................
Figure 19. Chip/Sector Erase Operation Timings ..........................
Figure 20. Data# Polling Timings
(During Embedded Algorithms)......................................................
Figure 21. Toggle Bit Timings
(During Embedded Algorithms)......................................................
Figure 22. DQ2 vs. DQ6.................................................................
44
44
45
46
47
47
Temporary Sector Unprotect .................................................. 48
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 48
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 49
Alternate CE# Controlled Erase and Program Operations ..... 50
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 51
Erase And Programming Performance. . . . . . . . 52
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 52
TSOP Pin and BGA Package Capacitance . . . . . 52
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54
TS 040—40-Pin Standard Thin Small Outline Package ......... 54
TSR040—40-Pin Reverse Thin Small Outline Package ......... 55
FBC048—48-Ball Fine-Pitch Ball Grid Array
9 x 8 mm Package .................................................................. 56
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 7. Erase Operation............................................................... 30
Erase Suspend/Erase Resume Commands ........................... 31
4
Am29LV033MU
September 12, 2006
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Part Number
Speed
Option
Am29LV033MU
VCC = 3.0–3.6 V
90R
101R
112R
(VIO = 3.0–3.6 V) (VIO = 2.7–3.6 V) (VIO =1.65–3.6 V)
VCC = 2.7–3.6 V
101
(VIO = 2.7–3.6 V)
120R
(VIO =1.65–3.6 V)
112
(VIO =1.65–3.6 V)
120
(VIO =1.65–3.6 V)
Max. Access Time (ns)
90
100
110
120
Max. CE# Access Time (ns)
90
100
110
120
Max. Page access time (tPACC)
25
30
30
40
30
40
Max. OE# Access Time (ns)
25
30
30
40
30
40
Note:
1. See “AC Characteristics” for full specifications.
2. For the Am29LV033MU device, the last numeric digit in the speed option (e.g. 90R, 101, 112, 120) is used for internal purposes
only. Please use OPNs as listed when placing orders.
BLOCK DIAGRAM
DQ0–DQ7
RY/BY#
VCC
Sector Switches
VSS
VIO
Erase Voltage
Generator
RESET#
WE#
Input/Output
Buffers
State
Control
ACC
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
A21–A0
September 12, 2006
Timer
Address Latch
STB
Am29LV033MU
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
5
D A T A
S H E E T
CONNECTION DIAGRAMS
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VIO
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Standard TSOP
40-Pin Reverse TSOP
Am29LV033MU
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VIO
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
September 12, 2006
D A T A
S H E E T
CONNECTION DIAGRAMS
48-Ball FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A14
A13
A15
A16
A17
NC
A20
VSS
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A11
A12
A19
A10
D6
D7
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
D5
NC
VCC
D4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
ACC
NC
NC
D2
D3
VIO
A21
A2
B2
C2
D2
E2
F2
G2
H2
A7
A18
A6
A5
D0
NC
NC
D1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
September 12, 2006
and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C
for prolonged periods of time.
Am29LV033MU
7
D A T A
PIN DESCRIPTION
A21–A0
= 22 Address inputs
DQ7–DQ0
= 8 Data inputs/outputs
CE#
= Chip Enable input
OE#
= Output Enable input
WE#
= Write Enable input
ACC
= Acceleration input
RESET#
= Hardware Reset Pin input
RY/BY#
= Ready/Busy output
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
S H E E T
LOGIC SYMBOL
22
A21–A0
CE#
8
DQ7–DQ0
OE#
WE#
VIO
= Output Buffer power
VSS
= Device Ground
NC
= Pin Not Connected Internally
8
ACC
RESET#
RY/BY#
VIO
Am29LV033MU
September 12, 2006
D A T A
S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV033M
U
90R
WM
I
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE TYPE
E
= 40-Pin Standard Pinout Thin Small Outline Package (TS 040)
F
= 40-Pin Reverse Pinout Thin Small Outline Package (TSR040)
WC = 48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 9 x 8 mm package (FBC048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE
U
= Uniform sector device
DEVICE NUMBER/DESCRIPTION
Am29LV033MU
32 Megabit (4 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory with VersatileIO™ Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP Package
Speed
(ns)
VIO
Range
VCC
Range
Am29LV033MU90R
90
3.0–3.6 V
3.0–3.6 V
Am29LV033MU101
100
2.7–3.6 V
110
1.65–3.6 V
120
1.65–3.6 V
Am29LV033MU101R
100
2.7–3.6 V
Am29LV033MU112R
110
1.65–3.6 V
Am29LV033MU120R
120
1.65–3.6 V
Am29LV033MU112
Am29LV033MU120
EI, FI
Valid Combinations for
Fine-Pitch BGA Package
Order Number
2.7–3.6 V
3.0–3.6 V
Package
Marking
Speed
(ns)
VIO
Range
VCC
Range
3.0–
3.6 V
Am29LV033MU90R
L033MU90R
90
3.0–
3.6 V
Am29LV033MU101
L033MU01V
100
2.7–
3.6 V
Am29LV033MU112
L033MU11V
110
1.65–
3.6 V
Am29LV033MU120
WCI L033MU12V
120
1.65–
3.6 V
I
Am29LV033MU101R
L033MU01R
100
2.7–
3.6 V
Am29LV033MU112R
L033MU11R
110
1.65–
3.6 V
Am29LV033MU120R
L033MU12R
120
1.65–
3.6 V
2.7–
3.6 V
3.0–
3.6 V
Valid Combinations
Valid Combinations list configurations planned to be supported in volume
for this device. Consult the local AMD sales office to confirm availability of
specific valid combinations and to check on newly released combinations.
Note:
For the Am29LV033MU device, the last numeric digit in the speed option
(e.g. 90R, 101, 112, 120) is used for internal purposes only. Please use
OPNs as listed when placing orders.
September 12, 2006
Am29LV033MU
9
D A T A
S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information
needed to execute the command. The contents of the
Table 1.
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Device Bus Operations
CE#
OE#
WE#
RESET#
ACC
Addresses
(Note 2)
DQ7–
DQ0
Read
L
L
H
H
X
AIN
DOUT
Write (Program/Erase)
L
H
L
H
X
AIN
(Note 3)
Accelerated Program
L
H
L
H
VHH
AIN
(Note 3)
VCC ±
0.3 V
X
X
VCC ±
0.3 V
H
X
High-Z
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Sector Group Protect (Note 2)
L
H
L
VID
X
SA, A6=L, A3=L,
A2=L, A1=H, A0=L
(Note 3)
Sector Group Unprotect
(Note 2)
L
H
L
VID
X
SA, A6=H, A3=L,
A2=L, A1=H, A0=L
(Note 3)
Temporary Sector Group
Unprotect
X
X
X
VID
X
AIN
(Note 3)
Operation
Standby
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A16.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO™ (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See Ordering Information
for VIO options on this device.
For example, a VI/O of 1.65–3.6 volts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
10
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. Refer
Am29LV033MU
September 12, 2006
D A T A
to the DC Characteristics table for the active current
specification for reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 bytes. The appropriate page is selected
by the higher address bits A(max)–A3. Address bits
A2–A0 determine the specific byte within a page. This
is an asynchronous operation; the microprocessor
supplies the specific byte location.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address
space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 32 bytes in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. See “Write
Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily intended to allow faster manufacturing throughput during system production.
September 12, 2006
S H E E T
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result. In addition, the ACC pin
must not be left floating or unconnected; inconsistent
behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires standard access time (t CE ) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Am29LV033MU
11
D A T A
S H E E T
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
memory, enabling the system to read the boot-up firmware from the Flash memory.
RESET#: Hardware Reset Pin
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t READY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current. If RESET# is held at VIL
but not within VSS±0.3 V, the standby current will be
greater.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
12
Am29LV033MU
September 12, 2006
D A T A
Table 2.
S H E E T
Sector Address Table
Sector
A21
A20
A19
A18
A17
A16
8-bit Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
000000–00FFFF
SA1
0
0
0
0
0
1
010000–01FFFF
SA2
0
0
0
0
1
0
020000–02FFFF
SA3
0
0
0
0
1
1
030000–03FFFF
SA4
0
0
0
1
0
0
040000–04FFFF
SA5
0
0
0
1
0
1
050000–05FFFF
SA6
0
0
0
1
1
0
060000–06FFFF
SA7
0
0
0
1
1
1
070000–07FFFF
SA8
0
0
1
0
0
0
080000–08FFFF
SA9
0
0
1
0
0
1
090000–09FFFF
SA10
0
0
1
0
1
0
0A0000–0AFFFF
SA11
0
0
1
0
1
1
0B0000–0BFFFF
SA12
0
0
1
1
0
0
0C0000–0CFFFF
SA13
0
0
1
1
0
1
0D0000–0DFFFF
SA14
0
0
1
1
1
0
0E0000–0EFFFF
SA15
0
0
1
1
1
1
0F0000–0FFFFF
SA16
0
1
0
0
0
0
100000–10FFFF
SA17
0
1
0
0
0
1
110000–11FFFF
SA18
0
1
0
0
1
0
120000–12FFFF
SA19
0
1
0
0
1
1
130000–13FFFF
SA20
0
1
0
1
0
0
140000–14FFFF
SA21
0
1
0
1
0
1
150000–15FFFF
SA22
0
1
0
1
1
0
160000–16FFFF
SA23
0
1
0
1
1
1
170000–17FFFF
SA24
0
1
1
0
0
0
180000–18FFFF
SA25
0
1
1
0
0
1
190000–19FFFF
SA26
0
1
1
0
1
0
1A0000–1AFFFF
SA27
0
1
1
0
1
1
1B0000–1BFFFF
SA28
0
1
1
1
0
0
1C0000–1CFFFF
SA29
0
1
1
1
0
1
1D0000–1DFFFF
SA30
0
1
1
1
1
0
1E0000–1EFFFF
SA31
0
1
1
1
1
1
1F0000–1FFFFF
SA32
1
0
0
0
0
0
200000–20FFFF
SA33
1
0
0
0
0
1
210000–21FFFF
September 12, 2006
Am29LV033MU
13
D A T A
Table 2.
S H E E T
Sector Address Table (Continued)
Sector
A21
A20
A19
A18
A17
A16
8-bit Address Range
(in hexadecimal)
SA34
1
0
0
0
1
0
220000–22FFFF
SA35
1
0
0
0
1
1
230000–23FFFF
SA36
1
0
0
1
0
0
240000–24FFFF
SA37
1
0
0
1
0
1
250000–25FFFF
SA38
1
0
0
1
1
0
260000–26FFFF
SA39
1
0
0
1
1
1
270000–27FFFF
SA40
1
0
1
0
0
0
280000–28FFFF
SA41
1
0
1
0
0
1
290000–29FFFF
SA42
1
0
1
0
1
0
2A0000–2AFFFF
SA43
1
0
1
0
1
1
2B0000–2BFFFF
SA44
1
0
1
1
0
0
2C0000–2CFFFF
SA45
1
0
1
1
0
1
2D0000–2DFFFF
SA46
1
0
1
1
1
0
2E0000–2EFFFF
SA47
1
0
1
1
1
1
2F0000–2FFFFF
SA48
1
1
0
0
0
0
300000–30FFFF
SA49
1
1
0
0
0
1
310000–31FFFF
SA50
1
1
0
0
1
0
320000–32FFFF
SA51
1
1
0
0
1
1
330000–33FFFF
SA52
1
1
0
1
0
0
340000–34FFFF
SA53
1
1
0
1
0
1
350000–35FFFF
SA54
1
1
0
1
1
0
360000–36FFFF
SA55
1
1
0
1
1
1
370000–37FFFF
SA56
1
1
1
0
0
0
380000–38FFFF
SA57
1
1
1
0
0
1
390000–39FFFF
SA58
1
1
1
0
1
0
3A0000–3AFFFF
SA59
1
1
1
0
1
1
3B0000–3BFFFF
SA60
1
1
1
1
0
0
3C0000–3CFFFF
SA61
1
1
1
1
0
1
3D0000–3DFFFF
SA62
1
1
1
1
1
0
3E0000–3EFFFF
SA63
1
1
1
1
1
1
3F0000–3FFFFF
Note: All sectors are 64 Kbytes in size.
14
Am29LV033MU
September 12, 2006
D A T A
S H E E T
Autoselect Mode
In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. Refer to the Autoselect Command Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 3.
Table 3.
Description
Device ID
Manufacturer ID: AMD
Autoselect Codes, (High Voltage Method)
CE#
OE#
WE#
A21
to
A15
A14
to
A10
A9
A8
to
A7
A6
A5
to
A4
A3
to
A2
A1
A0
DQ7 to DQ0
L
L
H
X
X
VID
X
L
X
L
L
L
01h
L
L
H
7Eh
L
L
H
X
X
VID
X
L
X
H
H
L
1Ch
H
H
H
00h
Cycle 1
Cycle 2
Cycle 3
Sector Protection
Verification
L
L
H
SA
X
VID
X
L
X
L
H
L
01h (protected),
00h (unprotected)
SecSi Sector Indicator Bit
(DQ7)
L
L
H
X
X
VID
X
L
X
L
H
H
90h (factory locked),
10h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
September 12, 2006
Am29LV033MU
15
D A T A
Sector Group Protection and
Unprotection
S H E E T
Table 4.
Sector Group Protection/Unprotection
Address Table
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
Sector Group
A22–A18
SA0–SA3
00000
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows
the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
SA4–SA7
00001
SA8–SA11
00010
SA12–SA15
00011
SA16–SA19
00100
SA20–SA23
00101
SA24–SA27
00110
SA28–SA31
00111
SA32–SA35
01000
SA36–SA39
01001
SA40–SA43
01010
SA44–SA47
01011
SA48–SA51
01100
SA52–SA55
01101
SA56–SA59
01110
SA60–SA63
01111
Note: All sector groups are 256 Kbytes in size.
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
16
Am29LV033MU
September 12, 2006
D A T A
S H E E T
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4).
START
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once
VID is removed from the RESET# pin, all the previously
protected sector groups are protected again. Figure 1
shows the algorithm, and Figure 23 shows the timing
diagrams, for this feature.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
September 12, 2006
Am29LV033MU
17
D A T A
S H E E T
START
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
No
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Group Unprotect
Mode
Yes
Yes
Set up sector
group address
No
All sector
groups
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Write 60h to sector
group address with
A6–A0 = 1xx0010
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Increment
PLSCNT
No
Reset
PLSCNT = 1
Read from
sector group address
with A6–A0
= 0xx0010
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6–A0 = 1xx0010
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with
A6–A0 = 1xx0010
Data = 01h?
Yes
No
Yes
Device failed
Protect
another
sector group?
Yes
PLSCNT
= 1000?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Group
Protect
Algorithm
Set up
next sector group
address
No
Data = 00h?
Yes
Last sector
group
verified?
No
Yes
Sector Group
Protect complete
Sector Group
Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Figure 2.
18
In-System Sector Group Protect/Unprotect Algorithms
Am29LV033MU
September 12, 2006
D A T A
S H E E T
SecSi (Secured Silicon) Sector Flash
Memory Region
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
Unless otherwise specified, the device is shipped such
that the customer may program and protect the
256-byte SecSi sector.
AMD offers the device with the SecSi Sector either
customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for
ordering information). The customer-lockable version
is shipped with the SecSi Sector unprotected, allowing
customers to program the sector after receiving the
device. The customer-lockable version also has the
SecSi Sector Indicator Bit permanently set to a “0.”
The factory-locked version is always protected when
shipped from the factory, and has the SecSi (Secured
Silicon) Sector Indicator Bit permanently set to a “1.”
Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC
function and unlock bypass modes are not available
when the SecSi Sector is enabled.
The SecSi sector address space in this device is allocated as follows:
Table 5.
SecSi Sector
Address Range
000000h–000007h
SecSi Sector Contents
Customer
Lockable
Determined by
customer
000008h–00007Fh
ESN Factory
Locked
ExpressFlash
Factory Locked
ESN
ESN or
determined by
customer
Unavailable
Determined by
customer
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0).
This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
September 12, 2006
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi Sector area can be protected using one of
the following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your local
AMD sales representative for details on ordering ESN
Factory Locked devices.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service (Express
Flash Factory Locked). The devices are then shipped
from AMD’s factory with the SecSi Sector permanently
locked. Contact an AMD representative for details on
using AMD’s ExpressFlash service.
Am29LV033MU
19
D A T A
S H E E T
.
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V CC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when V CC is
greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 3.
SecSi Sector Protect Verify
Power-Up Write Inhibit
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 6–9. To terminate reading CFI data,
the system must write the reset command.
20
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of
these documents.
Am29LV033MU
September 12, 2006
D A T A
Table 6.
S H E E T
CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h
Address for Alternate OEM Extended Table (00h = none exists)
Table 7.
System Interface String
Addresses
Data
1Bh
27h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
00h
VPP Min. voltage (00h = no VPP pin present)
1Eh
00h
VPP Max. voltage (00h = no VPP pin present)
1Fh
07h
Typical timeout per single byte write 2N µs
20h
07h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
0Ah
Typical timeout per individual block erase 2N ms
22h
00h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
01h
Max. timeout for byte write 2N times typical
24h
05h
Max. timeout for buffer write 2N times typical
25h
04h
Max. timeout per individual block erase 2N times typical
26h
00h
Max. timeout for full chip erase 2N times typical (00h = not supported)
September 12, 2006
Description
Am29LV033MU
21
D A T A
Table 8.
22
S H E E T
Device Geometry Definition
Addresses
Data
Description
27h
16h
Device Size = 2N byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
(00h not supported)
2Ah
2Bh
05h
00h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Dh
2Eh
2Fh
30h
3Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
00h
00h
00h
00h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
00h
00h
00h
00h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
Erase Block Region 4 Information (refer to CFI publication 100)
Am29LV033MU
September 12, 2006
D A T A
Table 9.
S H E E T
Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
31h
Major version number, ASCII
44h
33h
Minor version number, ASCII
45h
09h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
46h
02h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
04h
Sector Protect
0 = Not Supported, X = Number of sectors per group
48h
01h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
04h
Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah
00h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh
00h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
01h
Page Mode Type
00 = Not Supported, 01 = 8 Byte Page
4Dh
B5h
4Eh
C5h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh
00h
50h
01h
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the improper sequence may
place the device in an unknown state. A reset command is then required to return the device to reading
array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
September 12, 2006
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
Am29LV033MU
23
D A T A
non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See
the next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the device entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
24
S H E E T
Table 10 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the device is actively programming or erasing.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence:
■ A read cycle at address XX00h returns the manufacturer code.
■ Three read cycles at addresses 01h, 0Eh, and 0Fh
return the device code.
■ A read cycle to an address containing a sector
group address (SA), and the address 02h on A7–A0
returns 01h if the sector group is protected, or 00h
if it is unprotected. (Refer to Table 4 for valid sector
addresses).
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the device to normal operation. Table 10 shows the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash
Memory Region” for further information. Note that the
ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the byte program command
Am29LV033MU
September 12, 2006
D A T A
sequence. Note that the SecSi Sector, autoselect, and
CFI functions are unavailable when a program operation is in progress.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Note: Single byte programming is not supported in x8-mode.
Write buffer programming must be used during x8-mode
operation.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes to the device faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 10 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
S H E E T
Write Buffer Programming
Write buffer programming allows the system to write a
maximum of 32 bytes in one programming operation.
The effective programming time is faster than the standard programming algorithms. The write buffer programming command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle containing the Write Buffer Load command
written at the Sector Address in which programming
will occur. The fourth cycle writes the sector address
and the number of byte locations, minus one, to be
programmed. For example, if the system will program
6 unique address locations, then 05h should be written
to the device. This tells the device how many write
buffer addresses will be loaded with data and therefore
when to expect the Program Buffer to Flash command.
The number of locations to program cannot exceed
the size of the write buffer or the operation will abort.
The fifth cycle writes the first address location and
data to be programmed. A write-buffer-page is selected by address bits AMAX–A5. All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer. That
is, write buffer programming cannot occur across multiple write-buffer pages or sectors. If the system attempts to load programming data outside of the
selected write-buffer page, the operation will abort.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
s y s t e m m u s t t h e r e fo r e a c c o u n t fo r l o a d i n g a
write-buffer location more than once. The counter decrements for each data load operation, not for each
unique write-buffer-address location. Additionally, the
last data loaded prior to the Program Buffer to Flash
command will be programmed into the device. Note
also that if an address location is loaded more than
once into the buffer, the final data loaded for that address will be programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Program Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
The write-buffer programming operation can be suspended using the standard program suspend/resume
September 12, 2006
Am29LV033MU
25
D A T A
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the following ways:
■ Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■ Write to an address in a sector different than the
one specified during the Write-Buffer-Load command.
■ Write an Address/Data pair to a different
write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
■ Write data other than the Confirm Command after
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de-
26
S H E E T
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features
in Unlock Bypass mode.
Accelerated Program
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating
or unconnected; inconsistent behavior of the device
may result.
Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
Am29LV033MU
September 12, 2006
D A T A
S H E E T
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
No
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to
flash sector address
Notes:
Read DQ7 - DQ0 at
Last Loaded Address
When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
2.
DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3.
If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this flowchart
location was reached because DQ1= “1”, then the
Write to Buffer operation was ABORTED. In either
case, the proper reset command must be written
before the device can begin another operation. If
DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
4.
See Table 10 for command sequences required for
write buffer programming.
Yes
DQ7 = Data?
No
1.
No
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
(Note 2)
DQ7 = Data?
Yes
No
(Note 3)
FAIL or ABORT
Figure 4.
September 12, 2006
PASS
Write Buffer Programming Operation
Am29LV033MU
27
D A T A
S H E E T
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15
μs maximum (5 μs typical) and updates the status bits.
Addresses are not required when writing the Program
Suspend command.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 10 for program command sequence.
Figure 5.
Program Operation
No
After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
After the Program Resume command is written, the
device reverts to programming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more
information.
The system must write the Program Resume command (address bits are don’t care) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be
written after the device has resume programming.
28
Am29LV033MU
September 12, 2006
D A T A
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section
for information on these status bits.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 1 μs
Read data as
required
No
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
Figure 6.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
September 12, 2006
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Sector Erase Command Sequence
Yes
Write address/data
XXXh/30h
S H E E T
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the address and data requirements for the sector erase comm a n d s e q u e n c e. N o t e t h a t t h e S e c S i S e c t o r,
autoselect, and CFI functions are unavailable when a
program operation is in progress.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands.
Am29LV033MU
29
D A T A
S H E E T
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
START
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY# in the erasing sector. Refer to the
Write Operation Status section for information on
these status bits.
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
No
Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 7.
30
Am29LV033MU
Erase Operation
September 12, 2006
D A T A
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation.
S H E E T
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.
Note: During an erase operation, this flash device performs multiple internal operations which are invisible
to the system. When an erase operation is suspended,
any of the internal operations that were not fully completed must be restarted. As such, if this flash device
is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a
function of the number of suspends. The result will be
a longer cumulative erase time than without suspends.
Note that the additional suspends do not affect device
reliability or future performance. In most systems rapid
erase/suspend activity occurs only briefly. In such
cases, erase performance will not be significantly impacted.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors produces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard byte program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
September 12, 2006
Am29LV033MU
31
D A T A
S H E E T
Command Definitions
Table 10.
Read (Note 5)
Autoselect (Note 7)
Reset (Note 6)
Bus Cycles (Notes 1–4)
Cycles
Command Sequence (Notes)
Command Definitions
Addr
Data
1
RA
RD
First
Second
Addr
Data
Third
Addr
Fourth
Data
Addr
Fifth
Data
1
XXX
F0
Manufacturer ID
4
XXX
AA
XXX
55
XXX
90
X00
01
Device ID (Note 8)
6
XXX
AA
XXX
55
XXX
90
X01
7E
SecSi™ Sector Factory Protect
(Note 9)
4
XXX
AA
XXX
55
XXX
90
X03
(Note 9)
Sector Group Protect Verify
(Note 10)
4
XXX
AA
XXX
55
XXX
90
(SA)X02
00/01
Sixth
Addr
Data
Addr
Data
X0E
1C
X0F
00
Enter SecSi Sector Region
3
XXX
AA
XXX
55
XXX
88
Exit SecSi Sector Region
4
XXX
AA
XXX
55
XXX
90
XXX
00
Program
4
XXX
AA
XXX
55
XXX
A0
PA
PD
Write to Buffer
6
XXX
AA
XXX
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (Note 11)
3
XXX
AA
XXX
55
XXX
F0
Unlock Bypass
3
XXX
AA
XXX
55
XXX
20
Unlock Bypass Program (Note 12)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 13)
2
XXX
90
XXX
00
Chip Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
XXX
10
Sector Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
SA
30
Program/Erase Suspend (Note 14)
1
XXX
B0
Program/Erase Resume (Note 15)
1
XXX
30
CFI Query (Note 16)
1
55
98
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9.
3.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4.
During unlock and command cycles, when lower address bits are
don’t cares, address bits A21–A12 are also don’t cares.
5.
No unlock or command cycles required when device is in read
mode.
6.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
7.
8.
32
The fourth cycle of the autoselect command sequence is a read
cycle. See the Autoselect Command Sequence section for more
information.
The device ID must be read in three cycles.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A16 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Byte Count. Number of write buffer locations to load minus 1.
The data is 88h for factory locked and 08h for not factory locked.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. Command sequence resets device for next command after
aborted write-to-buffer operation.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
15. The Erase Resume command is valid only during the Erase
Suspend mode.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Am29LV033MU
September 12, 2006
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 8 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the
read mode.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
September 12, 2006
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29LV033MU
Figure 8.
Data# Polling Algorithm
33
D A T A
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
Table 11 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
34
S H E E T
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 21 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Am29LV033MU
September 12, 2006
D A T A
S H E E T
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
START
Read DQ7–DQ0
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6.
Read DQ7–DQ0
Toggle Bit
= Toggle?
No
Yes
No
Figure 9 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 21 shows the toggle bit timing diagram. Figure
22 shows the differences between DQ2 and DQ6 in
graphical form.
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
Reading Toggle Bits DQ6/DQ2
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 9.
Toggle Bit Algorithm
Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform
September 12, 2006
Am29LV033MU
35
D A T A
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase comTable 11.
Standard
Mode
Program
Suspend
Mode
Erase
Suspend
Mode
Write-toBuffer
S H E E T
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the system software should check the status of DQ3 prior to
and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 11 shows the status of DQ3 relative to the other
status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”.
The
system
must
issue
the
Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer
Write Operation Status
DQ7
Status
(Note 2)
Embedded Program Algorithm
DQ7#
Embedded Erase Algorithm
0
Program-Suspended
ProgramSector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
EraseSector
Suspend
Non-Erase Suspended
Read
Sector
Erase-Suspend-Program
DQ7#
(Embedded Program)
Busy (Note 3)
DQ7#
Abort (Note 4)
DQ7#
DQ6
Toggle
Toggle
No toggle
DQ5
(Note 1)
0
0
DQ3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
DQ1
0
N/A
RY/BY#
0
0
Invalid (not allowed)
1
Data
1
0
N/A
Toggle
N/A
Data
1
1
Toggle
0
N/A
N/A
N/A
0
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
36
Am29LV033MU
September 12, 2006
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
20 ns
A9, OE#, ACC, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
Figure 10. Maximum Negative
Overshoot Waveform
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot V SS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 10. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 11.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot V SS to –2.0 V for
periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for periods up
to 20 ns.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 11. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC for standard voltage range . . . . . . . . . . 2.7–3.6 V
Notes:
1. Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. See Ordering Information section for valid VCC/VIO range
combinations. The I/Os will not operate at 3 V when VIO =
1.8 V.
VCC for regulated voltage range . . . . . . . . . . 3.0–3.6 V
VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.0 V
September 12, 2006
Am29LV033MU
37
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
ILI
Input Load Current (Note 1)
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, ACC Input Load Current
VCC = VCC max; A9 = 12.5 V
35
µA
ILR
Reset Leakage Current
VCC = VCC max= 12.5 V
35
µA
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
±1.0
µA
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
ICC2
VCC Initial Page Read Current (1, 2)
CE# = VIL, OE# = VIH
ICC3
VCC Intra-Page Read Current (1, 2)
CE# = VIL, OE# = VIH
ICC4
VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH
ICC5
VCC Standby Current (Note 2)
ICC6
5 MHz
3
34
1 MHz
13
43
1 MHz
4
50
10 MHz
40
80
10 MHz
3
20
33 MHz
6
40
mA
50
60
mA
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
1
5
µA
VCC Reset Current (Note 2)
RESET# = VSS ± 0.3 V, WP# = VIH
1
5
µA
ICC7
Automatic Sleep Mode (Notes 2, 4)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V, WP# = VIH
1
5
µA
VIL1
Input Low Voltage 1(Notes 5, 6)
–0.5
0.8
V
VIH1
Input High Voltage 1 (Notes 5, 6)
1.9
VCC + 0.5
V
VIL2
Input Low Voltage 2 (Notes 5, 7)
–0.5
0.3 x VIO
V
VIH2
Input High Voltage 2 (Notes 5, 7)
1.9
VIO + 0.5
V
VHH
Voltage for ACC Program
Acceleration
VCC = 2.7 –3.6 V
11.5
12.5
V
VID
Voltage for Autoselect and Temporary
VCC = 2.7 –3.6 V
Sector Unprotect
11.5
12.5
V
VOL
Output Low Voltage
0.15 x VIO
V
VOH1
VOH2
VLKO
Output High Voltage
IOL = 4.0 mA, VCC = VCC min = VIO
mA
mA
IOH = –2.0 mA, VCC = VCC min = VIO
0.85 VIO
V
IOH = –100 µA, VCC = VCC min = VIO
VIO–0.4
V
Low VCC Lock-Out Voltage (Note 8)
2.3
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2.
3.
4.
5.
6.
7.
8.
38
Maximum ICC specifications are tested with VCC = VCCmax.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. Maximum VIH for these connections is VIO + 0.3 V
VCC voltage requirements.
VIO voltage requirements. VCC = 3 V and VIO = 3 V or 1.8 V. When VIO is at 1.8 V, I/Os cannot operate at 3 V.
Not 100% tested.
Am29LV033MU
September 12, 2006
D A T A
S H E E T
TEST CONDITIONS
Table 12.
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
Test Specifications
6.2 kΩ
All Speeds
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0–3.0
V
Input timing measurement
reference levels (See Note)
1.5
V
Output timing measurement
reference levels
0.5 VIO
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Figure 12.
Test Setup
Unit
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
0.5 VIO V
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and
Measurement Levels
September 12, 2006
Am29LV033MU
39
D A T A
S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDE
C
Std. Description
tAVAV
Test Setup
tRC Read Cycle Time (Note 1)
tAVQV tACC Address to Output Delay
tELQV
90R
tCE Chip Enable to Output Delay
tPAC
101R
101
112R
112
120R
120
Unit
Min
90
100
110
120
ns
CE#, OE# =
Max
VIL
90
100
110
120
ns
Max
90
100
110
120
ns
Max
25
30
30
40
30
40
ns
Max
25
30
30
40
30
40
ns
OE# = VIL
Page Access Time
C
tGLQV
tOE Output Enable to Output Delay
tEHQZ
tDF
Chip Enable to Output High Z
(Note 1)
Max
25
ns
tGHQZ
tDF
Output Enable to Output High Z
(Note 1)
Max
25
ns
tAXQX
Output Hold Time From
tOH Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
Min
0
ns
Min
10
ns
tOEH
Output Enable Read
Hold Time (Note Toggle and
1)
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 14.
40
Read Operation Timings
Am29LV033MU
September 12, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Same Page
A21-A3
A2-A0
Aa
Ab
tPACC
tACC
Data Bus
Qa
Ad
Ac
tPACC
Qb
tPACC
Qc
Qd
CE#
OE#
Figure 15.
September 12, 2006
Page Read Timings
Am29LV033MU
41
D A T A
S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
μs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
μs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 16.
42
Reset Timings
Am29LV033MU
September 12, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
90R
101,
101R
112,
112R
120,
120R
Unit
90
100
110
120
ns
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
µs
Effective Write Buffer Program Operation, Per
Byte (Notes 2, 4)
Typ
7.5
µs
Accelerated Effective Write Buffer Program
Operation, Per Byte (Notes 2, 4)
Typ
6.25
µs
Single Byte Program (Notes 2, 5)
Typ
60
µs
Accelerated Single Byte Programming Operation
(Notes 2, 5)
Typ
54
µs
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
WE# to RY/BY#
Max
tPOLL
Program Valid Before Status Polling (Note 6)
Max
tWLAX
tWHWH1
tWHWH2
tWHWH1
90
100
110
4
120
ns
µs
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–32 bytes programmed.
4. Effective write buffer specification is based upon a 32-byte write buffer operation.
5. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer.
6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied
upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to
reading the status bits upon resuming.
September 12, 2006
Am29LV033MU
43
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tPOLL
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
tWHWH1
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Note:PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 17.
Program Operation Timings
VHH
ACC
VIL or VIH
VIL or VIH
tVHH
tVHH
Figure 18.
44
Accelerated Program Timing Diagram
Am29LV033MU
September 12, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
XXXh
Addresses
Read Status Data
VA
SA
VA
XXXh for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”)
Figure 19.
September 12, 2006
Chip/Sector Erase Operation Timings
Am29LV033MU
45
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
tPOLL
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ15 and DQ7
DQ14–DQ8, DQ6–DQ0
Complement
Complement
Status Data
Status Data
True
True
Valid Data
Valid Data
High Z
High Z
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings
(During Embedded Algorithms)
46
Am29LV033MU
September 12, 2006
D A T A
S H E E T
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 21. Toggle Bit Timings
(During Embedded Algorithms)
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22.
September 12, 2006
DQ2 vs. DQ6
Am29LV033MU
47
D A T A
S H E E T
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect
Min
4
µs
Note: Not 100% tested.
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 23.
48
Temporary Sector Group Unprotect Timing Diagram
Am29LV033MU
September 12, 2006
D A T A
S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Group Protect or Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 24.
September 12, 2006
Sector Group Protect and Unprotect Timing Diagram
Am29LV033MU
49
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
90R
101,
101R
112,
112R
120,
120R
Unit
90
100
110
120
ns
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
45
ns
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
Write Buffer Program Operation
(Notes 2, 3)
Typ
240
µs
Effective Write Buffer Program Operation,
Per Byte (Notes 2, 4)
Typ
7.5
µs
Accelerated Effective Write Buffer Program
Operation, Per Byte (Notes 2, 4)
Typ
6.25
µs
Single Byte Program (Notes 2, 5)
Typ
60
µs
Accelerated Single Byte Programming
Operation (Note 2, 5)
Typ
54
µs
Sector Erase Operation (Note 2)
Typ
0.4
sec
RESET# High Time Before Write (Note 1)
Min
50
ns
Program Valid before Status Polling
(Note 6)
Max
4
µs
tWHWH1
tWHWH2
tWHWH1
tWHWH2
tRH
tPOLL
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information. Write buffer program is typical per word.
3. For 1–32 bytes programmed.
4. Effective write buffer specification is based upon a 32-byte write buffer operation.
5. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer.
6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied
upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to
reading the status bits upon resuming.
50
Am29LV033MU
September 12, 2006
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tPOLL
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#,
DQ15
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 25.
September 12, 2006
Alternate CE# Controlled Write (Erase/Program)
Operation Timings
Am29LV033MU
51
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.5
3.5
sec
Chip Erase Time
32
64
sec
Excludes 00h programming
prior to erasure (Note 6)
Single Byte Program Time (Note 3)
60
600
µs
Accelerated Single Byte Program Time (Note 3)
54
540
µs
Total Write Buffer Program Time (Note 4)
240
1200
µs
Effective Write Buffer Program Time (Note 5)
7.5
38
µs
Total Accelerated Write Buffer Program Time (Note 4)
200
1040
µs
Effective Accelerated Write Buffer Program Time (Note 5)
6.25
33
µs
Chip Program Time
31.5
73
sec
Excludes system level
overhead (Note 7)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, Programming specification assume that
all bits are programmed to 00h.
2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.
3. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer.
4. For 1-32 bytes programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-per-byte basis for a 32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence (s) for the program command. See Tables 12 and
13 for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
CIN
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
VIN = 0
VOUT = 0
VIN = 0
Typ
Max
Unit
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
TSOP
7.5
9
pF
BGA
3.9
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
52
Am29LV033MU
September 12, 2006
D A T A
S H E E T
DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
September 12, 2006
Am29LV033MU
53
D A T A
S H E E T
PHYSICAL DIMENSIONS
TS 040—40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
54
Am29LV033MU
September 12, 2006
D A T A
S H E E T
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse Thin Small Outline Package
Dwg rev AA; 10/99
September 12, 2006
Am29LV033MU
55
D A T A
S H E E T
PHYSICAL DIMENSIONS
FBC048—48-Ball Fine-Pitch Ball Grid Array
9 x 8 mm Package
Dwg rev AF; 10/99
56
Am29LV033MU
September 12, 2006
D A T A
S H E E T
REVISION SUMMARY
Revision A (June 20, 2002)
Revision A+2 (November 11, 2002)
Initial release.
Product Selector Guide and Read Only Operations
Revision A+1 (September 3, 2002)
Added a 30 ns Page Access time and Output Enable
Access time to the 113R and 123R Speed Options.
MIRRORBIT 64 MBIT Device Family
Ordering Information and Physical Dimensions
Added 64 Fortified BGA to LV640MU device.
Removed FBD048 package.
Alternate CE# Controlled Erase and Program
Operations
Added FBC048 package.
Added tRH parameter to table.
Changed order numbers and package markings to reflect new package.
Erase and Program Operations
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
Added tBUSY parameter to table.
Figure 16. Program Operation Timings
Added second bullet, SecSi sector-protect verify text
and figure 3.
Added RY/BY# to waveform.
SecSi Sector Flash Memory Region, and Enter
SecSi Sector/Exit SecSi Sector Command
Sequence
TSOP and BGA PIN Capacitance
Added the FBGA package.
Program Suspend/Program Resume Command
Sequence
Changed 15 μs typical to maximum and added 5 μs
typical.
Erase Suspend/Erase Resume Commands
Changed typical from 20 μs to 5 μs and added a maximum of 20 μs.
Noted that the ACC function and unlock bypass modes
are not available when the SecSi sector is enabled.
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase
Command Sequence
Product Selector Guide
Noted that the SecSi Sector, autoselect, and CFI
functions are unavailable when a program or erase
operation is in progress.
Added Note 2.
Common Flash Memory Interface (CFI)
Added 101R, 112R, and 120R to Speed Options.
Changed wording in last sentence of third paragraph
from, “...the autoselect mode.” to “...reading array
data.”
Connection Diagrams
Changed pin 30 from the 40-pin standard TSOP and
pin 11 from the 40-pin reverse TSOP from VCC to VIO.
Changed CFI website address.
Ordering Information
Erase and Programming Performance
Added 101R, 112R, and 120R to Valid Combinations
Table.
Added Note 1.
Changed the typicals and/or maximums of the Chip
Erase Time, Effective Write Buffer Program Time,
Byte/Word Program Time, and Accelerated Effective
Program Time to TBD.
Replaced 48-Pin Reverse and Standard Pinout Package to 40-Pin Reverse and Standard Pinout Package.
Revision A+3 (December 5, 2002)
Read-Only Operations, Alternate CE# Controlled
Erase and Program Operations, and Erase and
Program Operations
Added 101R, 112R, and 120R to Speed Options.
Physical Dimensions
Ordering Information
Modified package markings.
CMOS Compatible
Changed VIH1 and VIH2 minimum to 1.9.
Removed typos in notes.
Replaced TS 048 and TSR048 Package drawing to TS
040 and TSR040 Package drawing.
Revision A+4 (April 7, 2003)
Distinctive Characteristics
Corrected typos in performance characteristics.
September 12, 2006
Am29LV033MU
57
D A T A
Erase and Program Operations and Alternate CE#
Controlled Erase and Program Operations
Modified values of tWHWH1
Added Note #5
S H E E T
Table 10: Command Definitions
Replaced the Addr information for both Program/Erase
Suspend and Program/Erase Resume from BA to
XXX.
Erase and Programming Performance
AC Characteristics - Erase and Program
Operations
Added values to tables that were previously TBD
Added tPOLL information.
Added Note #3 and #4
AC Characteristics Figures - Program Operation
Timings, Data# Polling Timings (During Embedded
Algorithms, and Alternate CE# Controlled Write
(Erase/Program) Operation Timings
Revision B (May 16, 2003)
Distinctive Characteristics
Updated with tPOLL information.
Added typical active read current
Trademarks
Global
Updated.
Converted to Preliminary version.
Modified SecSi Sector Flash Memory Region section
to include ESN references.
Revision B+2 (May 20, 2004)
Global
CMOS Compatible
Converted to full Datasheet version.
Corrected Typ and Max values for the ICC 1, 2, and 3.
Cover sheet and Title page
Erase and Program Operations and Alternate CE#
Controlled Erase and Program Operations
Added notation referencing superseding documentation.
Changed Accelerated Effective Write Buffer Program
Operation value.
Revision B+3 (December 13, 2005)
Erase and Programming Performance
Global
Input values into table that were previously TBD.
This product has been retired and is not available for
designs. For new and current designs, S29GL032A
supersedes Am29LV033M and is the factory-recomm e n d e d m i g r a t i o n p a t h . P l e a s e r e fe r t o t h e
S29GL032A datasheet for specifications and ordering
information. Availability of this document is retained for
reference and historical purposes only.
Modified notes.
Removed Word references.
Revision B+1 (February 17, 2004)
Writing Commands/Command Sequences
Removed reference to word.
Revision B4 (September 12, 2006)
Word/Byte Program Command Sequences
Erase and Program Operations table
Removed reference to word.
Changed tBUSY to a maximum specification.
Added single byte programming note.
Erase Suspend/Erase Resume Commands
Added erase operation note.
58
Am29LV033MU
September 12, 2006
D A T A
S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2002-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
September 12, 2006
Am29LV033MU
59