SPANSION MB84VD22194FM

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50230-2E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
32M (×16) FLASH MEMORY &
4M (×16) STATIC RAM
MB84VD22184FM-70/MB84VD22194FM-70
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V
• High Performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 56-ball FBGA
(Continued)
■ PRODUCT LINE UP
Part No.
Supply Voltage(V)
VD22184FM / VD22194FM
VCCf= 3.0V
+0.1 V
–0.3 V
VCCs= 3.0V
Max Address Access Time (ns)
70
70
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
30
35
+0.1 V
–0.3 V
Note: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
■ PACKAGE
56-ball plastic FBGA
(BGA-56P-M03)
MB84VD22184FM/VD22194FM-70
(Continued)
— FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
Bank 1 : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank 2 : 24 Mbit (64 KB × 48)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4K word and sixty-three 32K word sectors in word mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD22184: Top sector
MB84VD22194: Bottom sector
• Embedded EraseTM * Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM * Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCCf Write Inhibit ≤ 2.5 V
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection
status.
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL34TF/BF” Datasheet in Detailed Function
— SRAM
• Power Dissipation
Operating : 40 mA Max
Standby : 10 µA Max
• Power Down Features using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.1 V
• CE1s and CE2s Chip Select
• Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD22184FM/VD22194FM-70
■ PIN ASSIGNMENT
(Top View)
Marking side
B8
C8
D8
E8
F8
G8
A15
N.C.
N.C.
A16
N.C.
Vss
A7
B7
C7
D7
E7
F7
G7
H7
A11
A12
A13
A14
N.C.
DQ15
DQ7
DQ14
A6
B6
C6
D6
E6
F6
G6
H6
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
A5
B5
C5
F5
G5
H5
WE
CE2s
A20
DQ4
Vccs
N.C.
A4
B4
C4
F4
G4
H4
RY/BY
DQ3
Vccf
DQ11
WP/ACC RESET
A3
B3
C3
D3
E3
F3
G3
H3
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
B2
C2
D2
E2
F2
G2
H2
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
B1
C1
D1
E1
F1
G1
A3
A2
A1
A0
CEf
CE1s
(BGA-56P-M03)
3
MB84VD22184FM/VD22194FM-70
■ PIN DESCRIPTION
Pin Name
Input/Output
A17 to A0
Address Inputs (Common)
I
A20 to A18
Address Inputs (Flash)
I
DQ15 to DQ0
Data Inputs / Outputs (Common)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
Ready/Busy Outputs (Flash) Open Drain
Output
O
UB
Upper Byte Control (SRAM)
I
LB
Lower Byte Control (SRAM)
I
Hardware Reset Pin / Sector Protection
Unlock (Flash)
I
Write Protect / Acceleration (Flash)
I
RY/BY
RESET
WP/ACC
4
Function
N.C.
No Internal Connection
VSS
Device Ground (Common)
Power
VCCf
Device Power Supply (Flash)
Power
VCCs
Device Power Supply (SRAM)
Power
—
MB84VD22184FM/VD22194FM-70
■ BLOCK DIAGRAM
VCCf
VSS
A20 to A0
RY/BY
A20 to A0
WP/ACC
RESET
CEf
32 M bit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A17 to A0
LB
UB
WE
OE
CE1s
CE2s
4 M bit
Static RAM
DQ15 to DQ0
5
MB84VD22184FM/VD22194FM-70
■ DEVICE BUS OPERATIONS
• User Bus Operations
Operation *1, *3
Full Standby
CEf CE1s CE2s OE
H
H
Output Disable
L
Read from Flash *2
L
Write to Flash
L
Read from SRAM
Write to SRAM
H
H
Temporary Sector
Group Unprotection*4
X
Flash Hardware Reset
X
Boot Block Sector Write
Protection
X
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
L
L
H
H
X
X
H
X
X
L
X
X
WP/
DQ7 to DQ0 DQ15 to DQ8 RESET ACC
*5
WE
LB
UB
X
X
X
X
High-Z
High-Z
H
H
X
X
High-Z
High-Z
X
X
H
H
High-Z
High-Z
H
H
X
X
High-Z
High-Z
L
H
X
X
DOUT
H
L
X
X
L
L
X
H
L
H
X
H
X
DOUT
H
X
DIN
DIN
H
X
L
DOUT
DOUT
H
L
High-Z
DOUT
H
X
L
H
DOUT
High-Z
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
X
X
X
X
X
X
VID
X
X
X
X
X
High-Z
High-Z
L
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9V) ; Program time will reduce by 40%.
6
MB84VD22184FM/VD22194FM-70
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
Tstg
–55
+125
°C
TA
–30
+85
°C
VIN, VOUT
–0.3
VCCf + 0.3
V
VCCs + 0.4
V
VCCf/VCCs Supply *1
VCCf, VCCs
–0.3
+3.3
V
2
VIN
–0.5
+13.0
V
VIN
–0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins
except RESET, WP/ACC *1
RESET *
3
WP/ACC *
*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or
VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+1.0 V or VCCs + 1.0 V for periods
of up to 20 ns.
*2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs)
does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to
+14.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
VCCf/VCCs Supply Voltages
Symbol
Value
Unit
Min
Max
TA
–30
+85
°C
Vccf, Vccs
+2.7
+3.1
V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
7
MB84VD22184FM/VD22194FM-70
■ ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Value
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
RESET Inputs Leakage
Current
ILIT
VCCf = VCCf Max, VCCs = VCCs Max,
RESET = 12.5V
—
—
35
µA
Flash VCC Active Current
(Read) *1
ICC1f
CEf = VIL,
OE = VIH
tCYCLE = 5 MHz
—
—
18
mA
tCYCLE = 1 MHz
—
—
4
mA
Flash VCC Active Current
(Program/Erase) *2
ICC2f
CEf = VIL, OE = VIH
—
—
30
mA
Flash VCC Active Current
(Read-While-Program) *5
ICC3f
CEf = VIL, OE = VIH
—
—
48
mA
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
CEf = VIL, OE = VIH
—
—
48
mA
Flash VCC Active Current
(Erase-Suspend-Program)
ICC5f
CEf = VIL, OE = VIH
—
—
35
mA
ACC Input Leakage
Current
ILIA
VCCf = VCCf Max, VCCs = VCCs Max,
WP/ACC = VACC Max
—
—
20
mA
SRAM VCC Active Current
ICC1s
VCCs = VCCs Max,
CE1s = VIL,
CE2s = VIH
tCYCLE =10 MHz
—
—
40
mA
SRAM VCC Active Current
ICC2s
tCYCLE = 10 MHz
CE1s = 0.2 V,
CE2s = VCCs – 0.2 V tCYCLE = 1 MHz
—
—
40
mA
—
—
8
mA
Flash VCC Standby Current
ISB1f
VCCf = VCCf Max, CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
—
5
µA
Flash VCC Standby Current
(RESET)
ISB2f
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
—
5
µA
Flash VCC Current
(Automatic Sleep Mode) *3
ISB3f
VCCf = VCCf Max, CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
VIN = VCCf± 0.3 V or VSS ± 0.3 V
—
—
5
µA
SRAM VCC Standby Current
ISB1s
CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V
LB = UB > VCCs–0.2 V or < 0.2V
—
—
10
µA
SRAM VCC Standby Current
ISB2s
CE1s > VCCs – 0.2 V or < 0.2V,
CE2s < 0.2 V
LB = UB > VCCs–0.2 V or < 0.2V
—
—
10
µA
(Continued)
8
MB84VD22184FM/VD22194FM-70
(Continued)
Parameter
Symbol
Test Conditions
Input Low Level
VIL
Input High Level
Value
Unit
Min
Typ
Max
—
–0.3
—
0.5
V
VIH
—
2.2
—
VCC+0.3*6
V
Voltage for Sector
Protection, and Temporary
Sector Unprotection
(RESET) *4
VID
—
11.5
—
12.5
V
Voltage for Program
Acceleration (WP/ACC) *4
VACC
—
8.5
9.0
9.5
V
SRAM Output Low Level
VOL
VCCs = VCCs Min, IOL = 0.1 mA
—
—
0.4
V
SRAM Output High Level
VOH
VCCs = VCCs Min, IOH = –0.1 mA
2.0
—
—
V
Flash Output Low Level
VOL
VCCf = VCCf Min, IOL = 4.0 mA
—
—
0.45
V
Flash Output High Level
VOH
VCCf = VCCf Min, IOH = –0.1 mA
VCCs–0.4
—
—
V
Flash Low VCCf Lock-Out
Voltage
VLKO
2.3
—
2.5
V
—
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4 : Applicable for only VCCf applying.
*5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)
*6 : VCC indicates lower of VCCf or VCCs.
9
MB84VD22184FM/VD22194FM-70
2. AC CHARACTERISTICS
• CE Timing
Symbol
Parameter
Test Setup
JEDEC
Standard
—
tCCR
CE Recover Time
—
Min
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
tCCR
tCCR
CE1s
CE2s
• Flash Characteristics
Please refer to “■32M Flash Memory for MCP”.
• SRAM Characteristics,
Please refer to “■4M SRAM for MCP”.
10
Value
Unit
0
ns
MB84VD22184FM/VD22194FM-70
■ 32 M FLASH MEMORY for MCP
1. Flexible Sector-erase Architecture on Flash Memory
• Eight 4 K words, and sixty three 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Bank B
Bank A
SA70 : 8KB (4KW)
SA69 : 8KB (4KW)
SA68 : 8KB (4KW)
SA67 : 8KB (4KW)
SA66 : 8KB (4KW)
SA65 : 8KB (4KW)
SA64 : 8KB (4KW)
SA63 : 8KB (4KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 64KB (32KW)
SA6 : 64KB (32KW)
SA5 : 64KB (32KW)
SA4 : 64KB (32KW)
SA3 : 64KB (32KW)
SA2 : 64KB (32KW)
SA1 : 64KB (32KW)
SA0 : 64KB (32KW)
(Top Boot Block)
1FFFFFh
1FF000h
1FE000h
1FD000h
1FC000h
1FB000h
1FA000h
1F9000h
1F8000h
1F0000h
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
Bank B
Bank A
SA70 : 64KB (32KW)
SA69 : 64KB (32KW)
SA68 : 64KB (32KW)
SA67 : 64KB (32KW)
SA66 : 64KB (32KW)
SA65 : 64KB (32KW)
SA64 : 64KB (32KW)
SA63 : 64KB (32KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
1FFFFFh
1F8000h
1F0000h
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
(Bottom Boot Block)
11
MB84VD22184FM/VD22194FM-70
Sector Address Table (Top Boot Type)
B
a
Sector
n
k
B
a
n
k
B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Sector address
Bank
address
A20 A19 A18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector size
(Kwords)
Address range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
(Continued)
12
MB84VD22184FM/VD22194FM-70
(Continued)
B
a
Sector
n
k
B
a
n
k
B
B
a
n
k
A
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Sector address
Bank
address
A20 A19 A18
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector size
(Kwords)
Address range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1F8FFFh
1F9000h to 1F9FFFh
1FA000h to 1FAFFFh
1FB000h to 1FBFFFh
1FC000h to 1FCFFFh
1FD000h to 1FDFFFh
1FE000h to 1FEFFFh
1FF000h to 1FFFFFh
13
MB84VD22184FM/VD22194FM-70
Sector Address Table (Bottom Boot Type)
B
a
Sector
n
k
B
a
n
k
B
SA70
SA69
SA68
SA67
SA66
SA65
SA64
SA63
SA62
SA61
SA60
SA59
SA58
SA57
SA56
SA55
SA54
SA53
SA52
SA51
SA50
SA49
SA48
SA47
SA46
SA45
SA44
SA43
SA42
SA41
SA40
SA39
Sector address
Bank
address
A20 A19 A18
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
A17
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A16
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A15
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector size
(Kwords)
Address range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1F8000h to 1FFFFFh
1F0000h to 1F7FFFh
1E8000h to 1EFFFFh
1E0000h to 1E7FFFh
1D8000h to 1DFFFFh
1D0000h to 1D7FFFh
1C8000h to 1CFFFFh
1C0000h to 1C7FFFh
1B8000h to 1BFFFFh
1B0000h to 1B7FFFh
1A8000h to 1AFFFFh
1A0000h to 1A7FFFh
198000h to 19FFFFh
190000h to 197FFFh
188000h to 18FFFFh
180000h to 187FFFh
178000h to 17FFFFh
170000h to 177FFFh
168000h to 16FFFFh
160000h to 167FFFh
158000h to 15FFFFh
150000h to 157FFFh
148000h to 14FFFFh
140000h to 147FFFh
138000h to 13FFFFh
130000h to 137FFFh
128000h to 12FFFFh
120000h to 127FFFh
118000h to 11FFFFh
110000h to 117FFFh
108000h to 10FFFFh
100000h to 107FFFh
(Continued)
14
MB84VD22184FM/VD22194FM-70
B
a
Bank
Sector
n
address
k
A20 A19 A18
SA38
0
1
1
SA37
0
1
1
SA36
0
1
1
SA35
0
1
1
SA34
0
1
1
SA33
0
1
1
B SA32
0
1
1
a SA31
0
1
1
n
0
1
0
k SA30
SA29
0
1
0
B
SA28
0
1
0
SA27
0
1
0
SA26
0
1
0
SA25
0
1
0
SA24
0
1
0
SA23
0
1
0
SA22
0
0
1
SA21
0
0
1
SA20
0
0
1
SA19
0
0
1
SA18
0
0
1
SA17
0
0
1
SA16
0
0
1
SA15
0
0
1
SA14
0
0
0
SA13
0
0
0
B
0
0
0
a SA12
n SA11
0
0
0
k SA10
0
0
0
A
SA9
0
0
0
SA8
0
0
0
SA7
0
0
0
SA6
0
0
0
SA5
0
0
0
SA4
0
0
0
SA3
0
0
0
SA2
0
0
0
SA1
0
0
0
SA0
0
0
0
Sector address
A17
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
A16
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
A15
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
1
1
0
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector size
(Kwords)
Address range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
0F8000h to 0FFFFFh
0F0000h to 0F7FFFh
0E8000h to 0EFFFFh
0E0000h to 0E7FFFh
0D8000h to 0DFFFFh
0D0000h to 0D7FFFh
0C8000h to 0CFFFFh
0C0000h to 0C7FFFh
0B8000h to 0BFFFFh
0B0000h to 0B7FFFh
0A8000h to 0AFFFFh
0A0000h to 0A7FFFh
098000h to 09FFFFh
090000h to 097FFFh
088000h to 08FFFFh
080000h to 087FFFh
078000h to 07FFFFh
070000h to 077FFFh
068000h to 06FFFFh
060000h to 067FFFh
058000h to 05FFFFh
050000h to 057FFFh
048000h to 04FFFFh
040000h to 047FFFh
038000h to 03FFFFh
030000h to 037FFFh
028000h to 02FFFFh
020000h to 027FFFh
018000h to 01FFFFh
010000h to 017FFFh
008000h to 00FFFFh
007000h to 007FFFh
006000h to 006FFFh
005000h to 005FFFh
004000h to 004FFFh
003000h to 003FFFh
002000h to 002FFFh
001000h to 001FFFh
000000h to 000FFFh
15
MB84VD22184FM/VD22194FM-70
Sector Group Addresses Table (Top Boot Type)
Sector group
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
X
X
X
SA0
0
1
1
0
X
X
X
SA1 to SA3
1
1
SGA1
0
0
0
SGA2
0
0
0
1
X
X
X
X
X
SA4 to SA7
SGA3
0
0
1
0
X
X
X
X
X
SA8 to SA11
SGA4
0
0
1
1
X
X
X
X
X
SA12 to SA15
SGA5
0
1
0
0
X
X
X
X
X
SA16 to SA19
SGA6
0
1
0
1
X
X
X
X
X
SA20 to SA23
SGA7
0
1
1
0
X
X
X
X
X
SA24 to SA27
SGA8
0
1
1
1
X
X
X
X
X
SA28 to SA31
SGA9
1
0
0
0
X
X
X
X
X
SA32 to SA35
SGA10
1
0
0
1
X
X
X
X
X
SA36 to SA39
SGA11
1
0
1
0
X
X
X
X
X
SA40 to SA43
SGA12
1
0
1
1
X
X
X
X
X
SA44 to SA47
SGA13
1
1
0
0
X
X
X
X
X
SA48 to SA51
SGA14
1
1
0
1
X
X
X
X
X
SA52 to SA55
SGA15
1
1
1
0
X
X
X
X
X
SA56 to SA59
0
0
0
1
X
X
X
SA60 to SA62
1
0
SGA16
16
0
1
1
1
1
SGA17
1
1
1
1
1
1
0
0
0
SA63
SGA18
1
1
1
1
1
1
0
0
1
SA64
SGA19
1
1
1
1
1
1
0
1
0
SA65
SGA20
1
1
1
1
1
1
0
1
1
SA66
SGA21
1
1
1
1
1
1
1
0
0
SA67
SGA22
1
1
1
1
1
1
1
0
1
SA68
SGA23
1
1
1
1
1
1
1
1
0
SA69
SGA24
1
1
1
1
1
1
1
1
1
SA70
MB84VD22184FM/VD22194FM-70
Sector Group Addresses Table (Bottom Boot Type)
Sector group
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
1
1
1
SA7
0
1
1
0
X
X
X
SA8 to SA10
1
1
SGA8
0
0
0
0
SGA9
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
1
1
1
0
X
X
X
X
X
SA63 to SA66
0
0
0
1
X
X
X
SA67 to SA69
1
0
1
1
X
X
X
SA70
SGA23
SGA24
1
1
1
1
1
1
1
1
17
MB84VD22184FM/VD22194FM-70
Sector Group Protection Verify Autoselect Codes Table (Top Boot Type)
A20 to A12
A6
A3
A2
A1
A0
Code (HEX)
Manufacture’s Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
2250h
Sector Group Protection
SA
L
L
L
H
L
01h*
Type
Legend: L = VIL, H = VIH. See DC Characteristics for voltage levels.
* : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
Expanded Autoselect Code Table (Top Boot Type)
Type
Code
Manufacture’s
Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
04h
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device Code
2250h
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
Sector Group
Protection
01h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Sector Group Protection Verify Autoselect Codes Table (Bottom Boot Type)
A20 to A12
A6
A3
A2
A1
A0
Code (HEX)
Manufacture’s Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
2253h
Sector Group Protection
SA
L
L
L
H
L
01h*
Type
Legend: L = VIL, H = VIH. See DC Characteristics for voltage levels.
* : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
Expanded Autoselect Code Table (Bottom Boot Type)
Type
18
Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacture’s
Code
04h
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device Code
2253h
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
Sector Group
Protection
01h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MB84VD22184FM/VD22194FM-70
Command Definitions Table
Command
sequence
Bus
First bus
write
write cycle
cycles
req’d Addr. Data
1
XXXh F0h
3
555h
AAh
Second bus
write cycle
Addr.


Data


Addr.


Data


90h






A0h
PA
PD




Sixth bus
write cycle
Autoselect
3
555h
AAh
2AAh
55h
Program
Program
Suspend
Program
Resume
Chip Erase
Sector Erase
Erase Suspend
Erase Resume
Set to
Fast Mode
Fast
Program *2
Reset from Fast
Mode *2
Extended
Sector Group
Protection *3
4
555h
AAh
2AAh
55h
1
BA
B0h










1
BA
30h










6
6
1
1
555h
555h
BA
BA
AAh
AAh
B0h
30h
2AAh
2AAh


55h
55h


555h
555h


80h
80h


555h
555h


AAh
AAh


2AAh
2AAh


55h
55h


555h
SA


10h
30h


3
555h
AAh
2AAh
55h
555h
20h






2
XXXh
A0h
PA
PD








2
BA
90h
XXXh
F0h*6








4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD




1
(BA)
55h
98h










3
555h
AAh
2AAh
55h
555h
88h






4
555h
AAh
2AAh
55h
555h
A0h
(HRA)
PA
PD




4
555h
AAh
2AAh
55h
(HRBA)
555h
90h
XXXh
00h




Query *4
HiddenROM
Entry
HiddenROM
Program *5
HiddenROM
Exit *5
Data

55h
Fifth bus
write cycle
Addr.

555h
(BA)
555h
555h
Read/Reset*1
Read/Reset*1
Addr.

2AAh
Fourth bus
read/write cycle
Data Addr. Data



F0h
RA
RD
Third bus
write cycle
(Continued)
19
MB84VD22184FM/VD22194FM-70
(Continued)
*1 : Both of these reset commands are equivalent.
*2 : This command is valid during Fast Mode.
*3 : This command is valid while RESET = VID.
*4 : The valid address are A6 to A0.
*5 : This command is valid during HiddenROM mode.
*6 : The date “00h” is also acceptable.
Notes: • Address bits A20 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector
Address (SA) , Bank Address (BA) .
• Bus operations are defined in
“User Bus Operations Tables” (■DEVICE BUS OPERATION).
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and
A12 will uniquely select any sector.
BA = Bank Address (A20 to A18)
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
• SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0,
1, 0) .
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
• HRA = Address of the HiddenROM area
Top Boot Type
:
1FF000h to 1FF07Fh
Bottom Boot Type :
000000h to 00007Fh
• HRBA = Bank Address of the HiddenROM area
Top Boot Type
: A20 = A19 = A18 = 1
Bottom Boot Type
: A20 = A19 = A18 = 0
• The system should generate the following address patterns :
Word Mode : 555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command combinations not described in “Command Definitions Table” are illegal.
20
MB84VD22184FM/VD22194FM-70
2. AC Characteristics
• Read Only Operations Characteristics
Symbol
Value*
Parameter
Test setup
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
tOE
Chip Enable to Output High-Z
tEHQZ
Output Enable to Output High-Z
Output Hold Time from Addresses,
CEf or OE, Whichever Occurs First
RESET Pin Low to Read Mode
Unit
Min
Max
70

ns
CEf = VIL
OE = VIL

70
ns
OE = VIL

70
ns
—

30
ns
tDF
—

25
ns
tGHQZ
tDF
—

25
ns
tAXQX
tOH
—
0

ns
—
tREADY
—

20
µs
—
* : Test Conditions:
Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 0.5 × Vccf
Output: 0.5 × Vccf
21
MB84VD22184FM/VD22194FM-70
• Write/Erase/Program Operations
Parameter
Write Cycle Time
Address Setup Time
Address Setup Time to OE Low During Toggle Bit
Polling
Address Hold Time
Address Hold Time from CEf or OE High During
Toggle Bit Polling
Data Setup Time
Data Hold Time
Read
Output Enable
Hold Time
Toggle and Data Polling
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
Read Recover Time Before Write
Read Recover Time Before Write
CEf Setup Time
WE Setup Time
CEf Hold Time
WE Hold Time
Write Pulse Width
CEf Pulse Width
Write Pulse Width High
CEf Pulse Width High
Sector Erase Operation *1
VCCf Setup Time
Rise Time to VID *2
Rise Time to VID *2
Voltage Transition Time *2
Write Pulse Width *2
OE Setup Time to WE Active *2
CEf Setup Time to WE Active *2
Recover Time from RY/BY
RESET Pulse Width
RESET High Level Period before Read
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
Erase Time-Out Time
Erase Suspend Transition Time
Symbol
JEDEC
Standard
tAVAV
tWC
tAS
tAVWL
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Group Protection operation.
22
Min
70
0
Value
Typ


Max


Unit
ns
ns
—
tASO
12


ns
tWLAX
tAH
45


ns
—
tAHT
0


ns
tDVWH
tWHDX
tDS
tDH
—
tOEH
—
—
tCEPH
tOEPH
tGHWL
tGHEL
tCS
tWS
tCH
tWH
tWP
tCP
tWPH
tCPH
tWHWH2
tVCS
tVIDR
tVACCR
tVLHT
tWPP
tOESP
tCSP
tRB
tRP
tRH
tBUSY
tEOE
tTOW
tSPD
30
0
0
10
20
20
0
0
0
0
0
0
35
35
25
25

50
500
500
4
100
4
4

500
200


50

















0.5









































90
70


ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
µs
ns
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
µs
tGHWL
tGHEL
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MB84VD22184FM/VD22194FM-70
• Read Cycle (Flash)
tRC
Address Stable
Address
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCEf
High-Z
DQ
High-Z
Output Valid
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCEf
RESET
tOH
DQ
High-Z
Output Valid
23
MB84VD22184FM/VD22194FM-70
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CEf
tCH
tCS
tCEf
OE
tGHWL
tWP
tOE
tWHWH1
tWPH
WE
tOH
tDS
tDH
DQ
A0h
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode.
24
DOUT
MB84VD22184FM/VD22194FM-70
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tWHWH1
tCPH
CEf
tDS
tDH
DQ
A0h
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode.
25
MB84VD22184FM/VD22194FM-70
• AC Waveforms Chip/Sector Erase Operations (Flash)
2AAh
555h
Address
tWC
tAS
555h
SA*
2AAh
555h
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
WE
tDS
tDH
AAh
DQ
30h for Sector Erase
55h
80h
AAh
55h
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
Note : These waveform are for the ×16 mode.
26
10h/
30h
MB84VD22184FM/VD22194FM-70
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tDF
tOE
OE
tOEH
WE
tCEf
*
DQ7
DQ7 =
Valid Data
DQ7
Data Input
High-Z
tWHWH1 or 2
DQ
(DQ6 to DQ0)
DQ6 to DQ0 = Output Flag
Data Input
tBUSY
DQ8 to DQ0
Valid Data
High-Z
tEOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
27
MB84VD22184FM/VD22194FM-70
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
tOEH
tOEH
tOEPH
OE
tDH
DQ6/DQ2
Data
tCEf *
tOE
Toggle
Data
Toggle
Data
Toggle
Data
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
28
Stop
Toggling
Output
Valid
MB84VD22184FM/VD22194FM-70
• Back-to-back Read/Write Timing Diagram (Flash)
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tAHT
tCE
CEf
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
29
MB84VD22184FM/VD22194FM-70
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
30
MB84VD22184FM/VD22194FM-70
• Temporary Sector Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection Period
31
MB84VD22184FM/VD22194FM-70
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SGAx
SGAx
SGAy
A0
A1
A6
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
tOE
SGAx : Sector Group Address to be protected
SGAy : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
32
60h
MB84VD22184FM/VD22194FM-70
• Accelerated Program (Flash)
VCCf
tVACCR
tVCS
tVLHT
VACC
3V
3V
WP/ACC
CEf
WE
tVLHT
Program Command Sequence
tVLHT
RY/BY
Acceleration period
33
MB84VD22184FM/VD22194FM-70
3. Erase and Programming Performance
Limits
Parameter
Comments
Typ
Max
Sector Erase Time

0.5
2.0
s
Excludes programming time
prior to erasure
Word Programming Time

6.0
100
µs
Excludes system-level
overhead
Chip Programming Time

12.6
50
s
Excludes system-level
overhead
100,000


cycle
Program/Erase Cycle
34
Unit
Min

MB84VD22184FM/VD22194FM-70
■ 4 M SRAM for MCP
1. AC Characteristics
• Read Cycle (SRAM)
Parameter
Symbol
Value
Min
Max
Unit
Read Cycle Time
tRC
70
—
ns
Address Access Time
tAA
—
70
ns
Chip Enable (CE1s) Access Time
tCO1
—
70
ns
Chip Enable (CE2s) Access Time
tCO2
—
70
ns
Output Enable Access Time
tOE
—
35
ns
LB, UB to Output Valid
tBA
—
70
ns
Chip Enable (CE1s Low and CE2s High) to Output Active
tCOE
5
—
ns
Output Enable Low to Output Active
tOEE
0
—
ns
UB, LB Enable Low to Output Active
tBE
0
—
ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z
tOD
—
25
ns
Output Enable High to Output High-Z
tODO
—
25
ns
UB, LB Output Enable to Output High-Z
tBD
—
25
ns
Output Data Hold Time
tOH
10
—
ns
Note: Test Conditions– Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCs
Timing measurement reference level
Input: 0.5×VCCs
Output: 0.5×VCCs
35
MB84VD22184FM/VD22194FM-70
• Read Cycle (SRAM)
tRC
Address
tAA
tOH
tCO1
CE1s
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
tODO
tOEE
LB, UB
tBD
tBA
tBE
tCOE
DQ
Note: WE remains HIGH for the read cycle.
36
Valid Data Output
MB84VD22184FM/VD22194FM-70
• Write Cycle (SRAM)
Parameter
Symbol
Value
Min
Max
Unit
Write Cycle Time
tWC
70
—
ns
Write Pulse Width
tWP
50
—
ns
Chip Enable to End of Write
tCW
55
—
ns
Address valid to End of Write
tAW
55
—
ns
UB, LB to End of Write
tBW
55
—
ns
Address Setup Time
tAS
0
—
ns
Write Recovery Time
tWR
0
—
ns
WE Low to Output High-Z
tODW
—
25
ns
WE High to Output Active
tOEW
0
—
ns
Data Setup Time
tDS
30
—
ns
Data Hold Time
tDH
0
—
ns
37
MB84VD22184FM/VD22194FM-70
• Write Cycle *1 (WE control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tOEW
tODW
DOUT
*2
*3
tDS
DIN
*4
tDH
Valid Data Input
*4
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output
will remain at high impedance.
*3 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output
will remain at high impedance.
*4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity
must not be applied.
38
MB84VD22184FM/VD22194FM-70
• Write Cycle *1 (CE1s control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data Input
*2
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
39
MB84VD22184FM/VD22194FM-70
• Write Cycle *1 (CE2s Control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tCW
CE1s
tAW
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data Input
*2
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
40
MB84VD22184FM/VD22194FM-70
• Write Cycle *1 (LB, UB Control) (SRAM)
tWC
Address
tWP
tWR
WE
tCW
CE1s
tCW
CE2s
tAW
tAS
tBW
LB, UB
tBE
tCOE
tODW
DOUT
tDS
DIN
*2
tDH
Valid Data Input
*2
*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.
*2 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
41
MB84VD22184FM/VD22194FM-70
2. Data Retention Characteristics (SRAM)
Parameter
Symbol
Data Retention Supply Voltage
Standby Current
VDH = 3.0 V
Chip Deselect to Data Retention Mode Time
Recovery Time
Value
Unit
Min
Typ
Max
VDH
1.5
—
3.1
V
IDDS2
—
—
10
µA
tCDR
0
—
—
ns
tR
tRC
—
—
ns
Note : tRC: Read cycle time
• CE1s Controlled Data Retention Mode *1
VCCs
Data Retention Mode
2.7 V
VIH
VDH
*2
*2
VCCs – 0.2 V
CE1s
tR
tCDR
GND
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
*2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition
of VCCs from VCCs Max to VIH Min level.
• CE2s Controlled Data Retention Mode *
VCCs
Data Retention Mode
2.7 V
VDH
VIH
tCDR
tR
CE2s
VIL
0.2 V
GND
* : In CE2s controlled data retention mode, input and input/output pins can be used between
–0.3 V to Vccs+0.3V.
42
MB84VD22184FM/VD22194FM-70
■ PIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
Unit
Typ
Max
Input Capacitance
CIN
VIN = 0
11
14
pF
Output Capacitance
COUT
VOUT = 0
12
16
pF
Control Pin Capacitance
CIN2
VIN = 0
14
16
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0
21.5
26
pF
Note : Test conditions TA = + 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET.
Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be
applied to RESET.
• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
43
MB84VD22184FM/VD22194FM-70
■ ORDERING INFORMATION
MB84VD2218
4
FM
-70
PBS
PACKAGE TYPE
PBS = 56-ball FBGA
SPEED OPTION
See Product Selector Guide
Device Revision
Bank Architecture
4 = 8Mbit / 24Mbit (Fixed Bank)
DEVICE NUMBER/DESCRIPTION
32Mega-bit (2M × 16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
4Mega-bit (256K × 16-bit) SRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2218 = Top sector
84VD2219 = Bottom sector
44
MB84VD22184FM/VD22194FM-70
■ PACKAGE DIMENSION
56-ball plastic FBGA
(BGA-56P-M03)
9.00±0.10(.354±.004)
1.2(.047)
(Mounting height)
MAX.
0.30±0.10
(Stand off)
(.012±.004)
7.00±0.10
(.276±.004)
5.60(.220)
0.80
(.031)
8
7
6
5
4
3
2
1
5.60(.220)
0.80
(.031)
K J H G F E D C B A
INDEX-MARK AREA
56-ø0.45
56-ø.018
+0.10
–0.05
+.004
–.002
0.08(.003)
M
0.10(.004)
C
2002 FUJITSU LIMITED BGA560030Sc-1-1
Dimensions in mm (inches)
Note: The values in parentheses are reference values.
45
MB84VD22184FM/VD22194FM-70
FUJITSU LIMITED
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representatives before ordering.
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circuit examples, in this document are presented solely for the
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F0311
 FUJITSU LIMITED Printed in Japan