FUJITSU MB84VD2002

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50110-1E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (× 8/× 16) FLASH MEMORY &
2M (× 8) STATIC RAM
MB84VD2002-10/MB84VD2003-10
■ FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–20 to +85°C
— FLASH MEMORY
• Simultaneous operations Read-while Erase or Read-while-Program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2002: Top sector
MB84VD2003: Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to "MBM29DL800TA/BA" data sheet in detailed function
— SRAM
• Power dissipation
Operating : 35 mA max.
Standby : 50 µA max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VD2002-10/MB84VD2003-10
■ BLOCK DIAGRAM
VCCf
VSS
A0 to A18
RY/BY
A0 to A18
A-1
DQ8 to DQ15
8 M bit
Flash Memory
RESET
CEf
BYTE
DQ0 to DQ7
VCCs
VSS
A0 to A16
2 M bit
Static RAM
SA
WE
OE
CE1s
CE2s
■ EXAMPLE OF CONNECTION WITH CHIPSET
VCC
A[1:19]
A[0:19]
A0
A[0:18]
SA
VCCf
BYTE
RESET
ROM_CS/
CEf
RAM_CS/
CE1s
Battery
Backup
Control
RY/BY
VCCs
CE2s
BATTERY BACKUP
HWR/
LWR/
WE
RD/
OE
D[0:15]
D[0:15]
CHIPSET
2
DQ[0:15]
MB84VD2002/3
MB84VD2002-10/MB84VD2003-10
■ PIN ASSIGNMENTS
(Top View)
A
B
C
D
E
F
G
H
6
CE1s
VSS
DQ1
A1
A2
A4
CE2s
A9
5
A10
DQ5
DQ2
A0
A3
A7
RY/BY
A14
4
OE
DQ7
DQ4
DQ0
A6
A18
RESET
A15
3
A11
A8
A5
DQ8
DQ3
DQ12
A12
BYTE
2
A13
A17
SA*
CEf
DQ10
VCCf
DQ6
DQ15/A-1
1
WE
VCCs
A16
VSS
DQ9
DQ11
DQ13
DQ14
*: A17 for SRAM
Table 1 Pin Configuration
Pin
A0 to A16
Function
Input/
Output
Address Inputs (Common)
I
A-1, A17 to A18
Address Input (Flash)
I
SA
Address Input (SRAM)
I
DQ0 to DQ7
Data Inputs/Outputs (Common)
I/O
DQ8 to DQ15
Data Inputs/Outputs (Flash)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
RY/BY
Ready/Busy Outputs (Flash)
O
BYTE
Selects 8-bit or 16-bit mode (Flash)
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
I
RESET
N.C.
No Internal Connection
—
VSS
Device Ground (Common)
Power
VCCf
Device Power Supply (Flash)
Power
VCCs
Device Power Supply (SRAM)
Power
3
MB84VD2002-10/MB84VD2003-10
■ PRODUCT LINE UP
Flash Memory
Ordering Part No.
VCC = 3.0 V
+0.6 V
–0.3 V
SRAM
MB84VD2002-10/MB84VD2003-10
Max. Address Access Time (ns)
100
100
Max. CE Access Time (ns)
100
100
Max. OE Access Time (ns)
40
50
■ BUS OPERATIONS
Table 2 User Bus Operations (BYTE=VIL)
Operation (1), (3)
CEf
CE1s
CE2s
H
X
X
L
X
X
H
X
X
L
H
X
X
L
OE
WE
DQ0 to DQ7 DQ8 to DQ15
RESET
X
X
HIGH-Z
HIGH-Z
H
H
H
HIGH-Z
HIGH-Z
H
L
H
DOUT
HIGH-Z
H
H
L
DIN
HIGH-Z
H
Full Standby
H
Output Disable
X
Read from Flash (2)
L
Write to Flash
L
Read from SRAM
H
L
H
L
H
DOUT
HIGH-Z
H
Write to SRAM
H
L
H
X
L
DIN
HIGH-Z
H
Flash Hardware Reset
X
H
X
X
L
X
X
HIGH-Z
HIGH-Z
L
Table 3 User Bus Operations (BYTE=VIH)
Operation (1), (3)
CEf
CE1s
CE2s
H
X
X
L
X
X
H
X
X
L
H
X
X
L
OE
WE
DQ0 to DQ7 DQ8 to DQ15
X
X
HIGH-Z
HIGH-Z
H
H
H
HIGH-Z
HIGH-Z
H
L
H
DOUT
DOUT
H
H
L
DIN
DIN
H
Full Standby
H
Output Disable
X
Read from Flash (2)
L
Write to Flash
L
Read from SRAM
H
L
H
L
H
DOUT
HIGH-Z
H
Write to SRAM
H
L
H
X
L
DIN
HIGH-Z
H
Flash Hardware Reset
X
H
X
X
L
X
X
HIGH-Z
HIGH-Z
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes: 1. Other operations except for indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
4
RESET
MB84VD2002-10/MB84VD2003-10
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.
• Individual-sector, multiple-sector, or bulk-erase capability.
(×8)
(×16)
(×8)
FFFFFH 7FFFFH
16K byte/8K word
FFFFFH 7FFFFH
64K byte/32K word
FC000H 7E000H
32K byte/16K word
F0000H 78000H
64K byte/32K word
F4000H 7A000H
8K byte/4K word
E0000H 70000H
64K byte/32K word
F2000H 79000H
8K byte/4K word
Bank 1
D0000H 68000H
64K byte/32K word
F0000H 78000H
8K byte/4K word
C0000H 60000H
64K byte/32K word
EE000H 77000H
8K byte/4K word
B0000H 58000H
64K byte/32K word
EC000H 76000H
32K byte/16K word
A0000H 50000H
64K byte/32K word
E4000H 72000H Bank 2
16K byte/8K word
90000H 48000H
64K byte/32K word
E0000H 70000H
64K byte/32K word
80000H 40000H
64K byte/32K word
D0000H 68000H
64K byte/32K word
70000H 38000H
64K byte/32K word
C0000H 60000H
64K byte/32K word
60000H 30000H
64K byte/32K word
B0000H 58000H
64K byte/32K word
50000H 28000H
64K byte/32K word
A0000H 50000H
64K byte/32K word
40000H 20000H
64K byte/32K word
90000H 48000H
64K byte/32K word
30000H 18000H
64K byte/32K word
80000H 40000H
64K byte/32K word
20000H 10000H
16K byte/8K word
70000H 38000H
Bank 2
(×16)
64K byte/32K word
1C000H 0C000H
32K byte/16K word
60000H 30000H
64K byte/32K word
14000H 0A000H
8K byte/4K word
50000H 28000H
64K byte/32K word
12000H 09000H
8K byte/4K word
40000H 20000H Bank 1
64K byte/32K word
10000H 08000H
8K byte/4K word
30000H 18000H
64K byte/32K word
0E000H 07000H
8K byte/4K word
20000H 10000H
64K byte/32K word
0C000H 06000H
32K byte/16K word
10000H 08000H
64K byte/32K word
04000H 02000H
16K byte/8K word
00000H 00000H
MBM29DL800TA Sector Architecture
MB84VD2002 Sector Architecture
00000H 00000H
MBM29DL800BA Sector Architecture
MB84VD2003 Sector Architecture
5
MB84VD2002-10/MB84VD2003-10
Table 4
Sector Address Tables (MB84DV2002)
Sector Address
Bank
Sector
Bank
Address
Sector Size
(Kbytes/
Kwords)
(×8)
Address Range
(×16)
Address Range
A18 A17 A16 A15 A14 A13 A12
SA0
0
0
0
0
X
X
X
64/32
00000H to 0FFFFH
00000H to 07FFFH
SA1
0
0
0
1
X
X
X
64/32
10000H to 1FFFFH
08000H to 0FFFFH
SA2
0
0
1
0
X
X
X
64/32
20000H to 2FFFFH
10000H to 17FFFH
SA3
0
0
1
1
X
X
X
64/32
30000H to 3FFFFH
18000H to 1FFFFH
SA4
0
1
0
0
X
X
X
64/32
40000H to 4FFFFH
20000H to 27FFFH
SA5
0
1
0
1
X
X
X
64/32
50000H to 5FFFFH
28000H to 2FFFFH
SA6
0
1
1
0
X
X
X
64/32
60000H to 6FFFFH
30000H to 37FFFH
SA7
0
1
1
1
X
X
X
64/32
70000H to 7FFFFH
38000H to 3FFFFH
SA8
1
0
0
0
X
X
X
64/32
80000H to 8FFFFH
40000H to 47FFFH
SA9
1
0
0
1
X
X
X
64/32
90000H to 9FFFFH
48000H to 4FFFFH
SA10
1
0
1
0
X
X
X
64/32
A0000H to AFFFFH
50000H to 57FFFH
SA11
1
0
1
1
X
X
X
64/32
B0000H to BFFFFH
58000H to 5FFFFH
SA12
1
1
0
0
X
X
X
64/32
C0000H to CFFFFH
60000H to 67FFFH
SA13
1
1
0
1
X
X
X
64/32
D0000H to DFFFFH
68000H to 6FFFFH
SA14
1
1
1
0
0
0
X
16/8
E0000H to E3FFFH
70000H to 71FFFH
0
1
X
SA15
1
1
1
0
32/16
E4000H to E7FFFH, 72000H to 73FFFH,
E8000H to EBFFFH 74000H to 75FFFH
Bank 2
1
0
X
SA16
1
1
1
0
1
1
0
8/4
EC000H to EDFFFH 76000H to 76FFFH
SA17
1
1
1
0
1
1
1
8/4
EE000H to EFFFFH
77000H to 77FFFH
SA18
1
1
1
1
0
0
0
8/4
F0000H to F1FFFH
78000H to 78FFFH
SA19
1
1
1
1
0
0
1
8/4
F2000H to F3FFFH
79000H to 79FFFH
0
1
X
SA20
1
1
1
1
1
0
X
1
1
X
Bank 1
SA21
1
1
1
1
32/16
F4000H to F7FFFH, 7A000H to 7BFFFH,
F8000H to FBFFFH 7C000H to 7DFFFH
16/8
FC000H to FFFFFH 7E000H to 7FFFFH
Note:The address range is A18: A-1 if in byte mode (BYTE = VIL). The address range is A18: A0 if in word mode (BYTE
= VIH).
6
MB84VD2002-10/MB84VD2003-10
Table 5
Sector Address Tables (MB84DV2003)
Sector Address
Bank
Sector
Bank
Address
Sector Size
(Kbytes/
Kwords)
(×8)
Address Range
(×16)
Address Range
A18 A17 A16 A15 A14 A13 A12
SA21
1
1
1
1
X
X
X
64/32
F0000H to FFFFFH
78000H to 7FFFFH
SA20
1
1
1
0
X
X
X
64/32
E0000H to EFFFFH
70000H to 77FFFH
SA19
1
1
0
1
X
X
X
64/32
D0000H to DFFFFH
68000H to 6FFFFH
SA18
1
1
0
0
X
X
X
64/32
C0000H to CFFFFH
60000H to 67FFFH
SA17
1
0
1
1
X
X
X
64/32
B0000H to BFFFFH
58000H to 5FFFFH
SA16
1
0
1
0
X
X
X
64/32
A0000H to AFFFFH
50000H to 57FFFH
SA15
1
0
0
1
X
X
X
64/32
90000H to 9FFFFH
48000H to 4FFFFH
SA14
1
0
0
0
X
X
X
64/32
80000H to 8FFFFH
40000H to 47FFFH
SA13
0
1
1
1
X
X
X
64/32
70000H to 7FFFFH
38000H to 3FFFFH
SA12
0
1
1
0
X
X
X
64/32
60000H to 6FFFFH
30000H to 37FFFH
SA11
0
1
0
1
X
X
X
64/32
50000H to 5FFFFH
28000H to 2FFFFH
SA10
0
1
0
0
X
X
X
64/32
40000H to 4FFFFH
20000H to 27FFFH
SA9
0
0
1
1
X
X
X
64/32
30000H to 3FFFFH
18000H to 1FFFFH
SA8
0
0
1
0
X
X
X
64/32
20000H to 2FFFFH
10000H to 17FFFH
SA7
0
0
0
1
1
1
X
16/8
1C000H to 1FFFFH
0E000H to 0FFFFH
1
0
X
SA6
0
0
0
1
32/16
14000H to 17FFFH, 0A000H to 0BFFFH,
18000H to 1BFFFH 0C000H to 0DFFFH
Bank 2
0
1
X
SA5
0
0
0
1
0
0
1
8/4
12000H to 13FFFH
09000H to 09FFFH
SA4
0
0
0
1
0
0
0
8/4
10000H to 11FFFH
08000H to 08FFFH
SA3
0
0
0
0
1
1
1
8/4
0E000H to 0FFFFH
07000H to 07FFFH
SA2
0
0
0
0
1
1
0
8/4
0C000H to 0DFFFH
06000H to 06FFFH
1
0
X
SA1
0
0
0
0
0
1
X
0
0
X
Bank 1
SA0
0
0
0
0
32/16
08000H to 0BFFFH, 04000H to 05FFFH,
04000H to 07FFFH 02000H to 03FFFH
16/8
00000H to 03FFFH
00000H to 01FFFH
Note: The address range is A18: A-1 if in byte mode (BYTE = VIL). The address range is A18: A0 if in word mode
(BYTE = VIH).
7
MB84VD2002-10/MB84VD2003-10
Table 6. 1 Flash Memory Autoselect Codes
Type
Manufacturer’s Code
A6
A1
A0
A-1*1
Code (HEX)
VIL
VIL
VIL
VIL
04H
VIL
4AH
VIL
VIL
VIH
X
224AH
VIL
CBH
X
22CBH
Byte
MB84VD2002
Word
Device Code
Byte
MB84VD2003
VIL
VIL
VIH
Word
*1: A-1 is for Byte mode.
Table 6. 2 Expanded Autoselect Code Table
Type
Manufacturer’s Code
Device
Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04H A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
MB84VD2002 (B)
(W)
4AH
224AH
A-1
0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
MB84VD2003 (B)
(W)
CBH
22CBH
A-1
0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
(B): Byte mode
(W): Word mode
8
Code
MB84VD2002-10/MB84VD2003-10
Table 7
Command
Sequence
Read/Reset
Read/Reset
Word
Byte
Word
Byte
Bus
Write
Cycles
Req’d
1
3
Word
3
Autoselect
Byte
Program
Chip Erase
Sector Erase
Word
Byte
Word
Byte
Word
Byte
Erase Suspend
Erase Resume
Set to
Fast Mode
Word
Fast
Program *
Word
Reset from
Fast Mode *
Word
Extended
Sector
Protect
Byte
Byte
Byte
Word
Byte
4
6
6
1
1
3
2
2
4
Flash Memory Command Definitions
First Bus Second Bus Third Bus Fourth Bus
Fifth Bus
Sixth Bus
Write Cycle Write Cycle Write Cycle Read/Write
Write Cycle Write Cycle
Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
XXXH F0H
—
—
—
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
(BA)
555H
2AAH
555H
AAH
55H
(BA)
AAAH
555H
AAAH
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
BA
B0H
—
—
—
BA
30H
—
—
—
555H
2AAH
555H
AAH
55H
AAAH
555H
AAAH
XXXH
A0H
PA
PD
—
XXXH
BA
XXXH
90H
F0H
—
BA
XXXH
XXXH 60H
SPA
60H
SPA
—
—
—
—
—
—
—
F0H
RA
RD
—
—
—
—
90H
—
—
—
—
—
—
A0H
PA
PD
—
—
—
—
555H
2AAH
555H
AAH
55H
10H
AAAH
555H
AAAH
555H
2AAH
80H
AAH
55H
SA
30H
AAAH
555H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80H
20H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40H
SPA
SD
—
—
—
—
Notes: 1. Address bits A11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA), Sector
Address (SA), and Bank Address (BA).
2. Bus operations are defined in Tables 2 and 3.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank Address (A16 to A18)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at
unprotected sector addresses.
* : This command is valid while Fast Mode.
9
MB84VD2002-10/MB84VD2003-10
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. –55°C to +125°C
Ambient Temperature with Power Applied .................................................................. –25°C to +85°C
Voltage with Respect to Ground All pins (Note) .......................................................... –0.3 V to VCCf +0.5 V
–0.3 V to VCCs +0.5 V
VCCf/VCCs Supply (Note) .............................................................................................. –0.3 V to +4.6 V
Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negativeovershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf +0.5 V or VCCs
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Commercial Devices
Ambient Temperature (TA) .........................................................................–20°C to +85°C
VCCf/VCCs Supply Voltages.........................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
10
MB84VD2002-10/MB84VD2003-10
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
ILI
ILO
Input Leakage Current
Output Leakage Current
ICC1f
Test Conditions
VCCf = VCC Max.,
Flash VCC Active Current
CEf
= VIL
(Read)
OE = VIH
—
—
Byte
tCYCLE = 10 MHz
Word
Byte
tCYCLE = 5 MHz
Word
Min.
Typ.
Max.
Unit
–1.0
–1.0
—
—
—
—
—
—
—
—
—
—
+1.0
+1.0
18
20
8
10
µA
µA
—
35
—
—
—
—
45
45
45
45
—
35
mA
—
—
—
40
12
35
mA
mA
mA
—
6
mA
—
5
µA
—
5
µA
—
2
mA
1
2.5
µA
—
55
µA
1.5
3
µA
—
60
µA
1
2
µA
—
5
µA
—
50
µA
—
—
0.6
VCC+0.3*
V
V
—
0.4
V
—
—
V
—
2.5
V
Flash VCC Active Current
VCCf = VCC Max., CEf = VIL, OE = VIH
—
(Program/Erase)
Byte
—
Flash VCC Active Current
ICC3f*** (Read-While-Program) CE = VIL, OE = VIH
Word
—
Byte
—
Flash VCC Active Current
ICC4f***
CE = VIL, OE = VIH
(Read-While-Erase)
Word
—
Flash VCC Active Current
ICC5f (Erase-SuspendCE = VIL, OE = VIH
—
Program)
tCYCLE =10 MHz
—
VCCs = VCC Max.,
SRAM VCC Active
ICC1s
Current
CE1s = VIL, CE2s = VIH tCYCLE = 1 MHz
—
—
CE1s = 0.2 V,
tCYCLE = 10 MHz
ICC2s SRAM VCC Active
CE2s = VCCs – 0.2 V,
Current
tCYCLE = 1 MHz
—
WE = VCCs – 0.2 V
VCCf = VCC Max., CEf = VCCf ± 0.3 V
Flash VCC Standby
ISB1f
—
Current
RESET = VCCf ± 0.3 V
Flash VCC Standby
ISB2f
—
VCCf = VCC Max., RESET = VSS ± 0.3 V
Current (RESET)
SRAM VCC Standby
ISB1s
CE1s = VIH or CE2s = VIL
—
Current
—
VCCs TA = 25°C
= 3.0
TA = –20 to
V
—
±10% +85°C
VCCs TA = 25°C
—
= 3.3
TA = –20 to
SRAM VCC Standby
CE1s = VCC –0.2 V
—
ISB2s** Current
V or CE2s = 0.2 V ±0.3 +85°C
V
—
TA = 25°C
VCCs TA = –20 to
—
= 3.0 +40°C
V
TA = –20 to
—
+85°C
VIL
Input Low Level
—
–0.3
VIH
Input High Level
—
2.2
Output Low Voltage
IOL = 2.1 mA,
VOL
—
Level
VCCf = VCCs = VCC Min.
Output High Voltage
IOH = –500 µA,
VCC – 0.5
VOH
Level
VCCf = VCCs = VCC Min.
Flash Low VCC Lock-Out
VLKO
—
2.3
Voltage
ICC2f
* : VCC indicate lower of VCCf or VCCs
** :During standby mode with CE1s = VCCS – 0.2 V, CE2s should be CE2s < 0.2V or CE2s > VCCS – 0.2V
*** :Embeded Algorithm (program or erase) is in progress. (@5 MHz)
mA
mA
mA
mA
11
MB84VD2002-10/MB84VD2003-10
■ AC CHARACTERISTICS
• CE Timing
Parameter
Symbols
JEDEC
Standard
—
tCCR
Description
Test Setup
CE Recover Time
—
-10
Unit
0
ns
Min.
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
tCCR
tCCR
CE1s
CE2s
• Read Only Operations Characteristics (Flash)
Parameter
Symbols
Description
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
tELQV
Unit
Min.
Max.
—
100
—
ns
Address to Output Delay
CEf = VIL
OE = VIL
—
100
ns
tCEf
Chip Enable to Output Delay
OE = VIL
—
100
ns
tGLQV
tOE
Output Enable to Output Delay
—
—
40
ns
tEHQZ
tDF
Chip Enable to Output High-Z
—
—
30
ns
tGHQZ
tDF
Output Enable to Output High-Z
—
—
30
ns
tAXQX
tOH
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
—
0
—
ns
—
tREADY
RESET Pin Low to Read Mode
—
—
20
µs
—
tELFL
tELFH
CE or BYTE Switching Low or High
—
—
5
ns
Note: Test Conditions–Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
12
-10
(Note)
Test
Setup
MB84VD2002-10/MB84VD2003-10
• Read Cycle (Flash)
tRC
Addresses Stable
ADDRESSES
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCE
HIGH-Z
DQ
HIGH-Z
Output Valid
tRC
ADDRESSES
Addresses Stable
tACC
tRH
RESET
tOH
DQ
HIGH-Z
Output Valid
13
MB84VD2002-10/MB84VD2003-10
• Erase/Program Operations (Flash)
Parameter Symbols
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
tAVEL
Description
Unit
Typ.
Max.
100
—
—
ns
Address Setup Time (WE to Addr.)
0
—
—
ns
tAS
Address Setup Time (CEf to Addr.)
0
—
—
ns
—
tASO
Address Setup Time to OE Low During Toggle Bit
Polling
15
—
—
ns
tWLAX
tAH
Address Hold Time (WE to Addr.)
50
—
—
ns
tELAX
tAH
Address Hold Time (CEf to Addr.)
50
—
—
ns
—
tAHT
Address Hold Time from CE or OE High During Toggle
Bit Polling
0
—
—
ns
tDVWH
tDS
Data Setup Time
50
—
—
ns
tWHDX
tDH
Data Hold Time
0
—
—
ns
—
tOEH
Output Enable Hold Time
0
—
—
ns
10
—
—
ns
—
tCEPH
CE High During Toggle Bit Polling
20
—
—
ns
—
tOEPH
OE High During Toggle Bit Polling
20
—
—
ns
tGHEL
tGHEL
Read Recover Time Before Write (OE to CEf)
0
—
—
ns
tGHWL
tGHWL
Read Recover Time Before Write (OE to WE)
0
—
—
ns
tWLEL
tWS
WE Setup Time (CEf to WE)
0
—
—
ns
tELWL
tCS
CEf Setup Time (WE to CEf)
0
—
—
ns
tEHWH
tWH
WE Hold Time (CEf to WE)
0
—
—
ns
Read
Toggle and Data Polling
tWHEH
tCH
CEf Hold Time (WE to CEf)
0
—
—
ns
tWLWH
tWP
Write Pulse Width
50
—
—
ns
tELEH
tCP
CEf Pulse Width
50
—
—
ns
tWHWL
tWPH
Write Pulse Width High
30
—
—
ns
tEHEL
tCPH
CEf Pulse Width High
30
—
—
ns
tWHWH1
tWHWH1
Byte Programming Operation
—
8
—
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
—
1
—
sec
—
—
15
sec
—
tVCS
VCCf Setup Time
50
—
—
µs
—
tVLHT
Voltage Transition Time (Note 2)
4
—
—
µs
—
tVIDR
Rise Time to VID (Note 2)
500
—
—
ns
—
tRB
Recover Time from RY/BY
0
—
—
ns
—
tRP
RESET Pulse Width
500
—
—
ns
—
tRH
RESET Hold Time Before Read
200
—
—
ns
—
tEOE
Delay Time from Embedded Output Enable
—
—
100
ns
—
tBUSY
Program/Erase Valid to RY/BY Delay
—
—
90
ns
—
tFLQZ
BYTE Switching Low to Output High-Z
—
—
30
ns
—
tFHQV
BYTE Switching High to Output Active
30
—
—
ns
Note : 1. This does not include the preprogramming time.
2. This timing is for Sector Protection Operation.
14
-10
Min.
MB84VD2002-10/MB84VD2003-10
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555H
ADDRESSES
tWC
PA
tAS
PA
tRC
tAH
CEf
tCH
tCS
tCO
OE
tGHWL
tWP
tFOE
tWHWH1
tWPH
WE
tOH
tDS
tDH
DQ
Notes: 1.
2.
3.
4.
5.
6.
A0H
PD
DQ7
DOUT
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence
These waveforms are for the x16 mode. The addresses differ from x8 mode.
15
MB84VD2002-10/MB84VD2003-10
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
ADDRESSES
Data Polling
PA
555H
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tWHWH1
tCPH
CEf
tDS
tDH
DQ
Notes: 1.
2.
3.
4.
5.
6.
16
A0H
PD
DQ7
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence
These waveforms are for the x16 mode. The addresses differ from x8 mode.
MB84VD2002-10/MB84VD2003-10
• AC Waveforms Chip/Sector Erase Operations (Flash)
2AAH
555H
ADDRESSES
tWC
tAS
555H
555H
2AAH
SA*1
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
WE
tDS
tDH
AAH
DQ
30H for Sector Erase
55H
80H
AAH
55H
10H/
30H
tVCS
VCC
Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H forChip Erase.
2. These waveforms are for the x16 mode. The addresses differ from x8 mode.
17
MB84VD2002-10/MB84VD2003-10
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
DQ7
Data
DQ7 =
Valid Data
DQ7
High-Z
t WHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6
Valid Data
DQ0 to DQ6 = Output Flag
t BUSY
High-Z
t EOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation).
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
18
Output
Valid
MB84VD2002-10/MB84VD2003-10
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
• Timing Diagram for Word Mode Configuration (Flash)
CE
BYTE
Data Output
(DQ0 to DQ7)
DQ0 to DQ14
tELFH
DQ15/A-1
Data Output
(DQ0 to DQ14)
tFHQV
A-1
DQ15
19
MB84VD2002-10/MB84VD2003-10
• Timing Diagram for Byte Mode Configuration (Flash)
CE
BYTE
DQ0 to DQ14
tELFL
Data Output
(DQ0 to DQ7)
Data Output
(DQ0 to DQ14)
DQ15/A-1
DQ15
A-1
tFLQZ
• BYTE Timing Diagram for Write Operations (Flash)
The falling edge of the last WE signal
CE or WE
Input
Valid
BYTE
tSET
(tAS)
tHOLD
(tAH)
• Temporary Sector Unprotection (Flash)
VCC
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
20
tVLHT
MB84VD2002-10/MB84VD2003-10
• Back-to-back Read/Write Timing Diagram
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA2
(PA)
BA1
BA2
(PA)
BA2
(555H)
BA1
tAS
BA1
tACC
tAH
tAS
tAHT
tCE
CE
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Intput
(A0H)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
21
MB84VD2002-10/MB84VD2003-10
• Extended Sector Protection (Flash)
VCC
tVCS
RESET
tVLHT
tVIDR
Add
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
WE
Data
60H
60H
40H
01H
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (min)
22
60H
MB84VD2002-10/MB84VD2003-10
• Read Cycle (SRAM)
Parameter
Symbol
Parameter Description
Min.
Max.
Unit
100
—
ns
tRC
Read Cycle Time
tAA
Address Access Time
—
100
ns
tCO1
Chip Enable (CE1s) Access Time
—
100
ns
tCO2
Chip Enable (CE2s) Access Time
—
100
ns
tOE
Output Enable Access Time
—
50
ns
tCOE
Chip Enable (CE1s Low and CE2s High) to Output Active
5
—
ns
tOEE
Output Enable Low to Output Active
0
—
ns
tOD
Chip Enable (CE1s High or CE2s Low) to Output High-Z
—
40
ns
tODO
Output Enable High to Output High-Z
—
40
ns
tOH
Output Data Hold Time
10
—
ns
• Read Cycle (Note 1) (SRAM)
tRC
ADDRESSES
tAA
tOH
tCO1
CE1s
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
tOEE
tODO
tCOE
DQ
VALID DATA OUT
Note: 1. WE remains HIGH for the read cycle.
23
MB84VD2002-10/MB84VD2003-10
•
Write Cycle (SRAM)
Parameter
Symbol
Parameter Description
Min.
Max.
Unit
tWC
Write Cycle Time
100
—
ns
tWP
Write Pulse Width
60
—
ns
tCW
Chip Enable to End of Write
80
—
ns
tAS
Address Setup Time
0
—
ns
tWR
Write Recovery Time
0
—
ns
tODW
WE Low to Output High-Z
—
40
ns
tOEW
WE High to Output Active
0
—
ns
tDS
Data Setup Time
40
—
ns
tDH
Data Hold Time
0
—
ns
• Write Cycle (Note 4) (WE control) (SRAM)
tWC
ADDRESSES
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
DOUT
tCW
tODW
tOEW
Note 2
Note 3
tDS
DIN
Note 5
tDH
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
24
MB84VD2002-10/MB84VD2003-10
• Write Cycle (Note 4) (CE1s control) (SRAM)
tWC
ADDRESSES
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
tCW
tCOE
tODW
DOUT
tDS
DIN
Note 5
tDH
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
25
MB84VD2002-10/MB84VD2003-10
• Write Cycle (Note 4) (CE2s Control) (SRAM)
tWC
ADDRESSES
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
tCW
tCOE
tODW
DOUT
tDS
DIN
Note 5
tDH
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
26
MB84VD2002-10/MB84VD2003-10
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits
Parameter
Unit
Comment
Min.
Typ.
Max.
Sector Erase Time
—
1
10
sec
Byte Programming Time
—
8
300
µs
Word Programming Time
—
16
360
µs
Chip Programming Time
—
8.4
T.B.D
sec
100,000
—
—
cycles
Erase/Program Cycle
Excludes programming time
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead
■ DATA RETENTION CHARACTERISTICS (SRAM)
Parameter
Symbol
Parameter Description
Min.
Typ.
Max.
Unit
2.0
—
3.6
V
VDH = 3.0 V
—
—
50*
µA
VDH = 3.6 V
—
—
60
µA
Chip Deselect to Data Retention Mode Time
0
—
—
ns
Recovery Time
5
—
—
ms
VDH
Data Retention Supply Voltage
IDDS2
Standby Current
tCDR
tR
* : 5 µA (Max.) at TA = –20°C to +40°C
• CE1s Controlled Data Retention Mode (Note 1)
VCCs
DATA RETENTION MODE
2.7 V
See Note 2
See Note 2
VIH
CE1s
VCCS –0.2 V
tCDR
tR
GND
27
MB84VD2002-10/MB84VD2003-10
• CE2s Controlled Data Retention Mode (Note 3)
VCCs
DATA RETENTION MODE
2.7 V
VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss
to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to
Vccs+0.3V.
2. When CE1s is operating at the VIH min. level (2.2 V), the standby current is given by ISB1s during the
transition of VCCs from 3.6 to 2.2 V.
3. In CE2s controlled data retention mode, input and input/output pins can be used between between
-0.3V to Vccs+0.3V.
■ PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
T.B.D
T.B.D
pF
COUT
Output Capacitance
VOUT = 0
T.B.D
T.B.D
pF
CIN2
Control Pin Capacitance
VIN = 0
T.B.D
T.B.D
pF
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
■ CAUTION
1.)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
2.)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the
sector useing "Extended sector protect" command.
28
MB84VD2002-10/MB84VD2003-10
■ PACKAGE
48-pin plastic FBGA
(BGA-48P-M06)
■ PACKAGE DIMENSIONS
48-pin plastic BGA
(BGA-48P-M06)
Note: The actual shape of coners may differ from the dimension.
11.00±0.15(.433±.006)
1.40±0.20
(.055±.008)
0.30±0.10
(.012±.004)
10.00±0.15
(.394±.006)
7.00±0.15(.276±.006)
Ø0.40±0.10
(Ø.016±.004)
5.00±0.15
(.197±.006)
0.15(.006)
1st PIN
INDEX
C
1998 FUJITSU LIMITED MCM-M001-2-3
1.00±0.15
(.039±.006)
INDEX
Dimension in mm (inches).
29
MB84VD2002-10/MB84VD2003-10
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9805
 FUJITSU LIMITED Printed in Japan
30
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.