FUJITSU SEMICONDUCTOR DATA SHEET DS05-20908-2E FLASH MEMORY CMOS 32 M (4 M × 8/2 M × 16) BIT Dual Operation MBM29DL34TF/BF 70 ■ DESCRIPTION The MBM29DL34TF/BF are a 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) ■ PRODUCT LINE UP MBM29DL34TF/BF Part No. 70 Power Supply Voltage (V) 2.7 V to 3.6 V Max Address Access Time (ns) 70 Max CE Access Time (ns) 70 Max OE Access Time (ns) 30 ■ PACKAGES 48-pin plastic TSOP (1) 48-ball plastic FBGA Marking side (FPT-48P-M19) (BGA-48P-M12) MBM29DL34TF/BF70 ) (Continued) MBM29DL34TF/BF are organized into two physical banks; Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the device, a design concept called Sliding Bank Architecture is implemented. Using this concept the device can execute simultaneous operation between Bank 1 and Bank 2(Refer to “1. Simultaneous Operation” in “■ FUNCTIONAL DESCRIPTION”.). The standard device offers access times 70 ns allowing operation of high-speed microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable (OE) controls. The MBM29DL34TF/BF support pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin. Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) . The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally return to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the Embedded ProgramTM * Algorithm or Embedded EraseTM * Algorithm, the device is automatically reset to the read mode and have erroneous data stored in the address locations being programmed or erased. These locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/ word at a time using the EPROM programming mechanism of hot electron injection. *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29DL34TF/BF70 ■ FEATURES • 0.17 µm Process Technology • Simultaneous Read/Write Operations (Dual Bank) Bank 1 : 8 Mbit Bank 2 : 24 Mbit Host system can program or erase in one bank, then immediately and simultaneously read and from the other bank. Zero latency between read and write operation. Read - while - erase Read - while - program • Single 3.0 V Read, Program, and Erase Minimizes system level power requirements • Compatible with JEDEC-standard Commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard World-wide Pinouts 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 48-ball FBGA (Package suffix : PBT) • Minimum 100,000 Program/Erase Cycles • High Performance 70 ns maximum access time • Sector Erase Architecture Eight 4 K word and sixty-three 32 K word sectors in word mode Eight 8 K byte and sixty-three 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device (Continued) 3 MBM29DL34TF/BF70 (Continued) • Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. Bank and Sector Organization Table 4 Device Part Number Bank 1 Bank 2 MBM29DL34TF Bank A (SA70 to 48) Bank B (SA47 to 0) MBM29DL34BF Bank A (SA0 to 22) Bank B (SA23 to 70) MBM29DL34TF/BF70 ■ PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) Normal Bend 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 (FPT-48P-M19) (Continued) 5 MBM29DL34TF/BF70 (Continued) FBGA (TOP VIEW) Marking side A6 B6 C6 D6 E6 A13 A12 A14 A15 A16 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 G6 H6 VSS A4 B4 C4 D4 E4 F4 G4 H4 WE RESET N.C. A19 DQ5 DQ12 VCC DQ4 A3 B3 RY/BY WP/ACC C3 D3 E3 F3 G3 H3 A18 A20 DQ2 DQ10 DQ11 DQ3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE OE VSS (BGA-48P-M12) 6 F6 BYTE DQ15/A-1 MBM29DL34TF/BF70 ■ PIN DESCRIPTION Pin Function A20 to A0, A-1 Address Input DQ15 to DQ0 Data Input/Output CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection BYTE WP/ACC Selects Byte (8-bit) or Word (16-bit) mode Hardware Write Protection/Program Acceleration VCC Device Power Supply VSS Device Ground N.C. No Internal Connection ■ LOGIC SYMBOL A-1 21 A20 to A0 16 or 8 DQ15 to DQ0 CE OE WE RESET RY/BY BYTE WP/ACC 7 MBM29DL34TF/BF70 ■ BLOCK DIAGRAM Cell Matrix Bank 2 Address A20 to A0 (A-1) (Bank 2) Y-Gating & Data Latch VCC VSS X-Decoder RY/BY State Control & Command Register Status DQ15 to DQ0 Control X-Decoder Bank 1 Address Cell Matrix (Bank 1) 8 Y-Gating & Data Latch RESET WE CE OE BYTE WP/ACC DQ15 to DQ0 MBM29DL34TF/BF70 ■ DEVICE BUS OPERATION MBM29DL34TF/BF User Bus Operations Table (Word Mode : BYTE = VIH) Operation CE OE WE A0 A1 A2 A3 A6 A9 DQ15 to DQ0 RESET WP/ ACC Standby H X X X X X X X X High-Z H X Autoselect Manufacturer Code *1 L L H L L L L L VID Code H X Autoselect Device Code *1 L L H H L L L L VID Code H X Extended Auto-Select Device Code *1 L L H L H H H L VID Code H X L L H H H H H L VID Code H X 3 L L H A0 A1 A2 A3 A6 A9 DOUT H X Output Disable L H H X X X X X X High-Z H X Write (Program/Erase) L H L A0 A1 A2 A3 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L L H L L L VID X H X Verify Sector Group Protection *2, *4 L L H L H L L L VID Code H X Temporary Sector Group Unprotection *5 X X X X X X X X X X VID X Reset (Hardware) X X X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X X X L Read * Legend : L = VIL, H = VIH, X = VIL or VIH, See “■ DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29DL34TF/BF Command Definitions Table”. *2: Refer to section on “8. Sector Group Protection” in ■ FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 2.7 V to 3.6 V *5: Also used for extended sector group protection. 9 MBM29DL34TF/BF70 MBM29DL34TF/BF User Bus Operations Table (Byte Mode : BYTE = VIL) Operation CE OE WE DQ15 /A-1 A0 A1 A2 A3 A6 A9 DQ7 to DQ0 RESET Standby H X X X X X X X X X High-Z H X Autoselect Manufacturer Code *1 L L H L L L L L L VID Code H X Autoselect Device Code *1 L L H L H L L L L VID Code H X L L H L L H H H L VID Code H X Extended Auto-Select Device Code *1 L L H L H H H H L VID Code H X 3 L L H A-1 A0 A1 A2 A3 A6 A9 DOUT H X Output Disable L H H X X X X X X X High-Z H X Write (Program/Erase) L H L A-1 A0 A1 A2 A3 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L L L H L L L VID X H X Verify Sector Group Protection *2, *4 L L H L L H L L L VID Code H X Temporary Sector Group Unprotection *5 X X X X X X X X X X X VID X Reset (Hardware) X X X X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X X X X L Read * Legend : L = VIL, H = VIH, X = VIL or VIH, See “■ DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29DL34TF/BF Command Definitions Table”. *2: Refer to section on “8. Sector Group Protection” in ■ FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 2.7 V to 3.6 V *5: Also used for extended sector group protection. 10 WP/ ACC MBM29DL34TF/BF70 MBM29DL34TF/BF Command Definitions Table *1 Bus write cycles req’d Command sequence Reset *2 Reset *2 Autoselect (Device ID) Program Word Byte Word Byte 1 3 Word First bus write cycle Addr. Data Addr. Data XXXh F0h 555h AAAh 4 Word Byte AAh 555h Byte 2AAh 555h AAh 555h AAAh 55h 2AAh AAAh 4 Second bus write cycle 55h 555h AAh 2AAh 555h 55h Third bus write cycle Addr. 555h AAAh (BA) 555h (BA) AAAh 555h AAAh Fourth bus Fifth bus Sixth bus read/write write cycle write cycle cycle Data Addr. Data Addr. Data Addr. Data F0h RA RD 90h 00h 04h A0h PA PD Program Suspend 1 BA B0h Program Resume 1 BA 30h Chip Erase Sector Erase Word Byte Word Byte Erase Suspend *3 Erase Resume * 3 Set to Fast Mode Word Fast Program *4 Word Byte Byte 6 6 2AAh 555h 55h 555h AAAh 555h AAAh 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h 1 BA 30h 20h 3 2 4 Word 1 Byte Byte AAAh AAh 555h 55h B0h Extended Word Sector Group Protection Byte *6,*7 Word 555h 2AAh BA 2 HiddenROM Entry *9 AAAh AAh 1 Word Reset from 5 Fast Mode * Byte Query *8 555h 3 555h AAAh XXXh XXXh BA BA AAh A0h 90h XXXh 60h (BA) 55h (BA) AAh 555h AAAh 98h AAh 2AAh 555h 55h 555h AAAh PD 00h*11 SGA 60h SGA 40h SGA SD 88h PA XXXh XXXh 2AAh 555h 55h 555h AAAh (Continued) 11 MBM29DL34TF/BF70 (Continued) Command sequence HiddenRom Program *10 HiddenRom Exit *10 Word Byte Bus write cycles req’d 4 Word Third bus write cycle Fourth bus read/write cycle Addr. Data Addr. Data Addr. Data Addr. 555h 555h A0h (HRA) PA PD 90h XXXh 00h First bus write cycle AAAh 555h 4 Byte AAh Second bus write cycle 2AAh 555h 55h 2AAh AAh AAAh 55h 555h AAAh (HRBA) 555h (HRBA) AAAh Fifth bus Sixth bus write cycle write cycle Data Addr. Data Addr. Data *1 : The command combinations not described in “MBM29DL34TF/BF Command Definitions Table” are illegal. *2 : Both of these reset commands are equivalent. *3 : Erase Suspend and Erase Resume command are valid only during a sector erase operation. *4 : This command is valid during Fast Mode. *5 : The Reset from Fast Mode command is required to return to the read mode when the device is in Fast Mode. *6 : This command is valid while RESET = VID (except during HiddenROM mode). *7 : Sector Group Address (SGA) with (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . *8 : The valid address are A6 to A0. *9 : The HiddenROM Entry command is required prior to the HiddenROM programming. *10 : This command is valid during HiddenROM mode. *11 : The date “F0h” is also acceptable. Notes: • Address bits A20 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector Address (SA) , Bank Address (BA) . • Bus operations are defined in “MBM29DL34TF/BF User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” (■ DEVICE BUS OPERATION). • RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A20 to A18) • RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. • SGA = Sector Group Address. The combination of A20 to A12 will uniquely select any sector group. SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. • HRA = Address of the HiddenROM area 29DL34TF (Top Boot Type) Word Mode : 1FF000h to 1FF07Fh Byte Mode : 3FE000h to 3FE0FFh 29DL34BF (Bottom Boot Type) Word Mode : 000000h to 00007Fh Byte Mode : 000000h to 0000FFh • HRBA = Bank Address of the HiddenROM area 29DL34TF (Top Boot Type) : A20 = A19 = A18 = 1 29DL34BF (Bottom Boot Type) : A20 = A19 = A18 = 0 • The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1 • Both Reset commands are functionally equivalent, resetting the device to the read mode. 12 MBM29DL34TF/BF70 Type MBM29DL34TF Sector Group Protection Verify Autoselect Codes Table A6 A3 A2 A1 A0 A20 to A12 A-1*1 3 BA* VIL VIL VIL VIL VIL BA*3 VIL VIL VIL VIL VIH Sector Group Addresses VIL VIL VIL VIH VIL Manufacture’s Code Device Code Byte Word Sector Group Protection Code (HEX) VIL 04h VIL 50h X 2250h VIL 01h*2 *1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. MBM29DL34TF Extended Autoselect Code Table Type Code Manufacture’s Code Device Code Byte* 04h 01h DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HZ HZ HZ HZ HZ HZ HZ 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A-1/0 50Eh A-1 Word 2250Eh Sector Group Protection DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 HZ: High-Z * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. 13 MBM29DL34TF/BF70 Type MBM29DL34BF Sector Group Protection Verify Autoselect Codes Table A6 A3 A2 A1 A0 A20 to A12 A-1*1 Manufacture’s Code Device Code Byte Word Sector Group Protection BA*3 VIL VIL VIL VIL VIL BA*3 VIL VIL VIL VIL VIH Sector Group Addresses VIL VIL VIL VIH VIL Code (HEX) VIL 04h VIL 53h X 2253h VIL 01h*2 *1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. MBM29DL34BF Extended Autoselect Code Table Type Code Manufacture’s Code Device Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Byte* 53h A-1 HZ HZ HZ HZ HZ HZ HZ 0 1 0 1 0 0 1 1 Word 2253h 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 01h A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Sector Group Protection HZ: High-Z * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. 14 MBM29DL34TF/BF70 ■ SECTOR-ERASE ARCHITECTURE Bank Sector A20 Bank 2 Sector Address Table (MBM29DL34TF) Sector address Sector ×8) size (× Bank address (Kbytes/ Address range A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) ×16) (× Address range SA0 0 0 0 0 0 0 X X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA9 0 0 1 0 0 1 X X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA17 0 1 0 0 0 1 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh SA32 1 0 0 0 0 0 X X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh 15 MBM29DL34TF/BF70 Sector address Bank Sector Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 Bank 1 Sector size (Kbytes/ Kwords) ×8) (× Address range ×16) (× Address range SA33 1 0 0 0 0 1 X X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA35 1 0 0 0 1 1 X X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA45 1 0 1 1 0 1 X X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA63 1 1 1 1 1 1 0 0 0 X 8/4 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 X 8/4 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh SA65 1 1 1 1 1 1 0 1 0 X 8/4 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh SA66 1 1 1 1 1 1 0 1 1 X 8/4 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh (Continued) 16 MBM29DL34TF/BF70 (Continued) Sector address Bank Sector Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 Sector size (Kbytes/ Kwords) ×8) (× Address range ×16) (× Address range SA67 1 1 1 1 1 1 1 0 0 X 8/4 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh SA68 1 1 1 1 1 1 1 0 1 X 8/4 3FA000h to 3FBFFFh 1FD000h to 1FDFFFh SA69 1 1 1 1 1 1 1 1 0 X 8/4 3FC000h to 3FDFFFh 1FE000h to 1FEFFFh SA70 1 1 1 1 1 1 1 1 1 X 8/4 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) . The address range is A20 : A0 if in word mode (BYTE = VIH) . Bank Sector A20 Bank 2 Sector Address Table (MBM29DL34BF) Sector address Sector ×8) size (× Bank address (Kbytes/ Address range A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) ×16) (× Address range SA70 1 1 1 1 1 1 X X X X 64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh SA69 1 1 1 1 1 0 X X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA68 1 1 1 1 0 1 X X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA67 1 1 1 1 0 0 X X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA66 1 1 1 0 1 1 X X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA65 1 1 1 0 1 0 X X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA64 1 1 1 0 0 1 X X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA63 1 1 1 0 0 0 X X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA62 1 1 0 1 1 1 X X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh SA61 1 1 0 1 1 0 X X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh SA60 1 1 0 1 0 1 X X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA59 1 1 0 1 0 0 X X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA58 1 1 0 0 1 1 X X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA57 1 1 0 0 1 0 X X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA56 1 1 0 0 0 1 X X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA55 1 1 0 0 0 0 X X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh SA54 1 0 1 1 1 1 X X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA53 1 0 1 1 1 0 X X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh SA52 1 0 1 1 0 1 X X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA51 1 0 1 1 0 0 X X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA50 1 0 1 0 1 1 X X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA49 1 0 1 0 1 0 X X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh (Continued) 17 MBM29DL34TF/BF70 Sector address Bank Sector Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 Bank 1 Sector size (Kbytes/ Kwords) ×8) (× Address range ×16) (× Address range SA48 1 0 1 0 0 1 X X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA47 1 0 1 0 0 0 X X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA46 1 0 0 1 1 1 X X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA45 1 0 0 1 1 0 X X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA44 1 0 0 1 0 1 X X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA43 1 0 0 1 0 0 X X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA42 1 0 0 0 1 1 X X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA41 1 0 0 0 1 0 X X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA40 1 0 0 0 0 1 X X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA39 1 0 0 0 0 0 X X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh SA38 0 1 1 1 1 1 X X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh SA37 0 1 1 1 1 0 X X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA36 0 1 1 1 0 1 X X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA35 0 1 1 1 0 0 X X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA34 0 1 1 0 1 1 X X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA33 0 1 1 0 1 0 X X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA32 0 1 1 0 0 1 X X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA31 0 1 1 0 0 0 X X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA30 0 1 0 1 1 1 X X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA29 0 1 0 1 1 0 X X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA28 0 1 0 1 0 1 X X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA27 0 1 0 1 0 0 X X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA26 0 1 0 0 1 1 X X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA25 0 1 0 0 1 0 X X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA24 0 1 0 0 0 1 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA23 0 1 0 0 0 0 X X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA22 0 0 1 1 1 1 X X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA21 0 0 1 1 1 0 X X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA20 0 0 1 1 0 1 X X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA19 0 0 1 1 0 0 X X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA18 0 0 1 0 1 1 X X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA17 0 0 1 0 1 0 X X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA16 0 0 1 0 0 1 X X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA15 0 0 1 0 0 0 X X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh (Continued) 18 MBM29DL34TF/BF70 (Continued) Sector address Bank Sector Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 Sector size (Kbytes/ Kwords) ×8) (× Address range ×16) (× Address range SA14 0 0 0 1 1 1 X X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA13 0 0 0 1 1 0 X X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA12 0 0 0 1 0 1 X X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA11 0 0 0 1 0 0 X X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA10 0 0 0 0 1 1 X X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA9 0 0 0 0 1 0 X X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA8 0 0 0 0 0 1 X X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA7 0 0 0 0 0 0 1 1 1 X 8/4 00E000h to 00FFFFh 007000h to 007FFFh SA6 0 0 0 0 0 0 1 1 0 X 8/4 00C000h to 00DFFFh 006000h to 006FFFh SA5 0 0 0 0 0 0 1 0 1 X 8/4 00A000h to 00BFFFh 005000h to 005FFFh SA4 0 0 0 0 0 0 1 0 0 X 8/4 008000h to 009FFFh 004000h to 004FFFh SA3 0 0 0 0 0 0 0 1 1 X 8/4 006000h to 007FFFh 003000h to 003FFFh SA2 0 0 0 0 0 0 0 1 0 X 8/4 004000h to 005FFFh 002000h to 002FFFh SA1 0 0 0 0 0 0 0 0 1 X 8/4 002000h to 003FFFh 001000h to 001FFFh SA0 0 0 0 0 0 0 0 0 0 X 8/4 000000h to 001FFFh 000000h to 000FFFh Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) . The address range is A20 : A0 if in word mode (BYTE = VIH) . 19 MBM29DL34TF/BF70 Sector group A20 A19 SGA0 0 0 SGA1 0 0 0 0 0 0 0 0 1 1 0 1 1 A12 Sectors X X X SA0 X X X SA1 to SA3 SGA2 0 0 0 1 X X X X X SA4 to SA7 SGA3 0 0 1 0 X X X X X SA8 to SA11 SGA4 0 0 1 1 X X X X X SA12 to SA15 SGA5 0 1 0 0 X X X X X SA16 to SA19 SGA6 0 1 0 1 X X X X X SA20 to SA23 SGA7 0 1 1 0 X X X X X SA24 to SA27 SGA8 0 1 1 1 X X X X X SA28 to SA31 SGA9 1 0 0 0 X X X X X SA32 to SA35 SGA10 1 0 0 1 X X X X X SA36 to SA39 SGA11 1 0 1 0 X X X X X SA40 to SA43 SGA12 1 0 1 1 X X X X X SA44 to SA47 SGA13 1 1 0 0 X X X X X SA48 to SA51 SGA14 1 1 0 1 X X X X X SA52 to SA55 SGA15 1 1 1 0 X X X X X SA56 to SA59 0 0 0 1 X X X SA60 to SA62 1 0 SGA16 20 0 Sector Group Addresses Table (MBM29DL34TF) A18 A17 A16 A15 A14 A13 1 1 1 1 SGA17 1 1 1 1 1 1 0 0 0 SA63 SGA18 1 1 1 1 1 1 0 0 1 SA64 SGA19 1 1 1 1 1 1 0 1 0 SA65 SGA20 1 1 1 1 1 1 0 1 1 SA66 SGA21 1 1 1 1 1 1 1 0 0 SA67 SGA22 1 1 1 1 1 1 1 0 1 SA68 SGA23 1 1 1 1 1 1 1 1 0 SA69 SGA24 1 1 1 1 1 1 1 1 1 SA70 MBM29DL34TF/BF70 Sector Group Addresses Table (MBM29DL34BF) A18 A17 A16 A15 A14 A13 Sector group A20 A19 SGA0 0 0 0 0 0 0 0 SGA1 0 0 0 0 0 0 SGA2 0 0 0 0 0 SGA3 0 0 0 0 SGA4 0 0 0 SGA5 0 0 SGA6 0 SGA7 0 SGA8 0 A12 Sectors 0 0 SA0 0 0 1 SA1 0 0 1 0 SA2 0 0 0 1 1 SA3 0 0 0 1 0 0 SA4 0 0 0 0 1 0 1 SA5 0 0 0 0 0 1 1 0 SA6 0 0 0 0 0 1 1 1 SA7 0 1 1 0 X X X SA8 to SA10 1 1 0 0 0 SGA9 0 0 0 1 X X X X X SA11 to SA14 SGA10 0 0 1 0 X X X X X SA15 to SA18 SGA11 0 0 1 1 X X X X X SA19 to SA22 SGA12 0 1 0 0 X X X X X SA23 to SA26 SGA13 0 1 0 1 X X X X X SA27 to SA30 SGA14 0 1 1 0 X X X X X SA31 to SA34 SGA15 0 1 1 1 X X X X X SA35 to SA38 SGA16 1 0 0 0 X X X X X SA39 to SA42 SGA17 1 0 0 1 X X X X X SA43 to SA46 SGA18 1 0 1 0 X X X X X SA47 to SA50 SGA19 1 0 1 1 X X X X X SA51 to SA54 SGA20 1 1 0 0 X X X X X SA55 to SA58 SGA21 1 1 0 1 X X X X X SA59 to SA62 SGA22 1 1 1 0 X X X X X SA63 to SA66 0 0 0 1 X X X SA67 to SA69 1 0 1 1 X X X SA70 SGA23 SGA24 1 1 1 1 1 1 1 1 21 MBM29DL34TF/BF70 Common Flash Memory Interface Code Table Description A6 to A0 DQ15 to DQ0 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 02h : AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended Table 19h 1Ah 0000h 0000h VCC Min (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV 1Bh 0027h VCC Max (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV 1Ch 0036h VPP Min voltage 1Dh 0000h 1Eh 0000h Typical timeout per single byte/word write 2 µs 1Fh 0004h Typical timeout for Min size buffer write 2 µs 20h 0000h N 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h Max timeout for full chip erase 2 times typical 26h 0000h Device Size = 2 byte 27h 0016h 02h : Supports ×8 and ×16 via BYTE with asynchronous interface. 28h 29h 0002h 0000h Max number of bytes in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0002h Erase Block Region 1 Information bit 0 to 15 : y = number of sectors bit 16 to 31 : z = size (z × 256 bytes) 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 2 Information bit 0 to 15 : y = number of sectors bit 16 to 31 : z = size (z × 256 bytes) 31h 32h 33h 34h 003Eh 0000h 0000h 0001h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h VPP Max voltage N N Typical timeout per individual sector erase 2 ms N Typical timeout for full chip erase 2 ms N Max timeout for byte/word write 2 times typical N Max timeout for buffer write 2 times typical N Max timeout per individual sector erase 2 times typical N N (Continued) 22 MBM29DL34TF/BF70 (Continued) Description A6 to A0 DQ15 to DQ0 Minor version number, ASCII 44h 0033h Address Sensitive Unlock (DQ1, DQ0) 00h = Required Silicon Revision Number (DQ7 to DQ2) 45h 0000h Erase Suspend 02h = To Read & Write 46h 0002h Sector Protection 00h = Not Supported X = Number of sectors per group 47h 0001h Sector Temporary Unprotection 01h = Supported 48h 0001h Sector Protection Algorithm 49h 0004h Dual Operation 00h = Not Supported X = Total number of sectors in all banks except Bank 1 4Ah 0030h Burst Mode Type 00h = Not Supported 4Bh 0000h Page Mode Type 00h = Not Supported 4Ch 0000h VACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV 4Dh 0085h VACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV 4Eh 0095h Boot Type 02h = MBM29DL34BF 03h = MBM29DL34TF 4Fh 00XXh Program Suspend 01h = Supported 50h 0001h Bank Organization 00h = If data at 4Ah is zero. X = Number of Banks 57h 0004h Bank A Region Information X = Number of sectors in Bank A 58h 000Fh Bank B Region Information X = Number of sectors in Bank B 59h 0018h Bank C Region Information X = Number of sectors in Bank C 5Ah 0018h Bank D Region Information X = Number of sectors in Bank D 5Bh 0008h 23 MBM29DL34TF/BF70 ■ FUNCTIONAL DESCRIPTION 1. Simultaneous Operation The device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank address (A20, A19, A18) with zero latency. The device consists of the following two banks : Bank 1 : 8 × 8 KB and 63 × 64 KB; Bank 2 : 48 × 64 KB. The device can execute simultaneous operations between Bank 1 and Bank 2. The simultaneous operation cannot execute multi-function mode in the same bank. “Simultaneous Operation Table” shows the possible combinations for simultaneous operation. (Refer to “8 Bank-to-Bank Read / write Timing Diagram” in ■TIMING DIAGRAM. Simultaneous Operation Table Case Bank 1 status Bank 2 status 1 Read Mode Read Mode 2 Read Mode Autoselect Mode 3 Read Mode Program Mode 4 Read Mode Erase Mode * 5 Autoselect Mode Read Mode 6 Program Mode Read Mode 7 Erase Mode * Read Mode * : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) means to specify each of the Banks. 2. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high, the device requires tRH of wake up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of the OE input. 3. Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in applications such as handy terminal, which requests low power consumption. To activate this mode, the devices automatically switch themselves to low power mode when the devices addresses remain stable after 150 ns from data valid. It is not necessary to control CE, WE, and OE in this mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) . During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are continuously read out. If the addresses are changed, the mode is automatically canceled and the devices read out the data for changed addresses. 4. Autoselect The autoselect mode allows reading out of a binary code and identifies its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be 24 MBM29DL34TF/BF70 programmed with its corresponding programming algorithm. To activate this mode, the programming equipment must force VID on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses can be either High or Low except A0, A1, A2, A3, and A6 (A-1) . (See “MBM29DL34TF/BF User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” in ■ DEVICE BUS OPERATION.) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29DL34TF/BF Command Definitions Table” (■ DEVICE BUS OPERATION). (Refer to “2. Autoselect Command” in ■ COMMAND DIFINITIONS.) In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle at address 01h outputs device code (MBM29DL34TF=2250h, MBM29DL34BF=2253h). Notice that the above applies to Word mode; the addresses and codes differ from those of Byte mode (Refer to “MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables” and “MBM29DL34TF/BF Extended Autoselect Code Tables” in ■ DEVICE BUS OPERATION.) . 5. Read Mode The device has two control functions required to obtain data at the outputs. CE is the power control and used for a device selection. OE is the output control and used to gate data to the output pins . Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, input hardware reset or to change CE pin from “H” or “L” 6. Output Disable With the OE input at a logic high level (VIH) , output from the devices are disabled. This will cause the output pins to be in a high impedance state. 7. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. 8. Sector Group Protection The devices feature hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See “Sector Group Addresses Tables (MBM29DL34TF/BF)” in ■ SECTOR-ERASE ARCHITECTURE) . The user’s side can use the sector group protection using programming equipment. The device is shipped with all sector groups that are unprotected. To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29DL34TF/BF)” in ■ SECTOR-ERASE ARCHITECTURE define the sector address for each of the seventy one (71) individual sectors, and “Sector Group Addresses Tables (MBM29DL34TF/BF)” in ■ SECTOR-ERASE ARCHITECTURE define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See “15. Sector Group Protection Timing Diagram” in ■ TIMING DIAGRAM and “5. Sector Group Protection Algorithm” in ■ FLOW CHART for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 25 MBM29DL34TF/BF70 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logic “1” code at device output DQ0 for a protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A6, A1, and A0 can be either High or Low. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on Byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logic “1” at DQ0 for a protected sector group. See “MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables” and “MBM29DL34TF/BF Extended Autoselect Code Tables” in ■ DEVICE BUS OPERATION for Autoselect codes. 9. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to “16. Temporary Sector Group Unprotection Timing Diagram” in ■ TIMING DIAGRAM and “6. Temporary Sector Group Unprotection Algorithm” in ■ FLOW CHART. 10. Hardware RESET The devices may be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See “11. RESET, RY/BY Timing Diagram” in ■ TIMING DIAGRAM for the timing diagram. Refer to “9. Temporary Sector Group Unprotection” for additional functionality. 11. Byte/Word Configuration The BYTE pin selects the Byte (8-bit) mode or Word (16-bit) mode for the MBM29DL34TF/BF devices. When this pin is driven high, the devices operate in the Word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in Byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to “12. Timing Diagram for Word Mode Configuration”, “13. Timing Diagram for Byte Mode Configuration” and “14. BYTE Timing Diagram for Write Operations” in ■ TIMING DIAGRAM for the timing diagram. 12. Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 8 K byte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector Group Protection”. The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. (MBM29DL34TF : SA69 and SA70, MBM29DL34BF : SA0 and SA1) If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two 26 MBM29DL34TF/BF70 sectors depends on whether they were last protected or unprotected using the method described in “Sector Group Protection”. 13. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed programming, so caution is needed as the sector group become temporarily unprotected. The system would use a fact program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See “18. Accelerated Program Timing Diagram” in ■ TIMING DIAGRAM. Erase operation at Acceleration mode is strictly prohibited. 27 MBM29DL34TF/BF70 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands are required Bank Address (BA) input. When command sequences are inputted to bank being read, the commands have priority than reading. “MBM29DL34TF/BF Command Definitions Table” in ■ DEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover both Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands must be asserted to DQ7 to DQ0 and DQ8 to DQ15 bits are ignored. 1. Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset operation is initiated by writing the Reset command sequence into the command register. The device remains enabled for reads until the command register contents are altered. The device will automatically be in the reset state after power-up. In this case, a command sequence is not required to read data. 2. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therfore, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, applying high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. Following the command write, in Word mode, a read cycle from address (BA) 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle at address (BA) 01h outputs device code. Notice that the above applies to Word mode. The addresses and codes differ from those of Byte mode. (Refer to “MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables” and “MBM29DL34TF/BF Extended Autoselect Code Tables” in ■ DEVICE BUS OPERATION.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address (BA) 02h for ×16 ( (BA) 04h for ×8). Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logic “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See “MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables” and “MBM29DL34TF/BF Extended Autoselect Code Tables” in ■ DEVICE BUS OPERATION.) The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. To terminate the operation, it is necessary to write the Reset command sequence into the register. To execute the Autoselect command during the operation, Reset command must be written before the Autoselect command. 3. Byte/Word Programming The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data 28 MBM29DL34TF/BF70 write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. Hence, Data Polling requires the same address which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any address sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. But a read from Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. Note that attempting to program a “1” over “0” will result in programming failure. This precaution is the same with Fujitsu standard NOR devices. “1. Embedded ProgramTM Algorithm” in ■ FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. 4. Program Suspend/Resume The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming. The Program Suspend command can also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programmed should be set when writing the Program Suspend command. When the Program Suspend command is written during a programming process, the device halts the program operation within 1 µs and updates the status bits. After the program operation has been suspended, the system can read data from any address. The data at program-suspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sectors being suspended should be set when writing the Program Resume command. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system also writes Autoselect command sequence in the Program Suspend mode. The device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits from the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Program Resume command (address bits are “Bank Address”) to exit from the Program Suspend mode and continue programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming. 5. Chip Erase Chip erase is a six bus cycle operation. It begins two “unlock” write cycles followed by writing the “set-up” command, and two “unlock” write cycles followed by the chip erase command which is invokes the Embeded Erase algorithm. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm the devices will automatically program and verify the entire memory for an all zero data pattern prior 29 MBM29DL34TF/BF70 to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) ,DQ2 (Toggle Bit II ), or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever happens first from last command sequence and completes when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time = Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “2. Embedded EraseTM Algorithm” in ■ FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 6. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations. This sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than Erase Time-out time (tTOW). Otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be reoccur after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command (s) . If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see “16. DQ3 Sector Erase Timer”.) Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to “12. Write Operation Status” for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38) . Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase using the Embedded Erase algorithm. When erasing a sector or sectors, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and completes when the data on DQ7 is “1” (See “12. Write Operation Status”.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. “2. Embedded EraseTM Algorithm” in ■ FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 7. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform read or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation within the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writing the Erase Suspend or Erase Resume command. 30 MBM29DL34TF/BF70 When the Erase Suspend command is written during the Sector Erase operation, the devices take maximum of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See “17. DQ2”.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is the same as programming in the regular Program mode, except that the data must be programmed to sectors that are not erase-suspended. Reading successively from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 8. Extended Command (1) Fast Mode Set/Reset The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming consists of two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to “8. Embedded ProgramTM Algorithm for Fast Mode” in ■ FLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to “8. Embedded ProgramTM Algorithm for Fast Mode” in ■ FLOW CHART.) (3) Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses pins is recommended) , and write extended sector group protection command (60h) . A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h) . Following the command write, a logic “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logic “0”, write extended sector group protection command (60h) again. To terminate the operation, set RESET pin to VIH. (Refer to “17. Extended Sector Group Protection Timing Diagram” in ■ TIMING DIAGRAM and “7. Extended Sector Group Protection Algorithm” in ■ FLOW CHART.) 31 MBM29DL34TF/BF70 (4) Query Command (CFI : Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to Common Flash memory Interface code. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is “0” in Word mode (16 bit) read. Refer to the Common Flash memory Interface code table. To terminate operation, it is necessary to write the Reset command sequence into the register. (See “Common Flash Memory Interface Code Table” in ■ SECTOR-ERASE ARCHITECTURE.) 9. HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 256 bytes in length and is stored at the same address of the 8 KB sectors. The MBM29DL34TF occupies the address of the byte mode 3FE000h to 3FE0FFh (word mode 1FF000h to 1FF07Fh) and the MBM29DL34BF type occupies the address of the byte mode 000000h to 0000FFh (word mode 000000h to 00007Fh) . After the system writes the Enter HiddenROM command sequence, it may read the HiddenROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. 10. HiddenROM Entry Command The device has a HiddenROM area with one time protect function. This area is to enter the security code and to unable the change of the code once set. Programming is allowed in this area until it is protected. However, once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required. The HiddenROM area is 256 bytes. This area is normally the “outermost” 8 Kbyte boot block area in Bank 1. Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. Sectors other than the boot block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the HiddenROM area and the Bank 1. 11. HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the usual program command, except that it needs to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data pooling, DQ6 toggle bit and RY/BY pin. You should pay attention to the address to be programmed. If an address not in the HiddenROM area is selected, the previous data will be deleted. 12. HiddenROM Protect Command There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used 32 MBM29DL34TF/BF70 because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Please refer to “7. Extended Command (3) Extended Sector Group Protection” for details of extension sector group protect setting. The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the HiddenROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect previously mentioned. Refer to “8. Secor Group Protection” in ■ FUNCTIONAL DESCRIPTION for details of the sector group protect setting. Take note that other sector groups will be affected if an address other than those for the HiddenROM area is selected for the sector group address, so please be careful. Pay close attention that once it is protected, protection CANNOT BE CANCELLED. 13. Write Operation Status Detailed in “Hardware Sequence Flags Table” are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank that does not operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information on DQ2 is address sensitive. If an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing. The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>, [2] <non-busy bank>, [3] <busy bank>, the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in the [1] and [3]. In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is outputted. Hardware Sequence Flags Table DQ6 DQ5 DQ3 DQ2 Status DQ7 Embedded Program Algorithm Embedded Erase Algorithm In Progress Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle *1 Data Data Data Data Data Data Data Data Data Data 1 1 0 0 Toggle *1 Data Data Data Data Data DQ7 Toggle 0 0 1 *2 DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A *1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. 33 MBM29DL34TF/BF70 14. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a “1” at the DQ7 output. The flow chart for Data Polling (DQ7) is shown in “3. Data Polling Algorithm” in ■ FLOW CHART. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address of the sectors being erased, not protected sector. Otherwise, the status become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See “Hardware Sequence Flags Table”.) See “6. Data Polling during Embedded Algorithm Operation Timing Diagram” in ■ TIMING DIAGRAM for the Data Polling timing specifications and diagrams. 15. DQ6 Toggle Bit I The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the Toggle Bit will toggle for about 1 µs and then stop toggling with the data unchanged. In erase, the devices will erase all the selected sectors except for the protected ones. If all selected sectors are protected, the chip will toggle the Toggle Bit for about 400 µs and then drop back into read mode, having data kept remined. Either CE or OE toggling will cause the DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank is actively erasing (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause DQ6 to toggle. To operate Toggle bit function properly, CE or OE must be high when bank address is changed. See “7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in ■ TIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams. 34 MBM29DL34TF/BF70 16. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in “MBM29DL34TF/BF User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” (■ DEVICE BUS OPERATION). The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a “1.” Note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence. 17. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high (“1”) , the internally controlled erase cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags Table”. 18. DQ2 Toggle Bit II This Toggle Bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status Table” and “9. DQ2 vs. DQ6” in ■ TIMING DIAGRAM. Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate Toggle Bit function properly, CE or OE must be high when bank address is changed. 19. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading Toggle Bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a Toggle Bit is toggling. Typically a system would note and store the value of the Toggle Bit after the first read. After the second read, the system would compare the new value of the Toggle Bit with the first. If the Toggle Bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, after the initial two read cycles, if the system determines that the Toggle Bit is still toggling, the system also should note whether the value of DQ5 is high (see “15. DQ5”) . If it is, the system should then determine 35 MBM29DL34TF/BF70 again whether the Toggle Bit is toggling, since the Toggle Bit may have stopped toggling just as DQ5 went high. If the Toggle Bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to “4. Toggle Bit Algorithm” in ■ FLOW CHART.) Toggle Bit Status Table DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle *1 Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle *1 DQ7 Toggle 1 *2 Mode Program Erase-Suspend Program *1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. 20. RY/BY Ready/Busy The devices provide a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. If the devices are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to “10. RY/BY Timing Diagram during Program/Erase Operations” and “11. RESET, RY/BY Timing Diagram” in ■ TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiple of devices may be connected to the host system via more than one RY/BY pin in parallel. 21. Data Protection The devices are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. 22. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is(are) not valid. 23. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. 36 MBM29DL34TF/BF70 24. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logic zero while OE is a logic one. 25. Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 26. Sector Protection Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both program and erase commands that are addressed to protected sectors. Any commands to program or erase addressed to protected sector are ignored. (See “8. Sector Group Protection” in ■ FUNCTIONAL DESCRIPTION.) 37 MBM29DL34TF/BF70 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Tstg −55 +125 °C TA −40 +85 °C VIN, VOUT −0.5 VCC + 0.5 V Power Supply Voltage *1 VCC −0.5 +4.0 V A9, OE, and RESET *1,*3 VIN −0.5 +13.0 V 1, 4 VACC −0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET *1,*2 WP/ACC * * *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when VCC is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Part No. Value Min Max Unit Ambient Temperatuer TA MBM29DL34TF/BF 70 −40 +85 °C Power Supply Voltage VCC MBM29DL34TF/BF 70 +2.7 +3.6 V Notes: • Voltage is defined on the basis of VSS = GND = 0 V. • Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 38 MBM29DL34TF/BF70 ■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V 20 ns 20 ns −0.5 V −2.0 V 20 ns Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 39 MBM29DL34TF/BF70 ■ DC CHARACTERISTICS Sym bol Conditions Input Leakage Current ILI Output Leakage Current A9, OE, RESET Inputs Leakage Current Parameter VCC Active Current * 1 Value Min Typ Max Uni t VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA ILO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA ILIT VCC = VCC Max, A9, OE, RESET = 12.5 V 35 µA 16 18 4 4 ICC1 CE = VIL, OE = VIH, f = 5 MHz CE = VIL, OE = VIH, f = 1 MHz Byte Word Byte Word mA VCC Active Current *2 ICC2 CE = VIL, OE = VIH 30 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V, WE/ACC = VCC ± 0.3 V 1 5 µA VCC Current (Standby, Reset) ICC4 VCC = VCC Max, RESET = VSS ± 0.3 V 1 5 µA VCC Current (Automatic Sleep Mode) *3 ICC5 VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V 1 5 µA VCC Active Current *5 (Read-While-Program) ICC6 CE = VIL, OE = VIH Byte 46 Word 48 VCC Active Current *5 (Read-While-Erase) ICC7 CE = VIL, OE = VIH Byte 46 Word 48 VCC Active Current (Erase-Suspend-Program) ICC8 CE = VIL, OE = VIH 35 mA ACC Accelerated Program Current IACC VCC = VCC Max, WP/ACC = VACC Max 20 mA Input Low Level VIL −0.5 +0.6 V Input High Level VIH 2.0 VCC + 0.3 V VACC 8.5 9.5 V Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 VID 11.5 12 12.5 V Output Low Voltage Level VOL 0.45 V 2.4 V VCC − 0.4 V 2.3 2.4 2.5 V Voltage for WP/ACC Sector Protection/ Unprotection and Program Acceleration Output High Voltage Level Low VCC Lock-Out Voltage IOL = 4.0 mA, VCC = VCC Min VOH1 IOH = −2.0 mA, VCC = VCC Min VOH2 IOH = −100 µA VLKO *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCC applying. *5: Embedded Algorithm (program or erase) is in progress (@5 MHz) . 40 mA mA mA MBM29DL34TF/BF70 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Value * Symbol Parameter Test setup 70 Unit Min Max 70 ns tACC CE = VIL OE = VIL 70 ns tELQV tCE OE = VIL 70 ns Output Enable to Output Delay tGLQV tOE 30 ns Chip Enable to Output High-Z tEHQZ tDF 25 ns Output Enable to Output High-Z tGHQZ tDF 25 ns Output Hold Time from Addresses, CE or OE, Whichever Occurs First tAXQX tOH 0 ns RESET Pin Low to Read Mode tREADY 20 µs CE to BYTE Switching Low or High tELFL, tELFH 5 ns JEDEC Standard Read Cycle Time tAVAV tRC Address to Output Delay tAVQV Chip Enable to Output Delay * : Test Conditions : Output Load : 1TTL gate and 100 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCC Timing measurement reference level Input : VCC / 2 Output : VCC / 2 3.3 V Diode = 1N3064 or Equivalent Device Under Test 2.7 kΩ 6.2 kΩ Diode = 1N3064 or Equivalent CL Note : CL = 100 pF including jig capacitance Test Conditions 41 MBM29DL34TF/BF70 • Write/Erase/Program Operations Symbol Parameter 70 Unit JEDEC Standard Min Typ Max Write Cycle Time tAVAV tWC 70 ns Address Setup Time tAVWL tAS 0 ns tASO 12 ns tWLAX tAH 45 ns tAHT 0 ns Data Setup Time tDVWH tDS 30 ns Data Hold Time tWHDX tDH 0 ns tOEH 0 ns 10 ns CE High During Toggle Bit Polling tCEPH 20 ns OE High During Toggle Bit Polling tOEPH 20 ns Read Recover Time Before Write tGHWL tGHWL 0 ns Read Recover Time Before Write tGHEL tGHEL 0 ns CE Setup Time tELWL tCS 0 ns WE Setup Time tWLEL tWS 0 ns CE Hold Time tWHEH tCH 0 ns WE Hold Time tEHWH tWH 0 ns Write Pulse Width tWLWH tWP 35 ns CE Pulse Width tELEH tCP 35 ns Write Pulse Width High tWHWL tWPH 25 ns CE Pulse Width High tEHEL tCPH 25 ns tWHWH1 tWHWH1 4 µs 6 µs tWHWH2 tWHWH2 0.5 s tVCS 50 µs Rise Time to VID * tVIDR 500 ns Rise Time to VACC *3 tVACCR 500 ns Voltage Transition Time *2 tVLHT 4 µs tWPP 100 µs tOESP 4 µs Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Output Enable Hold Time Read Toggle and Data Polling Byte Programming Operation Word Sector Erase Operation *1 VCC Setup Time 2 Write Pulse Width * 2 OE Setup Time to WE Active * 2 (Continued) 42 MBM29DL34TF/BF70 (Continued) Symbol Parameter 70 Unit JEDEC Standard Min Typ Max CE Setup Time to WE Active *2 tCSP 4 µs Recover Time from RY/BY tRB 0 ns RESET Pulse Width tRP 500 ns RESET High Level Period before Read tRH 200 ns BYTE Switching Low to Output High-Z tFLQZ 30 ns BYTE Switching High to Output Active tFHQV 70 ns Program/Erase Valid to RY/BY Delay tBUSY 90 ns Delay Time from Embedded Output Enable tEOE 70 ns Erase Time-Out Time tTOW 50 µs Erase Suspend Transition Time tSPD 20 µs *1 : Does not include the preprogramming time. *2 : For Sector Group Protection operation. *3 : This timing is limited for Accelerated Program operation only. 43 MBM29DL34TF/BF70 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Min Typ Max Sector Erase Time 0.5 2.0 s Word Programming Time 6.0 100 µs Byte Programming Time 4.0 80 µs Chip Programming Time 100 s 100,000 cycle Program/Erase Cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Notes : • Typical Erase conditions TA = +25 °C, Vcc = 2.9 V • Typical Program conditions TA = +25 °C, Vcc = 2.9 V, Data = checker ■ TSOP (1) PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Condition Value Unit Typ Max VIN = 0 6.0 10.0 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 11.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 9.0 12.0 pF Notes : • Test conditions TA = +25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. ■ FBGA PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Condition Unit Typ Max VIN = 0 6.0 10.0 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 11.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 9.0 12.0 pF Notes : • Test conditions TA = +25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. 44 Value MBM29DL34TF/BF70 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Change from H to L May Change from L to H Will Change from L to H "H" or "L" Any Change Permitted Changing State Unknown Does Not Apply Center Line is HighImpedance "Off" State 1. Read Operation Timing Diagram tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE High-Z Outputs tOH Output Valid High-Z 45 MBM29DL34TF/BF70 2. Hardware Reset/Read Operation Timing Diagram tRC Address Address Stable tACC CE tRH tRP tRH tCE RESET tOH High-Z Outputs Output Valid 3. Alternate WE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE tDS tDH Data A0h tOH tDF PD DQ7 DOUT DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at byte address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates the last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode (the addresses differ from ×8 mode) . 46 MBM29DL34TF/BF70 4. Alternate CE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data A0h tDH PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at byte address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates the last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode (the addresses differ from ×8 mode) . 47 MBM29DL34TF/BF70 5. Chip/Sector Erase Operation Timing Diagram 555h Address tWC 2AAh tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh Data 10h for Chip Erase 55h 80h AAh 55h 10h/ 30h tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) , AAAh (Byte) for Chip Erase. Note : These waveforms are for the ×16 mode (the addresses differ from ×8 mode) . 48 MBM29DL34TF/BF70 6. Data Polling during Embedded Algorithm Operation Timing Diagram CE tCH tDF tOE OE tOEH WE tCE * Data DQ7 DQ7 = Valid Data DQ7 High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 = Output Flag Data DQ6 to DQ0 Valid Data High-Z tEOE tBUSY RY/BY * : DQ7 = Valid Data (the device has completed the Embedded operation.) 7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram Address tAHT tASO tAHT tAS CE tCEPH WE tOEH tOEPH tOEH OE tDH DQ6/DQ2 tOE tCE Toggle Data Data Toggle Data Toggle Data * Stop Toggling Output Valid tBUSY RY/BY * : DQ6 stops toggling (the device has completed the Embedded operation) . 49 MBM29DL34TF/BF70 8. Bank-to-Bank Read/Write Timing Diagram Address Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tACC tAH tAS tAHT tCE CE tCEPH tOE OE tGHWL tOEH tWP tDF WE tDH tDS Valid Output DQ Valid Input tDF Valid Output (A0h) Valid Input Valid Output Status (PD) Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 9. DQ2 vs. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note : DQ2 is read from the erase-suspended sector. 50 Erase Erase Complete MBM29DL34TF/BF70 10. RY/BY Timing Diagram during Program/Erase Operations CE Rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY 11. RESET, RY/BY Timing Diagram WE RESET tRB tRP RY/BY tREADY 12. Timing Diagram for Word Mode Configuration CE tCE BYTE Data Output (DQ7 to DQ0) DQ14 to DQ0 tELFH DQ15/A-1 Data Output (DQ14 to DQ0) tFHQV A-1 DQ15 51 MBM29DL34TF/BF70 13. Timing Diagram for Byte Mode Configuration CE BYTE DQ14 to DQ0 tELFL Data Output (DQ14 to DQ0) Data Output (DQ14 to DQ0) tACC DQ15/A-1 A-1 DQ15 tFLQZ 14. BYTE Timing Diagram for Write Operations Falling edge of the last write signal CE or WE Input Valid BYTE tAH tAS 52 MBM29DL34TF/BF70 15. Sector Group Protection Timing Diagram A20, A19, A18 A17, A16, A15 A14, A13, A12 SGAX SGAY A6, A3, A2, A0 A1 VID VIH A9 tVLHT VID VIH OE tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE 01h Data tVCS tOE VCC SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected Note : A-1 is VIL on byte mode. 53 MBM29DL34TF/BF70 16. Temporary Sector Group Unprotection Timing Diagram VCC tVIDR tVLHT tVCS VID VIH RESET CE WE tVLHT Program or Erase Command Sequence RY/BY Unprotection Period 54 tVLHT MBM29DL34TF/BF70 17. Extended Sector Group Protection Timing Diagram VCC tVCS RESET tVLHT tVIDR tWC Address tWC SGAX SGAX SGAY A6, A3, A2, A0 A1 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h 60h tOE SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 55 MBM29DL34TF/BF70 18. Accelerated Program Timing Diagram VCC tVACCR tVLHT tVCS VACC VIH WP/ACC CE WE tVLHT tVLHT Program Command Sequence RY/BY Acceleration Period 56 MBM29DL34TF/BF70 ■ FLOW CHART 1. Embedded ProgramTM Algorithm EMBEDDED ALGORITHMS Start Write Program Command Sequence (See Below) Data Polling Device No Increment Address Verify Data ? Yes No Embedded Program Algorithm in progress Last Address ? Yes Programming Completed Program Command Sequence (Address/Command) : 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. 57 MBM29DL34TF/BF70 2. Embedded EraseTM Algorithm EMBEDDED ALGORITHMS Start Write Erase Command Sequence (See Below) Data Polling No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence (Address/Command) : Individual Sector/Multiple Sector Erase Command Sequence (Address/Command) : 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. 58 Additional sector erase commands are optional. MBM29DL34TF/BF70 3. Data Polling Algorithm VA = Valid Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 59 MBM29DL34TF/BF70 4. Toggle Bit Algorithm Start Read DQ7 to DQ0 Addr. = VA Read DQ7 to DQ0 Addr. = VA Toggle Bit = Toggle? VA = Bank address being executed Embedded Algorithm. *1 *1 No Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = VA *1, *2 Read DQ7 to DQ0 Addr. = VA Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether or not it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. 60 MBM29DL34TF/BF70 5. Sector Group Protection Algorithm Start ( Setup Sector Group Addr. A20, A19, A18, A17,A16, A15, A14, A13, A12 ) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A3 = A2 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group = SGA, A1 = VIH * ( AAddr. 6 = A3 = A2 = A0 = VIL ) No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group ? Yes No Device Failed Remove VID from A9 Write Reset Command Sector Group Protection Completed * : A-1 is VIL in byte mode. 61 MBM29DL34TF/BF70 6. Temporary Sector Group Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are reprotected. 62 MBM29DL34TF/BF70 7. Extended Sector Group Protection Algorithm Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Secter Group Write 60h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Time out 250 µs To Verify Sector Group Protection Write 40h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Increment PLSCNT Read from Sector Group Address (Addr. = SGA, A6 = A3 = A2 = A0 = VIL, A1 = VIH) No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command No Setup Next Sector Address Data = 01h? Yes Yes Protect Other Sector Group? No Remove VID from RESET Write Reset Command Device Failed Sector Protection Completed 63 MBM29DL34TF/BF70 8. Embedded ProgramTM Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling In Fast Program Verify Data? No Yes Increment Address No Last Address ? Yes Programming Completed (BA) XXXh/90h Reset Fast Mode XXXh/F0h Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. 64 MBM29DL34TF/BF70 ■ ORDERING INFORMATION Part No. Package Access Time (ns) 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 70 MBM29DL34TF70PBT 48-pin plastic FBGA (BGA-48P-M12) 70 MBM29DL34BF70TN 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 70 48-pin plastic FBGA (BGA-48P-M12) 70 MBM29DL34TF70TN MBM29DL34BF70PBT MBM29DL34 T F 70 Remarks Top Sector Bottom Sector TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend PBT = Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29DL34 32 Mega-bit (4 M × 8-Bit or 2 M × 16-Bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 65 MBM29DL34TF/BF70 ■ PACKAGE DIMENSIONS Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP (1) (FPT-48P-M19) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" 0.10(.004) (.472±.008) +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height) +0.03 0.17 –0.08 +.001 .007 –.003 C 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) 0.22±0.05 (.009±.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 66 MBM29DL34TF/BF70 (Continued) 48-pin plastic FBGA (BGA-48P-M12) +0.15 9.00±0.20(.354±.008) +.006 1.05 –0.10 .041 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 5.60(.220) 0.80(.031)TYP 6 5 INDEX 6.00±0.20 (.236±.008) 4 4.00(.157) 3 2 1 H C0.25(.010) G F E D 48-ø0.45±0.10 (48-ø.018±.004) C B A ø0.08(.003) M 0.10(.004) C 2001 FUJITSU LIMITED B48012S-c-3-3 Dimensions in mm (inches) Note : The values in parentheses are reference values. 67 MBM29DL34TF/BF70 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0311 FUJITSU LIMITED Printed in Japan