SPANSION MBM29SL800TD

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20871-5E
FLASH MEMORY
CMOS
8 M (1 M × 8/512 K × 16) BIT
MBM29SL800TD/BD-10/12
■ DESCRIPTION
The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , 48-ball FBGA and 48-ball
SCSP packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC
supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29SL800TD/MBM29SL800BD
−10
−12
Max Address Access Time (ns)
100
120
Max CE Access Time (ns)
100
120
Max OE Access Time (ns)
35
50
Ordering Part No.
VCC = +2.0 V ± 0.2
■ PACKAGES
48-pin Plastic TSOP (I)
48-pin Plastic TSOP (I)
48-pin Plastic FBGA
48-pin Plastic SCSP
(BGA-48P-M12)
(WLP-48P-M03)
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(Continued)
The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) ,
write enable (WE) , and output enable (OE) controls.
The MBM29SL800TD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29SL800TD/BD are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29SL800TD/BD are erased when shipped from the
factory.
The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29SL800TD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ FEATURES
• Single 1.8 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
48-ball SCSP (Package suffix : PW)
• Minimum 100,000 program/erase cycles
• High performance
100 ns maximum access time
• Sector erase architecture
One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector Protect command
• Fast programming Function by Extended Command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ PIN ASSIGNMENTS
TSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
Normal Bend
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
(FPT-48P-M19)
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Bend
(FPT-48P-M20)
(Continued)
4
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(Continued)
FBGA
(TOP VIEW)
Marking side
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
WE RESET N.C.
F6
G6
H6
BYTE DQ15/A-1 VSS
D4
E4
F4
G4
H4
N.C.
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY
N.C.
A18
N.C.
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE
OE
VSS
(BGA-48P-M12)
SCSP
(TOP VIEW)
Marking side
A6
B6
C6
D6
E6
F6
G6
H6
A3
A4
A2
A1
A0
CE
OE
VSS
A5
B5
C5
D5
E5
F5
G5
H5
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY
N.C.
A18
N.C.
DQ2
DQ10
DQ11
DQ3
A3
B3
C3
D3
E3
F3
G3
H3
WE
RESET
N.C.
N.C.
DQ5
DQ12
VCC
DQ4
A2
B2
C2
D2
E2
F2
G2
H2
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A1
B1
C1
D1
E1
F1
G1
H1
A13
A12
A14
A15
A16
BYTE DQ15/A-1 VSS
(WLP-48P-M03)
5
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ PIN DESCRIPTION
Pin name
6
Function
A18 to A0, A-1
Address Inputs
DQ15 to DQ0
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Hardware Reset Pin/Temporary Sector Unprotection
RY/BY
Ready/Busy Output
BYTE
Selects 8-bit or 16-bit mode
VSS
Device Ground
VCC
Device Power Supply
N.C.
No Internal Connection
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ BLOCK DIAGRAM
DQ15 to DQ0
VCC
RY/BY
Buffer
VSS
RY/BY
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
BYTE
RESET
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
STB
Data Latch
OE
Low VCC Detector
Timer for
Program/Erase
A18 to A0
Address Latch
STB
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A-1
■ LOGIC SYMBOL
A-1
19
A18 to A0
16 or 8
DQ15 to DQ0
CE
OE
WE
RY/BY
RESET
BYTE
7
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ DEVICE BUS OPERATION
MBM29SL800TD/800BD User Bus Operations Table (BYTE = VIH)
CE
OE
WE
A0
A1
A6
A9
DQ0 to DQ15
RESET
Auto-Select Manufacturer Code *1
L
L
H
L
L
L
VID
Code
H
Auto-Select Device Code *1
L
L
H
H
L
L
VID
Code
H
Read *3
L
L
H
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
DIN
H
L
VID
L
H
L
VID
X
H
Verify Sector Protection * *
L
L
H
L
H
L
VID
Code
H
Temporary Sector Unprotection
X
X
X
X
X
X
X
X
VID
Reset (Hardware) /Standby
X
X
X
X
X
X
X
High-Z
L
Operation
Enable Sector Protection *2, *4
2, 4
MBM29SL800TD/800BD User Bus Operations Table (BYTE = VIL)
CE
OE
WE
DQ15/
A-1
A0
A1
A6
A9
DQ0 to
DQ7
RESET
L
L
H
L
L
L
L
VID
Code
H
L
L
H
L
H
L
L
VID
Code
H
L
L
H
A-1
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
High-Z
H
L
H
L
A-1
A0
A1
A6
A9
DIN
H
Enable Sector Protection * *
L
VID
L
L
H
L
VID
X
H
Verify Sector Protection *2, *4
L
L
H
L
L
H
L
VID
Code
H
Temporary Sector Unprotection *5
X
X
X
X
X
X
X
X
X
VID
Reset (Hardware) /Standby
X
X
X
X
X
X
X
X
High-Z
L
Operation
Auto-Select Manufacturer Code *1
1
Auto-Select Device Code *
Read *
3
Write (Program/Erase)
2, 4
Legend : L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See
“MBM29SL800TD/800BD Standard Command Definitions Table”.
*2: Refer to the section on Sector Protection.
*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4: VCC = 2.0 V ± 10%
*5: It is also used for the extended sector protection.
8
MBM29SL800TD-10/12/MBM29SL800BD-10/12
MBM29SL800TD/800BD Standard Command Definitions Table
Command
Sequence
Read/
Reset
Word
Read/
Reset
Word
Autoselect
Program
Byte
Byte
Word
Byte
Word
Byte
Chip
Erase
Word
Sector
Erase
Word
Byte
Byte
Bus
Write
Cycles
Req’d
1
3
3
4
6
6
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fourth Bus
Fifth Bus
Sixth Bus
Read/Write
Write Cycle Write Cycle
Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
XXXh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
F0h
AAh
AAh
AAh
AAh
AAh

2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h

55h
55h
55h
55h
55h

555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh







F0h
RA
RD




90h






A0h
PA
PD




80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
55h
555h
AAAh
SA
Sector Erase Suspend
Erase can be suspended during sector erase with Addr. (“H” or “L”) . Data (B0h)
Sector Erase Resume
Erase can be resumed after suspend with Addr. (“H” or “L”) . Data (30h)
10h
30h
Notes : • Address bits A11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA)
• Bus operations are defined in “MBM29SL800TD/800BD User Bus Operations Tables (BYTE = VIH and
BYTE = VIL)”.
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
• The system should generate the following address patterns :
Word Mode : 555h or 2AAh to addresses A0 to A10
Byte Mode : AAAh or 555h to addresses A-1 and A0 to A10
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command combinations not described in “MBM29SL800TD/800BD Standard Command Definitions
Table” and “MBM29SL800TD/BD Extended Command Definitions Table” are illegal.
9
MBM29SL800TD-10/12/MBM29SL800BD-10/12
MBM29SL800TD/BD Extended Command Definitions Table
Bus
Write
Cycles
Req'd
Command
Sequence
Word
Set to
Fast Mode
Byte
Word
Fast Program*1
Byte
Reset from Fast
Mode*1
Word
Extended Sector
Protect*2
Word
Byte
Byte
First Bus
Write Cycle
Addr
Data
555h
3
XXXh
XXXh
XXXh
4
XXXh
55h
555h
PA
XXXh
90h
XXXh
60h
Third Bus
Write Cycle
Data
2AAh
A0h
XXXh
2
Addr
AAh
AAAh
2
Second Bus
Write Cycle
SPA
Addr
Fourth Bus
Read Cycle
Data
Addr
Data
20h


555h
AAAh
PD




F0h*3




60h
SPA
40h
SPA
SD
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0) .
SD : Sector protection verify data. Output 01h at protected sector address and output 00h at unprotected sector
address.
*1 : This command is valid during Fast Mode.
*2 : This command is valid while RESET = VID.
*3 : The data “00h” is also acceptable.
MBM29SL800TD/800BD Sector Protection Verify Autoselect Codes Table
Type
A12 to A18
A6
A1
A0
A-1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04h
X
VIL
VIL
VIH
VIL
EAh
X
22EAh
X
VIL
VIL
VIH
VIL
6Bh
X
226Bh
Sector
Address
VIL
VIH
VIL
VIL
01h*2
Manufacture’s Code
Byte
MBM29SL800TD
Word
Device Code
MBM29SL800BD
Byte
Word
Sector Protection
*1 : A−1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address.
*2 : Outputs 01h at protected sector address and outputs 00h at unprotected sector address.
Extended Autoselect Code Table
Type
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacturer’s Code
04h A-1/0
MBM29SL (B) *
(W)
Device 800TD
Code MBM29SL (B) *
800BD
(W)
EAh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
Sector Protection
22EAh
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
6Bh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
226Bh
0
01h A-1/0
0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
* : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address.
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
10
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable.
(×8)
FFFFFh
(×16)
(×8)
7FFFFh
16 Kbyte
(×16)
FFFFFh
7FFFFh
EFFFFh
77FFFh
DFFFFh
6FFFFh
CFFFFh
67FFFh
BFFFFh
5FFFFh
AFFFFh
57FFFh
9FFFFh
4FFFFh
8FFFFh
47FFFh
7FFFFh
3FFFFh
6FFFFh
37FFFh
5FFFFh
2FFFFh
4FFFFh
27FFFh
3FFFFh
1FFFFh
2FFFFh
17FFFh
1FFFFh
0FFFFh
0FFFFh
07FFFh
07FFFh
03FFFh
05FFFh
02FFFh
03FFFh
01FFFh
00000h
00000h
64 Kbyte
FBFFFh
7DFFFh
8 Kbyte
64 Kbyte
F9FFFh
7CFFFh
8 Kbyte
64 Kbyte
F7FFFh
7BFFFh
32 Kbyte
64 Kbyte
EFFFFh
77FFFh
64 Kbyte
64 Kbyte
DFFFFh
6FFFFh
64 Kbyte
64 Kbyte
CFFFFh
67FFFh
64 Kbyte
64 Kbyte
BFFFFh
5FFFFh
64 Kbyte
64 Kbyte
AFFFFh
57FFFh
64 Kbyte
64 Kbyte
9FFFFh
4FFFFh
64 Kbyte
64 Kbyte
8FFFFh
47FFFh
64 Kbyte
64 Kbyte
7FFFFh
3FFFFh
64 Kbyte
64 Kbyte
6FFFFh
37FFFh
64 Kbyte
64 Kbyte
5FFFFh
2FFFFh
64 Kbyte
64 Kbyte
4FFFFh
27FFFh
64 Kbyte
64 Kbyte
3FFFFh
1FFFFh
64 Kbyte
32 Kbyte
2FFFFh
17FFFh
64 Kbyte
8 Kbyte
1FFFFh
0FFFFh
64 Kbyte
8 Kbyte
0FFFFh
07FFFh
64 Kbyte
16 Kbyte
00000h
00000h
MBM29SL800TD Sector Architecture
MBM29SL800BD Sector Architecture
11
MBM29SL800TD-10/12/MBM29SL800BD-10/12
Sector Address Table (MBM29SL800TD)
Sector
Address
12
A18
A17
A16
A15
A14
A13
A12
×8)
Address Range (×
×16)
Address Range (×
SA0
0
0
0
0
X
X
X
00000h to 0FFFFh
00000h to 07FFFh
SA1
0
0
0
1
X
X
X
10000h to 1FFFFh
08000h to 0FFFFh
SA2
0
0
1
0
X
X
X
20000h to 2FFFFh
10000h to 17FFFh
SA3
0
0
1
1
X
X
X
30000h to 3FFFFh
18000h to 1FFFFh
SA4
0
1
0
0
X
X
X
40000h to 4FFFFh
20000h to 27FFFh
SA5
0
1
0
1
X
X
X
50000h to 5FFFFh
28000h to 2FFFFh
SA6
0
1
1
0
X
X
X
60000h to 6FFFFh
30000h to 37FFFh
SA7
0
1
1
1
X
X
X
70000h to 7FFFFh
38000h to 3FFFFh
SA8
1
0
0
0
X
X
X
80000h to 8FFFFh
40000h to 47FFFh
SA9
1
0
0
1
X
X
X
90000h to 9FFFFh
48000h to 4FFFFh
SA10
1
0
1
0
X
X
X
A0000h to AFFFFh
50000h to 57FFFh
SA11
1
0
1
1
X
X
X
B0000h to BFFFFh
58000h to 5FFFFh
SA12
1
1
0
0
X
X
X
C0000h to CFFFFh
60000h to 67FFFh
SA13
1
1
0
1
X
X
X
D0000h to DFFFFh
68000h to 6FFFFh
SA14
1
1
1
0
X
X
X
E0000h to EFFFFh
70000h to 77FFFh
SA15
1
1
1
1
0
X
X
F0000h to F7FFFh
78000h to 7BFFFh
SA16
1
1
1
1
1
0
0
F8000h to F9FFFh
7C000h to 7CFFFh
SA17
1
1
1
1
1
0
1
FA000h to FBFFFh
7D000h to 7DFFFh
SA18
1
1
1
1
1
1
X
FC000h to FFFFFh
7E000h to 7FFFFh
MBM29SL800TD-10/12/MBM29SL800BD-10/12
Sector Address Table (MBM29SL800BD)
Sector
Address
A18
A17
A16
A15
A14
A13
A12
×8)
Address Range (×
×16)
Address Range (×
SA0
0
0
0
0
0
0
X
00000h to 03FFFh
00000h to 01FFFh
SA1
0
0
0
0
0
1
0
04000h to 05FFFh
02000h to 02FFFh
SA2
0
0
0
0
0
1
1
06000h to 07FFFh
03000h to 03FFFh
SA3
0
0
0
0
1
X
X
08000h to 0FFFFh
04000h to 07FFFh
SA4
0
0
0
1
X
X
X
10000h to 1FFFFh
08000h to 0FFFFh
SA5
0
0
1
0
X
X
X
20000h to 2FFFFh
10000h to 17FFFh
SA6
0
0
1
1
X
X
X
30000h to 3FFFFh
18000h to 1FFFFh
SA7
0
1
0
0
X
X
X
40000h to 4FFFFh
20000h to 27FFFh
SA8
0
1
0
1
X
X
X
50000h to 5FFFFh
28000h to 2FFFFh
SA9
0
1
1
0
X
X
X
60000h to 6FFFFh
30000h to 37FFFh
SA10
0
1
1
1
X
X
X
70000h to 7FFFFh
38000h to 3FFFFh
SA11
1
0
0
0
X
X
X
80000h to 8FFFFh
40000h to 47FFFh
SA12
1
0
0
1
X
X
X
90000h to 9FFFFh
48000h to 4FFFFh
SA13
1
0
1
0
X
X
X
A0000h to AFFFFh
50000h to 57FFFh
SA14
1
0
1
1
X
X
X
B0000h to BFFFFh
58000h to 5FFFFh
SA15
1
1
0
0
X
X
X
C0000h to CFFFFh
60000h to 67FFFh
SA16
1
1
0
1
X
X
X
D0000h to DFFFFh
68000h to 6FFFFh
SA17
1
1
1
0
X
X
X
E0000h to EFFFFh
70000h to 77FFFh
SA18
1
1
1
1
X
X
X
F0000h to FFFFFh
78000h to 7FFFFh
13
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29SL800TD/BD have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE pin from “H” to “L”
Standby Mode
There are two ways to implement the standby mode on the MBM29SL800TD/BD devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time
(tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is
required even CE = “H”.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE = “H” or “L”) . Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29SL800TD/800BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29SL800TD/800BD automatically switch themselves to low power mode when
MBM29SL800TD/800BD addresses remain stably during access fine of 150 ns. It is not necessary to control
CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) .
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29SL800TD/800BD read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH) , output from the devices are disabled. This will cause the output
pins to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (10 V to 11 V) on address pin A9. Two identifier
bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are
DON’T CARES except A0, A1, A6, and A-1. (See “MBM29SL800TD/800BD Sector Protection Verify Autoselect
Codes Table” in ■DEVICE BUS OPERATION.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29SL800TD/BD are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29SL800TD/800BD Standard Command Definitions Table” (in ■DEVICE BUS OPERATION). (Refer to Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier
code (MBM29SL800TD = EAh and MBM29SL800BD = 6Bh for ×8 mode; MBM29SL800TD = 22EAh and
MBM29SL800BD = 226Bh for ×16 mode) . These two bytes/words are given in “MBM29SL800TD/800BD Sector
Protection Verify Autoselect Codes Table and Extended Autoselect Code Table (in ■DEVICE BUS OPERATION”).
14
MBM29SL800TD-10/12/MBM29SL800BD-10/12
All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to
read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29SL800TD/800BD
Sector Protection Verify Autoselect Codes Table and Extended Autoselect Code Table in ■DEVICE BUS OPERATION”.)
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29SL800TD/BD feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 18) . The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE,
CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to
be protected. “Sector Address Tables (MBM29SL800TD/BD)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the nineteen (19) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector addresses must be held constant during the WE pulse. See “(13) Sector
Protection Timing Diagram” in ■TIMING DIAGRAM and “(5) Sector Protection Algorithm” in ■FLOW CHART
for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while
(A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
A-1 requires to apply to VIL on byte mode.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29SL800TD/BD devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(VID) . During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the VID is taken away from the RESET pin, all the previously protected sectors will be protected
again. See “(14) Temporary Sector Unprotection Timing Diagram” in ■TIMING DIAGRAM and “(6) Temporary
Sector Unprotection Algorithm” in ■FLOW CHART.
RESET
Hardware Reset
The MBM29SL800TD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “(9) RESET, RY/BY Timing
Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
15
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
“MBM29SL800TD/800BD Standard Command Definitions Table” in ■DEVICE BUS OPERATION defines the
valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands
are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are
functionally equivalent, resetting the device to the read mode. Please note that commands are always written
at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage
onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29SL800TD = EAh and
MBM29SL800BD = 6Bh for ×8 mode; MBM29SL800TD = 22EAh and MBM29SL800BD = 226Bh for ×16
mode) . (See “MBM29SL800TD/800BD Sector Protection Verify Autoselect Codes Table and Extended
Autoselect Code Table in ■DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd
parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address
XX02h for ×16 (XX04h for ×8) .
Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a
logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode on the protected sector. (See “MBM29SL800TD/800BD User Bus Operations Table (BYTE = VIH and BYTE
= VIL)” in ■DEVICE BUS OPERATION.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the
16
MBM29SL800TD-10/12/MBM29SL800BD-10/12
system at this particular instance of time. Hence, Data Polling must be performed at the memory location which
is being programmed.
If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being
written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“(1) Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29SL800TD/800BD
Standard Command Definitions Table” in ■DEVICE BUS OPERATION. This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last
WE will initiate the execution of the Sector Erase command (s) . If another falling edge of the WE occurs within
the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still
open, see section DQ3, Sector Erase Timer.) Resetting the devices once execution has begun will corrupt the
data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the
Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done
in any sequence and with any number of sectors (0 to 18) .
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.)
at which time the devices return to the read mode. Data polling must be performed at an address within any of
17
MBM29SL800TD-10/12/MBM29SL800BD-10/12
the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase
“(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. Writting the Erase Suspend command during the
Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the
RY/BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address
of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29SL800TD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles required
in the standard program command sequence by writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register.
(Refer to “(8) Embedded Programming Algorithm for Fast Mode” in ■FLOW CHART Extended algorithm.) The
VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to the
“(8) Embedded Programming Algorithm for Fast Mode” in ■FLOW CHART Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29SL800TD/BD has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
18
MBM29SL800TD-10/12/MBM29SL800BD-10/12
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET
pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With
this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then,
the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the
sector to be protected (recommend to set VIL for the other addresses pins) , and write extended sector protect
command (60h) . A sector is typically protected in 250 µs. To verify programming of the protection circuitry, the
sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a
command (40h) . Following the command write, a logical “1” at device output DQ0 will produce for protected
sector in the read operation. If the output data is logical “0”, please repeat to write extended sector protect
command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH.
Write Operation Status
Hardware Sequence Flags Table
Status
Embedded Program Algorithm
Embedded Erase Algorithm
In Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspended
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Embedded Program Algorithm
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle*1
1
1
0
0
Toggle
Data
Data
Data
Data
Data
DQ7
Toggle
0
0
1*2
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
*1: Successive reads from the erasing or erase-suspend sector causes DQ2 to toggle.
*2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
DQ7
Data Polling
The MBM29SL800TD/BD devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” in ■FLOW CHART.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29SL800TD/BD data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
19
MBM29SL800TD-10/12/MBM29SL800BD-10/12
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags Table”.)
See “(6) Data Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the
Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29SL800TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) .
The OE and WE pins will control the output disable functions as described in “MBM29SL800TD/800BD User
Bus Operations Table (BYTE = VIH and BYTE = VIL)” (in ■DEVICE BUS OPERATION).
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun. If DQ3 is low (“0”) the device will accept additional sector erase commands. To insure
the command has been accepted, the system software should check the status of DQ3 prior to and following
each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not
have been accepted.
20
MBM29SL800TD-10/12/MBM29SL800BD-10/12
See “Hardware Sequence Flags Table”.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags Table” and “(15) DQ2 vs. DQ6” in ■TIMING
DIAGRAM.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7 to DQ0 on the following read cycle.
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status
of the operation. (Refer to “Toggle Bit Algorithm” in “■FLOW CHART”.)
Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle*1
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
DQ7
Toggle
1*2
Mode
Program
Erase-Suspend Program
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
21
MBM29SL800TD-10/12/MBM29SL800BD-10/12
RY/BY
Ready/Busy
The MBM29SL800TD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any
read/write or erase operation. If the MBM29SL800TD/BD are placed in an Erase Suspend mode, the RY/BY
output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “(8) RY/BY Timing Diagram during Program/Erase Operation
Timing Diagram” and “(9) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram.
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29SL800TD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to “(10) Timing Diagram for Word Mode Configuration” and “(11) Timing Diagram for Byte Mode Configuration”
and “(12) BYTE Timing Diagram for Write Operations” in ■TIMING DIAGRAM for the timing diagram.
Data Protection
The MBM29SL800TD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Protection
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressd to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in
■ FUNCTIONAL DESCRIPTION) .
22
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
Tstg
−55
+125
°C
TA
−40
+85
°C
VIN, VOUT
−0.5
VCC + 0.5
V
A9, OE, and RESET *1,*3
VIN
−0.5
+11.5
V
Power Supply Voltage *1
VCC
−0.5
+3.0
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins except A9,
OE, and RESET *1,*2
*1: Voltage is defined on the basis of VSS = GND = 0 V.
*2: Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.
*3: Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET
pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage
(VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +11.5 V which may
overshoot to +12.5 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Max
Unit
Ambient Temperature
TA
−40
+85
°C
Power Supply Voltage*
VCC
+1.8
+2.2
V
*: Voltage is defined on the basis of VSS = GND = 0 V.
Note: Operating ranges define those limits between which the proper device function is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
23
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
20 ns
20 ns
0.2 × VCC
−0.5 V
−2.0 V
20 ns
Figure 1
Maximum Undershoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
0.8 × VCC
20 ns
Figure 2
20 ns
Maximum Overshoot Waveform 1
20 ns
+12.5 V
+11.5 V
VCC + 0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.
Figure 3
24
Maximum Overshoot Waveform 2
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ DC CHARACTERISTICS
Parameter
Symbol
Value
Conditions
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
−1.0

+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
−1.0

+1.0
µA
A9, OE, RESET Inputs Leakage
Current
ILIT
VCC = VCC Max,
A9, OE, RESET = 11 V


35
µA




CE = VIL, OE = VIH,
f = 10 MHz
VCC Active Current *
1
ICC1
CE = VIL, OE = VIH,
f = 5 MHz
Byte
Word
Byte
Word
20
20
10
10
mA
mA
VCC Active Current *2
ICC2
CE = VIL, OE = VIH


25
mA
VCC Current (Standby)
ICC3
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V

1
5
µA
VCC Current (Standby, Reset)
ICC4
VCC = VCC Max,
RESET = VSS ± 0.3 V

1
5
µA
VCC Current
(Automatic Sleep Mode) *3
ICC5
VCC = VCC Max, CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V,
VIN = VCC ± 0.3 V or VSS ± 0.3 V

1
5
µA
Input Low Voltage
VIL

−0.5

0.2 × VCC
V
Input High Voltage
VIH

0.8 × VCC

VCC + 0.3
V
Voltage for Autoselect and Sector
Protection (A9, OE, RESET) *4, *5
VID

10
10.5
11
V
Output Low Voltage
VOL
IOL = 0.1 mA, VCC = VCC Min


0.1
V
Output High Voltage
VOH
IOH = −100 µA
VCC − 0.1


V
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4: This timing is only for Sector Protection operation and Autoselect mode.
*5: Applicable for only VCC applying.
25
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Symbol
Parameter
Value (Note)
Test Setup
-10
-12
Min
Max
Min
Max

100

120

ns
tACC
CE = VIL
OE = VIL

100

120
ns
tELQV
tCE
OE = VIL

100

120
ns
Output Enable to Output Delay
tGLQV
tOE


35

50
ns
Chip Enable to Output High-Z
tEHQZ
tDF


30

40
ns
Output Enable to Output High-Z
tGHQZ
tDF


30

40
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
tOH

0

0

ns
RESET Pin Low to Read Mode

tREADY


20

20
µs
CE to BYTE Switching Low or High

tELFL
tELFH


5

5
ns
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
Chip Enable to Output Delay
Note : Test Conditions :
Output Load : 1 TTL gate and 30 pF (MBM29SL800TD/BD-10)
1 TTL gate and 100 pF (MBM29SL800TD/BD-12)
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCC
Timing measurement reference level
Input : 0.5 × VCC
Output : 0.5 × VCC
VCC
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes : • CL = 30 pF including jig capacitance (MBM29SL800TD/BD-10)
• CL = 100 pF including jig capacitance (MBM29SL800TD/BD-12)
Figure 4
26
Unit
Test Conditions
MBM29SL800TD-10/12/MBM29SL800BD-10/12
• Write/Erase/Program Operations
Value
Symbol
Parameter
JEDEC Standard
-10
-12
Unit
Min
Typ
Max
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
100


120


ns
Address Setup Time
tAVWL
tAS
0


0


ns
Address Hold Time
tWLAX
tAH
50


60


ns
Data Setup Time
tDVWH
tDS
50


60


ns
Data Hold Time
tWHDX
tDH
0


0


ns
Output Enable Setup Time

tOES
0


0


ns
Output Enable Hold Read
Time
Toggle and Data Polling

tOEH
0


0


ns
10


10


ns
Read Recover Time Before Write
tGHWL
tGHWL
0


0


ns
Read Recover Time Before Write
tGHEL
tGHEL
0


0


ns
CE Setup Time
tELWL
tCS
0


0


ns
WE Setup Time
tWLEL
tWS
0


0


ns
CE Hold Time
tWHEH
tCH
0


0


ns
WE Hold Time
tEHWH
tWH
0


0


ns
Write Pulse Width
tWLWH
tWP
50


60


ns
CE Pulse Width
tELEH
tCP
50


60


ns
Write Pulse Width High
tWHWL
tWPH
30


30


ns
CE Pulse Width High
tEHEL
tCPH
30


30


ns
tWHWH1
tWHWH1

10.6


10.6

µs

14.6


14.6

µs
tWHWH2
tWHWH2

1.5


1.5

s

tVCS
50


50


µs

tVIDR
500


500


ns

tVLHT
4


4


µs
Byte
Programming
Operation
Word
Sector Erase Operation *
1
VCC Setup Time
2
Rise Time to VID *
Voltage Transition Time *
2

tWPP
100


100


µs
2

tOESP
4


4


µs
2
CE Setup Time to WE Active *

tCSP
4


4


µs
Recover Time From RY/BY

tRB
0


0


ns
RESET Pulse Width

tRP
500


500


ns
RESET Hold Time Before Read

tRH
200


200


ns
BYTE Switching Low to Output High-Z

tFLQZ


30


40
ns
BYTE Switching High to Output Active

tFHQV


100


120
ns
Program/Erase Valid to RY/BY Delay

tBUSY


90


90
ns
Delay Time from Embedded Output Enable

tEOE


100


120
ns
Power On/Off Timing

tPS
0


0


ns
Write Pulse Width *
2
OE Setup Time to WE Active *
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection operation.
27
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ ERASE AND PROGRAMMING PERFORMANCE
Parameter
Limits
Unit
Min
Typ
Max
Sector Erase Time

1.5
15
s
Word Programming Time

14.6
360
µs
Byte Programming Time

10.6
300
µs
Chip Programming Time

7.7
200
s
100,000


cycle
Program/Erase Cycle
Remarks
Excludes programming time prior to erasure
Excludes system-level overhead
Excludes system-level overhead
—
■ TSOP (I) PIN CAPACITANCE
Parameter
Symbol
Test Setup
Value
Unit
Typ
Max
7.5
9.5
pF
Input Capacitance
CIN
VIN = 0
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
10
13
pF
Notes : • Test conditions TA = +25 °C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
■ FBGA PIN CAPACITANCE
Parameter
Symbol
Test Setup
Value
Unit
Typ
Max
7.5
9.5
pF
Input Capacitance
CIN
VIN = 0
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
10
13
pF
Notes : • Test conditions TA = +25 °C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
■ SCSP PIN CAPACITANCE
Parameter
Symbol
Test Setup
Unit
Typ
Max
7.5
9.5
pF
Input Capacitance
CIN
VIN = 0
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
10
13
pF
Notes : • Test conditions TA = +25 °C, f = 1.0 MHz
• DQ15/A-1 pin capacitance is stipulated by output capacitance.
28
Value
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Change
from H to L
May
Change
from L to H
Will Change
from L to H
"H" or "L":
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
"Off" State
(1) Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
High-Z
Outputs
tOH
Outputs Valid
High-Z
29
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(2) Hardware Reset/Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CE
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
30
High-Z
Outputs Valid
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(3) Alternate WE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CE
tCS
tCH
tCE
OE
tGHWL
tWP
tOE
tWPH
tWHWH1
WE
Data
A0h
tOH
tDF
tDS tDH
PD
DQ7
DOUT
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
31
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(4) Alternate CE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
Data
A0h
tDH
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
32
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(5) Chip/Sector Erase Operation Timing Diagram
555h
Address
tWC
2AAh
tAS
555h
555h
2AAh
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
10h for Chip Erase
55h
80h
AAh
55h
Data
10h/
30h
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
Note : These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
33
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(6) Data Polling during Embedded Algorithm Operation Timing Diagram
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
Data
DQ7
DQ7 =
Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
DQ6 to DQ0 =
Outputs Flag
Data
tBUSY
DQ6 to DQ0
Valid Data
tEOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation) .
34
High-Z
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
Output
Valid
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation) .
35
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(8) RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
(9) RESET, RY/BY Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
36
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(10) Timing Diagram for Word Mode Configuration
CE
tCE
BYTE
Data Output
(DQ7 to DQ0)
DQ14 to DQ0
tELFH
Data Output
(DQ14 to DQ0)
tFHQV
A-1
DQ15/A-1
DQ15
(11) Timing Diagram for Byte Mode Configuration
CE
BYTE
DQ14 to DQ0
tELFL
Data Outputs
(DQ7 to DQ0)
Data Outputs
(DQ14 to DQ0)
tACC
DQ15/A-1
A-1
DQ15
tFLQZ
(12) BYTE Timing Diagram for Write Operations
Falling edge of the last write signal
CE or WE
Input
Valid
BYTE
tAS
tAH
37
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(13) Sector Protection Timing Diagram
A18, A17, A16
A15, A14, A13
A12
SPAX
SPAY
A6, A0
A1
VID
VIH
A9
VID
VIH
OE
tVLHT
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
01h
Data
tVCS
VCC
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
Note : A-1 is VIL on byte mode.
38
tOE
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(14) Temporary Sector Unprotection Timing Diagram
VCC
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
(15) DQ2 vs. DQ6
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
39
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(16) Extended Sector Protection Timing Diagram
VCC
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SPAX
SPAX
SPAY
A6, A0
A1
CE
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
tOE
SPAX
: Sector Address to be protected
SPAY
: Next Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
40
60h
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(17) Power ON/OFF Timing Diagram
tPS
tPS
RESET
VIH
VCC
0V
1.8 V
Address
Data
Input Valid
tRH
Output Valid
tACC
41
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ FLOW CHART
(1) Embedded ProgramTM Algorithm
EMBEDDED ALGORITHM
Start
Write Program
Command Sequence
(See Below)
Data Polling
No
No
Increment Address
Verify Data
?
Yes
Embedded
Program
Algorithm
in program
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Note : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
42
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(2) Embedded EraseTM Algorithm
EMBEDDED ALGORITHM
Start
Write Erase
Command Sequence
(See Below)
Data Polling
No
Data = FFh
?
Yes
Embedded
Erase
Algorithm
in progress
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address
/30h
Sector Address
/30h
Sector Address
/30h
Additional sector
erase commands
are optional.
Note : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
43
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(3) Data Polling Algorithm
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
= Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
operation.
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
*
No
Fail
Yes
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
44
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(4) Toggle Bit Algorithm
Start
Read DQ7 to DQ0
Addr. = VIH or VIL
*1
Read DQ7 to DQ0
Addr. = VIH or VIL
DQ6 =
Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7 to DQ0
Twice
Addr. = VIH or VIL
DQ6 =
Toggle?
*1, *2
No
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
45
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(5) Sector Protection Algorithm
Start
Setup Sector Addr.
(A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID
CE = VIL, RESET = VIH
A6 = A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector Group
A1 = VIH *
( Addr.A6= =SPA,
)
A0 = VIL
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
No
Data = 01h?
Yes
Protect Another
Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
* : A-1 is VIL on byte mode.
46
Yes
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(6) Temporary Sector Unprotection Algorithm
Start
RESET = VID
*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
*2
*1 : All protected sectors are unprotected.
*2 : All previously protected sectors are protected once again.
47
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(7) Extended Sector Protection Algorithm
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXh/60h
PLSCNT = 1
To Protect Secter
Write 60h to Secter Address
(A6 = A0 = VIL, A1 = VIH)
Time out 250 µs
To Verify Sector Protection
Write 40h to Secter Address
(A6 = A0 = VIL, A1 = VIH)
Increment PLSCNT
Read from Sector Address
(Addr. = SPA, A0 = VIL,
A1 = VIH, A6 = VIL)
No
Setup Next Sector Address
PLSCNT = 25?
Yes
No
Data = 01h?
Yes
Protect Other Group?
Remove VID from RESET
Write Reset Command
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
48
Yes
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(8) Embedded Programming Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
In Fast Program
Data Polling
Verify Data?
No
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXh/90h
Reset Fast Mode
XXXh/F0h
Note : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
49
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ ORDERING INFORMATION
50
Part No.
Package
Access Time (ns)
MBM29SL800TD-10PFTN
MBM29SL800TD-12PFTN
48-pin plastic TSOP (I)
(FPT-48P-M19)
Normal Bend
100
120
MBM29SL800TD-10PFTR
MBM29SL800TD-12PFTR
48-pin plastic TSOP (I)
(FPT-48P-M20)
Reverse Bend
100
120
MBM29SL800TD-10PBT
MBM29SL800TD-12PBT
48-pin plastic FBGA
(BGA-48P-M12)
100
120
MBM29SL800TD-10PW
MBM29SL800TD-12PW
48-pin plastic SCSP
(WLP-48P-M03)
100
120
MBM29SL800BD-10PFTN
MBM29SL800BD-12PFTN
48-pin plastic TSOP (I)
(FPT-48P-M19)
Normal Bend
100
120
MBM29SL800BD-10PFTR
MBM29SL800BD-12PFTR
48-pin plastic TSOP (I)
(FPT-48P-M20)
Reverse Bend
100
120
MBM29SL800BD-10PBT
MBM29SL800BD-12PBT
48-pin plastic FBGA
(BGA-48P-M12)
100
120
MBM29SL800BD-10PW
MBM29SL800BD-12PW
48-pin plastic SCSP
(WLP-48P-M03)
100
120
Sector Architecture
Top Sector
Bottom Sector
MBM29SL800TD-10/12/MBM29SL800BD-10/12
MBM29SL800
T
D − 10
TN
PACKAGE TYPE
TN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
TR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PBT = 48-Ball Fine Pitch Ball Grid Array
Package (FBGA)
PW = 48-Ball Super Chip Size Package
(SCSP)
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29SL800
8 Mega-bit (1 M × 8-Bit or 512 K × 16-Bit) CMOS Flash Memory
1.8 V-only Read, Program, and Erase
51
MBM29SL800TD-10/12/MBM29SL800BD-10/12
■ PACKAGE DIMENSIONS
48-pin plastic TSOP (I)
(FPT-48P-M19)
Note 1 : * : Resin Protrusion. (Each Side : 0.15 (.006) Max)
Note 2 : Pins width and pins thickness include plating thickness.
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
"A"
0.10(.004)
* 12.00±0.20
(.472±.008)
11.50REF
(.453)
+.004
.043 –.002
(Mounting
height)
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
TYP
+0.03
0.17 –0.08
+.001
.007 –.003
C
+0.10
1.10 –0.05
0.22±0.05
(.009±.002)
0.10(.004)
M
2001 FUJITSU LIMITED F48029S-c-4-5
Dimensions in mm (inches)
(Continued)
52
MBM29SL800TD-10/12/MBM29SL800BD-10/12
48-pin plastic TSOP (I)
(FPT-48P-M20)
Note 1 : * : Resin Protrusion. (Each Side : 0.15 (.006) Max)
Note 2 : Pins width and pins thickness include plating thickness.
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
+0.03
0.17 –0.08
+.001
0.10(.004)
.007 –.003
0.50(.020)
TYP
0.22±0.05
(.009±.002)
M
0.10±0.05
(.004±.002)
(Stand off height)
+0.10
"A"
1.10 –0.05
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
0.10(.004)
11.50(.453)REF
+.004
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
2001 FUJITSU LIMITED F48030S-c-4-5
Dimensions in mm (inches)
(Continued)
53
MBM29SL800TD-10/12/MBM29SL800BD-10/12
48-ball plastic FBGA
(BGA-48P-M12)
+0.15
9.00±0.20(.354±.008)
+.006
1.05 –0.10 .041 –.004
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
5.60(.220)
0.80(.031)TYP
6
5
INDEX
6.00±0.20
(.236±.008)
4
4.00(.157)
3
2
1
H
C0.25(.010)
G
F
E
D
48-ø0.45±0.10
(48-ø.018±.004)
C
B
A
ø0.08(.003)
M
0.10(.004)
C
2001 FUJITSU LIMITED B48012S-c-3-3
Dimensions in mm (inches)
(Continued)
54
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(Continued)
48-ball plastic SCSP
(WLP-48P-M03)
(3.50=0.50x7)
((.138=.020x7))
7.06±0.10(.278±.004)
0.50(.020)
TYP
Y
(0.13SQ)
((.005SQ))
3.52±0.10
(.139±.004)
(INDEX)
(2.50=0.50x5)
((.098=.020x5))
(0.25(.010)
INDEX AREA
(LASER MARKING)
0.50(.020)
TYP
X
4-Ø0.13(4-Ø.005)
1.00(.039)
Max.
Z
C
0.10(.004) Z
(2.25)
((.089))
0.25(.010)
Min.
48-Ø0.35±0.10
(48-Ø.014±.004)
0.08(.003)
M
XYZ
(Stand off)
2001 FUJITSU LIMITED W48003S-c-1-1
Dimensions in mm (inches)
55
MBM29SL800TD-10/12/MBM29SL800BD-10/12
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0210
 FUJITSU LIMITED Printed in Japan