STMICROELECTRONICS CRX14-MQP

CRX14
Low Cost ISO14443 type-B Contactless Coupler Chip
with Anti-Collision, CRC Management and Anti-Clone Function
FEATURES SUMMARY
■
■
■
■
Single 5V ±500mV Supply Voltage
SO16N package
Contactless Communication
– ISO14443 type-B protocol
– 13.56MHz Carrier Frequency using an
External Oscillator
– 106 Kbit/s Data Rate
– 36 Byte Input/Output Frame Register
– Supports Frame Answer with/without
SOF/EOF
– CRC Generation and Check
– France Telecom Proprietary Anti-Clone
Function
– Automated ST Anti-Collision Exchange
I²C Communication
– Two Wire I²C Serial Interface
– Supports 400kHz Protocol
– 3 Chip Enable Pins
– Up to 8 CRX14 Connected on the Same
Bus
July 2005
Figure 1. Delivery Form
16
1
SO16 (MQ)
150 mils width
1/40
CRX14
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Delivery Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Oscillator (OSC1, OSC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Antenna Output Driver (RFOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Antenna Input Filter (RFIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transmitter Reference Voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Supply (VCC, GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. CRX14 Application Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I²C Bus . . . . . . . . . . . . . . . . 8
CRX14 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. CRX14 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Parameter Register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Parameter Register Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Frame Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Input/Output Frame Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Authenticate Register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Slot Marker Register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Slot Marker Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CRX14 I²C PROTOCOL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Acknowledge Bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. I²C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I²C Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CRX14 I²C Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. CRX14 I²C Write Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. I²C Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CRX14 I²C Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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CRX14
Figure 10.CRX14 I²C Read Modes Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
APPLYING THE I²C PROTOCOL TO THE CRX14 REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I²C Parameter Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.Host-to-CRX14 Transfer: I²C Write to Parameter Register . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.CRX14-to-Host Transfer: I²C Random Address Read from Parameter Register . . . . . . 17
Figure 13.CRX14-to-Host Transfer: I²C Current Address Read from Parameter Register . . . . . . . 17
I²C Input/Output Frame Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14.Host-to-CRX14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B . . . 18
Figure 15.CRX14-to-Host Transfer: I²C Random Address Read
from Input/Output Frame Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16.CRX14-to-Host Transfer: I²C Current Address Read
from I/O Frame Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I²C Authenticate Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I²C Slot Marker Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17.Host-to-CRX14 Transfer: I²C Write to Slot Marker Register . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18.CRX14-to-Host Transfer: I²C Random Address Read from Slot Marker Register . . . . . 19
Figure 19.CRX14-to-Host Transfer: I²C Current Address Read from Slot Marker Register . . . . . . 19
Addresses above Location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CRX14 ISO14443 TYPE-B RADIO FREQUENCY DATA TRANSFER . . . . . . . . . . . . . . . . . . . . . . . . 21
Output RF Data Transfer from the CRX14 to the PICC (Request Frame) . . . . . . . . . . . . . . . . . 21
Figure 20.Wave Transmitted using ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Transmission Format of Request Frame Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21.CRX14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. CRX14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 22.Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 23.Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input RF Data Transfer from the PICC to the CRX14 (Answer Frame) . . . . . . . . . . . . . . . . . . . 23
Figure 24.Wave Received using BPSK Sub-carrier Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Transmission Format of Answer Frame Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25.Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 26.Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 27.Example of a Complete Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 28.CRC Transmission Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TAG ACCESS USING THE CRX14 COUPLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Standard TAG Command Access Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 29.Standard TAG Command: Request Frame Transmission. . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 30.Standard TAG Command: Answer Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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CRX14
Figure 31.Standard TAG Command: Complete TAG Access Description . . . . . . . . . . . . . . . . . . . 27
Anti-Collision TAG Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32.Anti-Collision ST short range memory Sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33.Anti-Collision ST short range memory Sequence Continued . . . . . . . . . . . . . . . . . . . . . 29
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. I²C AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 34.I²C AC Testing I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. I²C Input Parameters(1,2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11. I²C DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 35.I²C AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. I²C AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 36.CRX14 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. RFOUT AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. RFIN AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 37.SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Outline . . 36
Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX A.ISO14443 TYPE B CRC CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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CRX14
SUMMARY DESCRIPTION
The CRX14 is a contactless coupler that is compliant with the short range ISO14443 type-B standard. It is controlled using the two wire I²C bus.
The CRX14 generates a 13.56MHz signal on an
external antenna. Transmitted data are modulated
using Amplitude Shift Keying (ASK). Received
data are demodulated from the PICC (Proximity integrated Coupling Card) load variation signal, induced on the antenna, using Bit Phase Shift
Keying (BPSK) of a 847kHz sub-carrier. The
Transmitted ASK wave is 10% modulated. The
Data transfer rate between the CRX14 and the
PICC is 106 Kbit/s in both transmission and reception modes.
The CRX14 follows the ISO14443 type-B recommendation for Radio frequency power and signal
interface.
The CRX14 is specifically designed for short range
applications that need disposable, or secure and
re-usable, products.
The CRX14 includes an automated anti-collision
mechanism that allows it to detect and select any
ST short range memories that are present at the
same time within its range. The anti-collision
mechanism is based on the STMicroelectronics
probabilistic scanning method.
The CRX14 provides an anti-clone function, from
FRANCE
TELECOM,
which
allows
the
authentication of the ST short range memories.
Using the CRX14 single chip coupler, therefore, it
is easy to design a reader, with authentication capability and to build an end application with a high
level of security at low cost.
The CRX14 provides a complete analog interface,
compliant
with
the
ISO14443
type-B
recommendations for Radio-Frequency power
and signal interfacing. With it, any ISO14443 typeB PICC products can be powered and have their
data transmission controlled via a simple antenna.
The CRX14 is fabricated in STMicroelectronics
High Endurance Single Poly-silicon CMOS technology.
The CRX14 is organized as 4 different blocks (see
Figure 3.):
■
The I²C bus controller. It handles the serial
connection with the application host. It is
compliant with the 400kHz I²C bus
specification, and controls the read/write
access to all the CRX14 registers.
■
The RAM buffer. It is bi-directional. . It stores
all the request frame Bytes to be transmitted to
the PICC, and all the received Bytes sent by
the PICC on the answer frame.
■
The transmitter. It powers the PICCs by
generating a 13.56MHz signal on an external
antenna. The resulting field is 10% modulated
using ASK (amplitude shift keying) for
outgoing data.
■
The receiver. It demodulates the signal
generated on the antenna by the load variation
of the PICC. The resulting signal is decoded
by a 847kHz BPSK (binary phase shift keying)
sub-carrier decoder.
The CRX14 is designed to be connected to a digital host (Microcontroller or ASIC). This host has to
manage the entire communication protocol in both
transmit and receive modes, through the I²C serial
bus.
Figure 2. Logic Diagram
VCC
VREF
RFOUT
OSC1
OSC2
SCL
SDA
E0
E1
E2
CRX14
Antenna
RFIN
GND
GND_RF
AI06828B
Table 1. Signal Names
RFOUT
Antenna Output Driver
RFIN
Antenna Input Filter
OSC1
Oscillator Input
OSC2
Oscillator Output
E0, E1, E2
Chip Enable Inputs
SDA
I²C Bi-Directional Data
SCL
I²C Clock
VCC
Power Supply
GND
Ground
VREF
Transmitter Reference Voltage
GND_RF
Ground for RF circuitry
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CRX14
Figure 3. Logic Block Diagram
Figure 4. SO Pin Connections
SO16
VCC
VREF
CRX14
Transmitter
GND
RFOUT
OSC2
Antenna
Receiver
RAM Buffer
SCL
SDA
E0
E1
E2
I²C Bus Controller
OSC1
RFIN
GND_RF
AI10910
6/40
VREF
RFIN
E0
E1
E2
GND_RF
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
RFOUT
GND_RF
OSC1
OSC2
GND
SCL
SDA
AI10911
CRX14
SIGNAL DESCRIPTION
See Figure 2., and Table 1., for an overview of the
signals connected to this device.
Oscillator (OSC1, OSC2). The OSC1 and OSC2
pins are internally connected to the on-chip oscillator circuit. The OSC1 pin is the input pin, the
OSC2 is the output pin. For correct operation of
the CRX14, it is required to connect a 13.56MHz
quartz crystal across OSC1 and OSC2. If an external clock is used, it must be connected to OSC1
and OSC2 must be left open.
Antenna Output Driver (RFOUT). The Antenna
Output Driver pin, RFOUT, generates the modulated 13.56MHz signal on the antenna. Care must be
taken as it will not withstand a short-circuit.
RFOUT has to be connected to the antenna circuitry as shown in Figure 5. The LRC antenna circuitry
must be connected across the RFOUT pin and
GND.
Antenna Input Filter (RFIN). The antenna input
filter of the CRX14, RFIN, has to be connected to
the external antenna through an adapter circuit, as
shown in Figure 5.
The input filter demodulates the signal generated
on the antenna by the load variation of the PICC.
The resulting signal is then decoded by the
847kHz BPSK decoder.
Transmitter Reference Voltage (VREF). The
Transmitter Reference Voltage input, VREF, provides a reference voltage used by the output driver
for ASK modulation.
The Transmitter Reference Voltage input should
be connected to an external capacitor, as shown in
Figure 5.
Serial Clock (SCL). The SCL input pin is used to
strobe all I²C data in and out of the CRX14. In applications where this line is used by slave devices
to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up
resistor must be connected from the Serial Clock
(SCL) to VCC. ( Figure 6. indicates how the value
of the pull-up resistor can be calculated).
In most applications, though, this method of synchronization is not employed, and so the pull-up
resistor is not necessary, provided that the master
has a push-pull (rather than open drain) output.
Serial Data (SDA). The SDA signal is bi-directional. It is used to transfer I²C data in and out of
the CRX14. It is an open drain output that may be
wire-OR’ed with other open drain or open collector
signals on the bus. A pull-up resistor must be connected from Serial data (SDA) to VCC. (Figure 6.
indicates how the value of the pull-up resistor can
be calculated).
Chip Enable (E0, E1, E2). The Chip Enable inputs E0, E1, E2 are used to set and reset the value
on the three least significant bits (b3, b2, b1) of the
7-bit I²C Device Select Code. They are used for
hardwired addressing, allowing up to eight CRX14
devices to be addressed on the same I²C bus.
These inputs may be driven dynamically or tied to
VCC or GND to establish the Device Select Code
(note that the VIL and VIH levels for the inputs are
CMOS compatible, not TTL compatible).
When left open, E0, E1 and E2 are internally read
at the logic level 0 due to the internal pull-down resistors connected to each inputs.
Power Supply (VCC, GND, GND_RF). Power is
supplied to the CRX14 using the VCC, GND and
GND_RF pins.
VCC is the Power Supply pin that supplies the power (+5V) for all CRX14 operations.
The GND and GND_RF pins are ground connections. They must be connected together.
Decoupling capacitors should be connected between the VCC Supply Voltage pin, the GND
Ground pin and the GND_REF Ground pin to filter
the power line, as shown in Figure 5.
7/40
CRX14
Figure 5. CRX14 Application Schematic
D1
1N4148 (OPTIONAL)
C6VCC
C8
100pF50V
VCC
100nF50V
C5
10pF50V R8
0R
OPT
OPT
R1
WURTH 742-792-042U1
FL7
1
VREF
VCC
2
R5
RFIN RFOUT
22nF50V
3
E0
GND_RF
4
E1
OSC1
5
E2
OSC2
6
E2
GND_RF GND
7
0R
GND
SCL
8
GND
SDA
R6
CRX14
OPT C3
R3
E0
0R
E1
0R
R2
R4
C1 7pF50V
16
15
14
13
12
11
10
9
X1
13.56MHz
C8'
8pF50V
ANT1
C7
C7'
120pF50V 33pF50V
C2 7pF50V
R7
ANT2
0R
J1
4
3
2
1
SDASCL
FL5 0R
FL4
0R
FL6
0R
VCC
+ C4
22uF 10V
AI10952
Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I²C Bus
VCC
Maximum RP value (kΩ)
20
16
RL
12
RL
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
CBUS
SCL
CBUS
0
10
100
1000
CBUS (pF)
AI01665
8/40
CRX14
CRX14 REGISTERS
The CRX14 chip coupler contains six volatile registers. It is entirely controlled, at both digital and
analog level, using the four registers listed below
and shown in Table 2.:
■
Parameter Register
■
Input/Output Frame Register
■
Authentication Register
■
Slot Marker Register
The other 2 registers are located at addresses 04h
and 05h. They are “ST Reserved”, and must not
be used in end-user applications.
In the I²C protocol, all data Bytes are transmitted
Most Significant Byte first, with each Byte transmitted Most significant bit first.
Table 2. CRX14 Control Registers
Address
Length
00h
Parameter Register
1 Byte
01h
Input/output Frame Register
36 Bytes
Access
Purpose
W
Set parameter register
R
Read parameter register
W
Store and send request frame to the PICC.
Wait for PICC answer frame
R
Transfer PICC answered frame data to Host
W
Start the Authentication process
R
Get the Authentication status
W
Launch the automated anti-collision process
from Slot_0 to Slot_15
R
Return data FFh
02h
Authenticate Register
NA
03h
Slot Marker Register
1 Byte
04h
ST Reserved
NA
R and W ST Reserved. Must not be used
05h
ST Reserved
NA
R and W ST Reserved. Must not be used
Parameter Register (00h)
The Parameter Register is an 8-bit volatile register
used to configure the CRX14, and thus, to customize the circuit behavior. The Parameter Register is
located at the I²C address 00h and it is accessible
in I²C Read and Write modes. Its default value,
00h, puts the CRX14 in standard ISO14443 typeB configuration.
Table 3. Parameter Register Bits Description
Bit
Control
b0
Frame Standard
b1
RFU
b2
Answer Frame Format
b3
ASK Modulation Depth
b4
Carrier Frequency
b5
Value
Description
0
ISO14443 type-B frame management
1
RFU
0
Not used
0
Answer PICC Frames are delimited by SOF and EOF
1
Answer PICC Frames do not provide SOF and EOF delimiters
0
10% ASK modulation depth mode
1
RFU
0
13.56MHz carrier on RF OUT is OFF
1
13.56MHz carrier on RF OUT is ON
b6
tWDG
Answer delay watchdog
b5=0, b6=0: Watchdog time-out = 500µs to be used for read
b5=0, b6=1: Watchdog time-out = 5ms to be used for authentication
b5=1, b6=0: Watchdog time-out = 10ms to be used for write
b5=1, b6=1: Watchdog time-out = 309ms to be used for MCU timings
b7
RFU
0
Not used
Note: RFU = Reserved for Future Use.
9/40
CRX14
Input/Output Frame Register (01h)
The Input/Output Frame Register is a 36-Byte
buffer that is accessed serially from Byte 0 through
to Byte 35 (see Table 4.). It is located at the I²C address 01h.
The Input/Output Frame Register is the buffer in
which the CRX14 stores the data Bytes of the request frame to be sent to the PICC. It automatically stores the data Bytes of the answer frame
received from the PICC. The first Byte (Byte 0) of
the Input/Output Frame Register is used to store
the frame length for both transmission and reception.
When accessed in I²C Write mode , the register
stores the request frame Bytes that are to be
transmitted to the PICC. Byte 0 must be set with
the request frame length (in Bytes) and the frame
is stored from Byte 1 onwards. At the end of the
transmission, the 16-bit CRC is automatically added. After the transmission, the CRX14 wait for the
PICC to send back an answer frame. When correctly decoded, the PICC answer frame Bytes are
stored in the Input/Output Frame Register from
Byte 1 onwards. Byte 0 stores the number of Bytes
received from the PICC.
When accessed in I²C Read mode, the Input/Output Register sends back the last PICC answer
frame Bytes, if any, with Byte 0 transmitted first.
The 16-bit CRC is not stored, and it is not sent
back on the I²C bus.
The Input/Output Frame Register is set to all 00h
between transmission and reception. If there is no
answer from the PICC, Byte 0 is set to 00h. In the
case of a CRC error, Byte 0 is set to FFh, and the
data Bytes are discarded and not appended in the
register.
The CRX14 Input/Output Frame Register is so designed as to generate all the ST short range memory command frames. It can also generate all
standardized ISO14443 type-B command frames
like REQB, SLOT-MARKER, ATTRIB, HALT, and
get all the answers like ATQB, or answer to ATTRIB. All ISO14443 type-B compliant PICCs can
be accessed by the CRX14 provided that their
data frame exchange is not longer than 35 Bytes
in both request and answer.
Table 4. Input/Output Frame Register Description
Byte 0
Byte 1
Byte 2
Frame Length
First data Byte
Second data Byte
Byte 3
...
Byte 34
Byte 35
Last data Byte
<------------- Request and Answer Frame Bytes exchanged on the RF ------------->
00h No Byte transmitted
FFh CRC Error
xxh Number of transmitted Bytes
Authenticate Register (02h)
The Authenticate Register is used to trigger the
complete authentication exchange between the
CRX14 and the secured ST short range memory.
It is located at the I²C address 02h.
The Authentication system is based on a proprietary challenge/response mechanism that allows
the application software to authenticate a secured
ST short range memory of the SRXxxx family. A
reader designed with the CRX14 can check the
authenticity of a memory device and protect the
application system against silicon copies or emulators.
A complete description of the Authentication system is available under Non Disclosure Agreement
(NDA) with STMicroelectronics. For more details
about this CRX14 function, please contact the
nearest STMicroelectronics sales office.
Slot Marker Register (03h)
The slot Marker Register is located at the I²C address 03h. It is used to trigger an automated anti-
10/40
collision sequence between the CRX14 and any
ST short range memory present in the electromagnetic field. With one I²C access, the CRX14
launches a complete stream of commands starting
from
PCALL16(),
SLOT_MARKER(1),
SLOT_MARKER(2) up to SLOT_MARKER(15),
and stores all the identified Chip_IDs into the Input/Output Frame Register (I²C address 01h).
This automated anti-collision sequence simplifies
the host software development and reduces the
time needed to interrogate the 16 slots of the STMicroelectronics anti-collision mechanism.
When accessed in I²C Write mode, the Slot Marker
Register starts generating the sequence of anticollision commands. After each command, the
CRX14 wait for the ST short range memory answer frame which contains the Chip_ID. The validity of the answer is checked and stored into the
corresponding Status Slot Bit (Byte 1 and Byte 2
as described in Table 6.). If the answer is correct,
the Status Slot Bit is set to ‘1’ and the Chip_ID is
stored into the corresponding Slot_Register. If no
answer is detected, the Status Slot Bit is set to ‘0’,
and the corresponding Slot_Register is set to 00h.
CRX14
If a CRC error is detected, the Status Slot Bit is set
to ‘0’, and the corresponding Slot_Register is set
to FFh.
Each time the Slot Marker Register is accessed in
I²C Write mode, Byte 0 of the Input/Output Frame
Register is set to 18, Bytes 1 and 2 provide Status
Bits Slot information, and Bytes 3 to 18 store the
corresponding Chip_ID or error code.
The Slot Marker Register cannot be accessed in
I²C Read mode. All the anti-collision data can be
accessed by reading the Input/Output Frame Register at the I²C address 01h.
Table 5. Slot Marker Register Description
b7
b6
b5
Byte 1
Status Slot
Bit 7
Status Slot
Bit 6
Status Slot
Bit 5
Status Slot
Bit 4
Byte 2
Status Slot
Bit 15
Status Slot
Bit 14
Status Slot
Bit 13
Status Slot
Bit 12
Byte 0
b4
b3
b2
b1
b0
Status Slot
Bit 3
Status Slot
Bit 2
Status Slot
Bit 1
Status Slot
Bit 0
Status Slot
Bit 11
Status Slot
Bit 10
Status Slot
Bit 9
Status Slot
Bit 8
Number of stored Bytes: fixed to 18
Byte 3
Slot_Register 0 = Chip_ID value detected in Slot 0
Byte 4
Slot_Register 1 = Chip_ID value detected in Slot 1
Byte 5
Slot_Register 2 = Chip_ID value detected in Slot 2
Byte 6
Slot_Register 3 = Chip_ID value detected in Slot 3
Byte n
.....
Byte 17
Slot_Register 14 = Chip_ID value detected in Slot 14
Byte 18
Slot_Register 15 = Chip_ID value detected in Slot 15
Status bit value description:
1: No error detected. The Chip_ID stored in the Slot register is valid.
0: Error detected
- Slot register = 00h: No answer frame detected from ST short range memory
- Slot register = FFh: Answer Frame detected with CRC error. Collision may have occurred
11/40
CRX14
CRX14 I²C PROTOCOL DESCRIPTION
The CRX14 is compatible with the I²C serial bus
memory standard, which is a two-wire serial interface that uses a bi-directional data bus and serial
clock.
The CRX14 has a pre-programmed, 4-bit identification code, ’1010’ (as shown in Table 6.), that
corresponds to the I²C bus definition. With this
code and the three Chip Enable inputs (E2, E1,
E0) up to eight CRX14 devices can be connected
to the I²C bus, and selected individually.
The CRX14 behaves as a slave device in the I²C
protocol, with all CRX14 operations synchronized
to the serial clock.
I²C Read and Write operations are initiated by a
START condition, generated by the bus master.
The START condition is followed by the Device
Select Code and by a Read/Write bit (R/W). It is
terminated by an acknowledge bit. The Device Select Code consists of seven bits (as shown in Table 6.):
■
the Device Code (first four bits)
■
plus three bits corresponding to the states of
the three Chip Enable inputs, E2, E1 and E0,
respectively
When data is written to the CRX14, the device inserts an acknowledge bit (9th bit) after the bus
master’s 8-bit transmission.
When the bus master reads data, it also acknowledges the receipt of the data Byte by inserting an
acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition
after an ACK for Write, or after a NoACK for Read.
The CRX14 supports the I²C protocol, as summarized in Figure 7.
Any device that sends data on to the bus, is defined as a transmitter, and any device that reads
the data, as a receiver.
The device that controls the data transfer is known
as the master, and the other, as the slave. A data
transfer can only be initiated by the master, which
also provides the serial clock for synchronization.
The CRX14 is always a slave device in all I²C communications. All data are transmitted Most Significant Bit (MSB) first.
Table 6. Device Select Code
Device Code
CRX14 Select
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
I²C Start Condition
START is identified by a High-to-Low transition of
the Serial Data line, SDA, while the Serial Clock,
SCL, is stable in the High state. A START condition must precede any data transfer command.
The CRX14 continuously monitors the SDA and
SCL lines for a START condition (except during
Radio Frequency data exchanges), and will not respond unless one is sent.
I²C Stop Condition
STOP is identified by a Low-to-High transition of
the Serial Data line, SDA, while the Serial Clock,
SCL, is stable in the High state.
A STOP condition terminates communications between the CRX14 and the bus master.
A STOP condition at the end of an I²C Read command, after (and only after) a NoACK, forces the
CRX14 into its stand-by state.
12/40
Chip Enable
A STOP condition at the end of an I²C Write command triggers the Radio Frequency data exchange between the CRX14 and the PICC.
I²C Acknowledge Bit (ACK)
An acknowledge bit is used to indicate a successful data transfer on the I²C bus.
The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending 8 bits of
data. During the 9th clock pulse the receiver pulls
the SDA line Low to acknowledge the receipt of
the 8 data bits.
I²C Data Input
During data input, the CRX14 samples the SDA
bus signal on the rising edge of the Serial Clock,
SCL. For correct device operation, the SDA signal
must be stable during the Low-to-High Serial
Clock transition, and the data must change only
when the SCL line is Low
CRX14
Figure 7. I²C Bus Protocol
SCL
SDA
START
CONDITION
SCL
1
SDA
MSB
SDA
INPUT
2
SDA
CHANGE
STOP
CONDITION
3
7
8
9
ACK
START
CONDITION
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
CONDITION
AI00792
I²C Memory Addressing
To start up communication with the CRX14, the
bus master must initiate a START condition. Then,
the bus master sends 8 bits (with the most significant bit first) on the Serial Data line, SDA. These
bits consist of the Device Select Code (7 bits) plus
a RW bit.
According to the I²C bus definition, the seven most
significant bits of the Device Select Code are the
Device Type Identifier. For the CRX14, these bits
are defined as shown in Table 6.
The 8th bit is the Read/Write bit (RW). It is set to
‘1’ for I²C Read, and to ‘0’ for I²C Write operations.
If the data sent by the bus master matches the Device Select Code of a CRX14 device, the corresponding device returns an acknowledgment on
the SDA bus during the 9th bit time.
The CRX14 devices whose Device Select Codes
do not correspond to the data sent, generate a No-
ACK. They deselect themselves from the bus and
go into stand-by mode.
CRX14 I²C Write Operations
The bus master sends a START condition, followed by a Device Select Code and the R/W bit set
to ’0’. The CRX14 that corresponds to the Device
Select Code, acknowledges and waits for the bus
master to send the Byte address of the register
that is to be written to. After receipt of the address,
the CRX14 returns another ACK, and waits for the
bus master to send the data Bytes that are to be
written.
In the CRX14 I²C Write mode, the bus master may
sends one or more data Bytes depending on the
selected register.
The CRX14 replies with an ACK after each data
Byte received. The bus master terminates the
transfer by generating a STOP condition.
13/40
CRX14
The STOP condition at the end of a Write access
to the Input/Output Frame, Authenticate or AntiCollision Register, causes the Radio Frequency
data exchange between the CRX14 and the PICC
to be started.
During the Radio Frequency data exchange, the
CRX14 disconnects itself from the I²C bus. The
time (tRFEX) needed to complete the exchange is
not fixed as it depends on the PICC command format. To know when the exchange is complete, the
bus master uses an ACK polling sequence as
shown in Figure 9. It consists of the following:
■
■
■
Initial condition: a Radio Frequency data
exchange is in progress.
Step 1: the master issues a START condition
followed by the first Byte of the new instruction
(Device Select Code plus R/W bit).
Step 2: if the CRX14 is busy, no ACK is
returned and the master goes back to Step 1.
If the CRX14 has completed the Radio
Frequency data exchange, it responds with an
ACK, indicating that it is ready to receive the
second part of the next instruction (the first
Byte of this instruction being sent during Step
1).
R/W
DEV SEL
BYTE ADDR
DATA 1
DATA 2
DATA N
DATA 3
STOP
BUS Master
START
Figure 8. CRX14 I²C Write Mode Sequence
CRX14 WRITE
BUS Slave
ACK
ACK
ACK
ACK
ACK
ACK
AI09265
14/40
CRX14
Figure 9. I²C Polling Flowchart using ACK
Radio Frequency
data exchange
in progress
START Condition
DEVICE SELECT
CODE with R/W=1
NO
First byte of instruction
with R/W = 1 already
decoded by the CRX14
YES
NO
ReSTART
ACK
returned
Next
operation is
addressing
the CRX14
YES
Proceed to READ
Operation
STOP
STOP
ai09234
15/40
CRX14
CRX14 I²C Read Operations
To send a Read command, the bus master sends
a START condition, followed by a Device Select
Code and the R/W bit set to ’1’.
The CRX14 that corresponds to the Device Select
Code acknowledges and outputs the first data
Byte of the addressed register.
To select a specific register, a dummy Write command must first be issued, giving an address Byte
but no data Bytes, as shown in the bottom half of
Figure 10. This causes the new address to be
stored in the internal address pointer, for use by
the Read command that immediately follows the
dummy Write command.
In the I²C Read mode, the CRX14 may read one
or more data Bytes depending on the selected register. The bus master has to generate an ACK after each data Byte to read all the register data in a
continuous stream. Only the last data Byte should
not be followed by an ACK. The master then terminates the transfer with a STOP condition, as
shown in Figure 10.
After reading each Byte, the CRX14 waits for the
master to send an ACK during the 9th bit time. If
the master does not return an ACK within this time,
the CRX14 terminates the data transfer and
switches to stand-by mode.
Figure 10. CRX14 I²C Read Modes Sequences
ACK
R/W
ACK
ACK
ACK
NoACK
STOP
BUS Master
START
I²C CURRENT ADDRESS READ
DEV SEL
CRX14 READ
DATA 1
BUS Slave
DATA 2
DATA 3
DATA 4
DATA N
ACK
DEV SEL
ADDRESS
R/W
ACK
ACK
NoACK
STOP
R/W
Re-START
BUS Master
START
I²C RANDOM ADDRESS READ
DEV SEL
CRX14 READ
DATA 1
BUS Slave
ACK
ACK
DATA 2
DATA N
ACK
AI09266
16/40
CRX14
APPLYING THE I²C PROTOCOL TO THE CRX14 REGISTERS
I²C Parameter Register Protocol
Figure 11. shows how new data is written to the
Parameter Register. The new value becomes active after the I²C STOP condition.
Figure 12. shows how to read the Parameter Register contents. The CRX14 sends and re-sends the
Parameter Register contents until it receives a
NoACK from the I²C Host.
The CRX14 supports the I²C Current Address and
Random Address Read modes. The Current Address Read mode can be used if the previous
command was issued to the register where the
Read is to take place.
Figure 11. Host-to-CRX14 Transfer: I²C Write to Parameter Register
Bus Master
CRX14 Write
S
T
A
R
T
R/W
Device Select
Code
Parameter Register
Address
1 0 1 0 X X X
00h
Register Byte
Value
S
T
O
P
data
Bus Slave
ACK
ACK
ACK
ai09240
Figure 12. CRX14-to-Host Transfer: I²C Random Address Read from Parameter Register
Bus Master
CRX14 Read
S
T
A
R
T
R
E
S
T
A
R
T
R/W
Device Select
Code
Parameter Register
Address
1 0 1 0 X X X
00h
R/W
Device Select
Code
ACK
S
T
O
P
data
1 0 1 0 X X X
Bus Slave
ACK
NoACK
ACK
Register Byte
Value
ai09241
Figure 13. CRX14-to-Host Transfer: I²C Current Address Read from Parameter Register
Bus Master
CRX14 Read
S
T
A
R
T
R/W
NoACK
Device Select
Code
S
T
O
P
data
1 0 1 0 X X X
Bus Slave
ACK
Register Byte
Value
ai09242
17/40
CRX14
I²C Input/Output Frame Register Protocol
Figure 14. shows how to store a PICC request
frame command of N Bytes into the Input/Output
Frame Register.
After the I²C STOP condition, the request frame is
RF transmitted in the ISO14443 type-B format.
The CRX14 then waits for the PICC answer frame
which will also be stored in the Input/Output Frame
Register. The request frame is over-written by the
answer frame.
Figure 15. shows how to read an N-Byte PICC answer frame.
The two CRC Bytes generated by the PICC are
not stored.
The CRX14 continues to output data Bytes until a
NoACK has been generated by the I²C Host, and
received by the CRX14. After all 36 Bytes have
been output, the CRX14 “rolls over”, and starts
outputting from the start of the Input/Output Frame
Register again.
The CRX14 supports the I²C Current Address and
Random Address Read modes. The Current Address Read mode can be used if the previous
command was issued to the register where the
Read is to take place.
Figure 14. Host-to-CRX14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B
Bus
Master
CRX14
Write
S
T
A
R
T
R/W
Device
Select
Code
Input/Output
Register
Address
1 0 1 0 XX X
Bus
Slave
PICC
Command
Code
Request Frame
Length N
01h
N
ACK
Data 1
ACK
ACK
PICC
Command
Parameter
PICC
Command
Parameter
PICC
Command
Parameter
Data 2
ACK
S
T
O
P
Data N
ACK
ACK
ACK
ai09243
Figure 15. CRX14-to-Host Transfer: I²C Random Address Read
from Input/Output Frame Register for ISO14443B
R/W
S
Device
T
Select
Bus
A
Code
Master R
T
CRX14
1 0 1 0XXX
Read
Bus
Slave
Input/Output
Register
Address
01h
ACK
R
E
S
T
A
R
T
ACK
ACK
R/W
ACK
NoACK
ACK
Device
Select
Code
S
T
O
P
N
1 0 1 0 XXX
Data1
Received
ACK Frame
Length
ACK
Data 2
Answer
Frame
Data
Data N
Answer
Frame
Data
Answer
Frame
Data
Answer
Frame
Data
ai09243
Figure 16. CRX14-to-Host Transfer: I²C Current Address Read
from I/O Frame Register for ISO14443B
Bus Master
CRX14 Write
S
T
A
R
T
ACK
ACK
R/W
ACK
ACK
NoACK
Device
Select
Code
S
T
O
P
1 0 1 0 XX X
N
Bus Slave
ACK
Data 1
Answer Frame
Received
Data
Frame Length
Data 2
Answer Frame
Data
Data N
Answer Frame
Data
Answer Frame
Data
ai09245
18/40
CRX14
I²C Authenticate Register Protocol
For information please contact your nearest STMicroelectronics sales office.
I²C Slot Marker Register Protocol
An I²C Write command to the Slot Marker Register
generates an automated sixteen-command loop
(See Figure 17. for a description of the command).
All the answers from the ST short range memory
devices that are detected, are written in the Input/
Output Frame Register.
Read from the I²C Slot Marker Register is not supported by the CRX14. If the I²C Host tries to read
the Slot Marker Register, the CRX14 will return the
data value FFh in both Random Address and Current Address Read modes until NoACK is generated by the I²C Host.
The result of the detection sequence is stored in
the Input/Output Frame Register. This Register
can be read by the host by using I²C Random Address Read.
Figure 17. Host-to-CRX14 Transfer: I²C Write to Slot Marker Register
Bus Master
S
T
A
R
T
CRX14 Write
R/W
Device Select
Code
Slot Marker
Register
Address
1 0 1 0 X X X
03h
S
T
O
P
Bus Slave
ACK
ACK
ai09246
Figure 18. CRX14-to-Host Transfer: I²C Random Address Read from Slot Marker Register
Bus Master
CRX14 Read
S
T
A
R
T
R
E
S
T
A
R
T
R/W
Device Select
Code
Slot Marker
Register
Address
1 0 1 0 X X X
00h
R/W
NoACK
Device Select
Code
S
T
O
P
FFh
1 0 1 0 X X X
Bus Slave
ACK
ACK
ACK
ai09247
Figure 19. CRX14-to-Host Transfer: I²C Current Address Read from Slot Marker Register
Bus Master
CRX14 Read
S
T
A
R
T
R/W
NoACK
Device Select
Code
S
T
O
P
FFh
1 0 1 0 X X X
Bus Slave
ACK
ai09248
19/40
CRX14
Addresses above Location 06h
In I²C Write mode, when the CRX14 receives the
8-bit register address, and the address is above location 06h, the device does not acknowledge
(NoACK) and deselects itself from the bus. The
Serial Data line, SDA, stays at logic ‘1’ (pull-up resistor), and the I²C Host receives a NoACK during
20/40
the 9th bit time. The SDA line stays High until the
STOP condition is issued.
In the I²C Current and Random Address Read
modes, when the CRX14 receives the 8-bit register address, and the address is above location
06h, the device does not acknowledge the Device
Select Code after the START condition, and deselects itself from the bus.
CRX14
CRX14 ISO14443 TYPE-B RADIO FREQUENCY DATA TRANSFER
Output RF Data Transfer from the CRX14 to the
PICC (Request Frame)
The CRX14 output buffer is controlled by the
13.56MHz clock signal generated by the external
oscillator and by the request frame generator. The
CRX14 can be directly connected to an external
matching circuit to generate a 13.56MHz sinusoidal carrier frequency on its antenna.
The current driven into the antenna coil is directly
generated by the CRX14 RFOUT output driver.
If the antenna is correctly tuned, it emits an H-field
of a large enough magnitude to power a contactless PICC from a short distance. The energy received on the PICC antenna is converted to a
Power Supply Voltage by a regulator, and turned
into data bits by the ASK demodulator. The
CRX14 amplitude modulates the 13.56MHz wave
by 10% as represented in Figure 20. The data
transfer rate is 106 kbit/s.
Figure 20. Wave Transmitted using ASK Modulation
DATA BIT TRANSMITTED
BY THE CRX14
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE RFOUT
DRIVER
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED ON THE CRX14
ANTENNA
Transfer time for one data bit is 1/106 kHz
AI10912
Transmission Format of Request Frame
Characters
The CRX14 transmits characters of 10 bits, with
the Least Significant Bit (b0) transmitted first, as
shown in Figure 21.
Several 10-bit characters, preceded by the Start
Of Frame (SOF) and followed by the End Of
Frame (EOF), constitute a Request Frame, as
shown in Figure 27.
A Request Frame includes the SOF, instructions,
addresses, data, CRC and the EOF as defined in
the ISO14443 type-B.
Each bit duration is called an Elementary Time
Unit (ETU). One ETU is equal to 9.44µs (1/
106kHz).
Figure 21. CRX14 Request Frame Character Format
b0
b1
1
Start LSB
ETU
'0'
b2
b3
b4
b5
Information Byte
b6
b7
b8
b9
MSB Stop
'1'
ai09250
21/40
CRX14
Table 7. CRX14 Request Frame Character Format
Bit
Description
Value
b0
Start bit used to synchronize the transmission
b0 = 0
b1 to b8
Information Byte (instruction, address or data)
Information Byte is sent Least Significant Bit
first
b9
Stop bit used to indicate the end of the character
b9 = 1
Request Start Of Frame
The Start Of Frame (SOF) described in Figure 22.
consists of:
– a falling edge,
– followed by ten Elementary Time Units (ETU)
each containing a logical ‘0’
– followed by a single rising edge
– followed by two ETUs, each containing a
logical ‘1’.
Figure 22. Request Start Of Frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
0
0
0
0
0
0
0
0
0
0
1
1
ai09251
Request End Of Frame
The End Of Frame (EOF) shown in Figure 23. consists of:
– a falling edge,
– followed by ten Elementary Time Units (ETU)
containing each a logical ‘0’,
– followed by a single rising edge.
Figure 23. Request End Of Frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
0
0
0
0
0
0
0
0
0
0
ai09252
22/40
CRX14
Input RF Data Transfer from the PICC to the
CRX14 (Answer Frame)
The CRX14 uses the ISO14443 type-B retro-modulation scheme which is demodulated and decoded by the RFIN circuitry.
The modulation is obtained by modifying the PICC
current consumption (load modulation). This load
modulation induces an H-field variation, by coupling, that is detected by the CRX14 RFIN input as
a voltage variation on the antenna. The RFIN input
demodulates this variation and decodes the information received from the PICC.
Data must be transmitted using a 847kHz, BPSK
modulated sub-carrier frequency, fS, as shown in
Figure 24., and as specified in ISO14443 type-B.
In BPSK, all data state transitions (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) are encoded by phase shift keying
the sub-carrier.
Figure 24. Wave Received using BPSK Sub-carrier Modulation
1/106kHz
PICC data bit to be transmitted
to the CRX14.
847kHz BPSK, resulting signal
generated by the PICC for the
load modulation.
1/847kHz
phase shift
VRFIN
VRET
VDYN
Load modulation effect on
the H-Field received on the
CRX14 RFIN input pad
VOFFSET
t
ai09253
Transmission Format of Answer Frame
Characters
The PICC should use the same character format
as that used for output data transfer (see Figure
21.).
An Answer Frame includes the SOF, data, CRC
and the EOF, as illustrated in Figure 27.. The data
transfer rate is 106 kbit/s.
The CRX14 will also accept Answer Frames that
do not contain the SOF and EOF delimiters, provided that these Frames are correctly set in the
Parameter Register. (See Figure 27.).
23/40
CRX14
Answer Start Of Frame
The PICC SOF must be compliant with the
ISO14443 type-B, and is shown in Figure 25.
– Ten or eleven Elementary Time Units (ETU)
each containing a logical ‘0’,
– Two ETUs containing a logical ‘1’.
Figure 25. Answer Start Of Frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
0
0
0
0
0
0
0
0
0
0
1
1
1
ai09254
Answer End Of Frame
The PICC EOF must be compliant with the
ISO14443 type-B, and is shown in Figure 26.
– Ten or eleven Elementary Time Units (ETU)
each containing a logical ‘0’,
– Two ETUs containing a logical ‘1’
Figure 26. Answer End Of Frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
0
0
0
0
0
0
0
0
0
0
1
1
1
ai09254
24/40
CRX14
Transmission Frame
The Request Frame transmission must be followed by a minimum delay, t0 (see Table 13.), in
which no ASK or BPSK modulation occurs, before
the Answer Frame can be transmitted. t0 is the
minimum time required by the CRX14 to switch
from transmission mode to reception mode, and
should be inserted after each frame. After t0, the
13.56MHz carrier frequency is modulated by the
PICC at 847kHz for a minimum time of t1 (see Table 13.) to allow the CRX14 to synchronize. After
t1, the first phase transition generated by the PICC
represents the start bit (‘0’) of the Answer SOF (or
the start bit ‘0’ of the first data character in non
SOF/EOF mode).
Figure 27. Example of a Complete Transmission Frame
Sent by
the CRX14
SOF
12 bits
at 106Kb/s
Cmd
Data
CRC
CRC
EOF
10 bits
10 bits
10 bits
10 bits
10 bits
tDR
fs = 847.5kHz
Sync
Case of Answer Frame with SOF & EOF
Sent by the PICC
t0
64/fs Min
t1
80/fs Min
SOF
12 or 13
bits
Data
CRC
CRC
10 bits
10 bits
10 bits
EOF
12 or 13
bits
tWDG
Sync
Case of Answer Frame without SOF & EOF
t0
64/fs Min
t1
80/fs Min
Data
Data
Data
CRC
CRC
10 bits
10 bits
10 bits
10 bits
10 bits
tWDG
Output Data Transfer using ASK Modulation
Input Data Transfer using 847kHz BPSK Modulation
ai09255
CRC
The 16-bit CRC used by the CRX14 follows the
ISO14443 type B recommendation. For further information, please see APPENDIX A., page 38.
The two CRC Bytes are present in all Request and
Answer Frames, just before the EOF. The CRC is
calculated on all the Bytes between the SOF and
the CRC Bytes.
Upon transmission of a Request from the CRX14,
the PICC verifies that the CRC value is valid. If it is
invalid, it discards the frame and does not answer
the CRX14.
Upon reception of an Answer from the PICC, the
CRX14 verifies that the CRC value is valid. If it is
invalid, it stores the value FFh in the Input/Output
Frame Register.
The CRC is transmitted Least Significant Byte first.
Each Byte is transmitted Least Significant Bit first.
Figure 28. CRC Transmission Rules
LSByte
LSBit
MSByte
MSBit LSBit
CRC 16 (8 bits)
MSBit
CRC 16 (8 bits)
ai09256
25/40
CRX14
TAG ACCESS USING THE CRX14 COUPLER
In all the following I²C commands, the last three
bits of the Device Select Code can be replaced by
any of the three-bit binary values (000, 001, 010,
011, 100, 101, 110, 111). These values are linked
to the logic levels applied to the E2, E1 and E0
pads of the CRX14.
ure 14., page 18. After the I²C STOP condition, the
CRX14 inserts the I²C Bytes in the required ISO
character format ( Figure 21.) and starts to transmit the request frame to the PICC. Once the RF
transmission is over, the CRX14 waits for the
PICC to send an answer frame.
If the PICC answers, the characters received ( Figure 27.) are demodulated, decoded and stored
into the Input/Output Frame Register, as specified
in Table 4. During the entire RF transmission, the
CRX14 disconnects itself from the I²C bus. On reception of the PICC EOF, the CRX14 checks the
CRC and reconnects itself to the I²C bus.
The host can then get the PICC answer frame by
issuing an Input/Output Frame Register Read on
the I²C bus, as specified in Figures 15 and 16.
If no answer from the PICC is detected after a
time-out delay, fixed in the Parameter Register
(bits b5 and b6), the Input/Output Frame Register
is set as specified in Table 4.
Standard TAG Command Access Description
Standard PICC commands, like Read and Write,
are generated by the CRX14 using the Input/Output Frame Register.
When the host needs to send a standard frame
command to the PICC, it first has to internally generate the complete frame, with the command code
followed by the command parameters. Only the
two CRC Bytes should not be generated, as the
CRX14 automatically adds them during the RF
transmission.
When the frame is ready, the host has to write the
request frame into the Input/Output Frame Register using the I²C write command specified in Fig-
Figure 29. Standard TAG Command: Request Frame Transmission
S
T
A Device
R Select
T Code
I²C
Input/
Output
Register
Address
Request
Frame
Length
TAG
Cmd
Code
01h
N
Data 1
Param
Data 2
Param
Data
Param
S
T
O
P
CRX14
SOF
TAG
Cmd
Code
Param
Param
Param
CRC
CRC
SRX14
EOF
Data 2
Data
Data N
CRC
CRC
EOF
Data N
RF
SOF
Data 1
ai09260
Figure 30. Standard TAG Command: Answer Frame Reception
TAG
SOF
TAG
Data
TAG
Data
TAG
Data
TAG
Data
TAG
CRC
TAG
CRC
TAG
EOF
I²C
RF
SOF
Data 1
Data 2
Data
Data P
CRC
CRC
S
T
A Device
R Select
T Code
Input/
Output
Register
Address
Answer
Frame
Length
TAG
Data
01h
P
Data 1
TAG
Data
Data 2
TAG
Data
Data
TAG
Data
S
T
O
P
Data P
EOF
ai09261
26/40
CRX14
Figure 31. Standard TAG Command: Complete TAG Access Description
I²C
Device
I/O
Request Request
Select
Code Register Frame Frame
Write Address Length Bytes
START
Device Answer Request
Select Frame Frame
Code Length Bytes
Read
STOP
START
STOP
SOF
RF
EOF
SOF
EOF
Request
TAG
Frame
CRC T0 T1 Answer Frame CRC
<--> <-->
Characters
Characters
ai09262
Anti-Collision TAG Sequence
The CRX14 can identify an ST short range memory using a proprietary anti-collision system.
Issuing an I²C Write command to the Slot Marker
Register ( Figure 17.) causes the CRX14 TO automatically generate a 16-slot anti-collision sequence, and to store the identified Chip_ID in the
Input/Output Frame Register, as specified in Table
5.
After receiving the Slot Marker Register I²C Write
command, the CRX14 generates an RF PCALL16
command followed by fifteen SLOT_MARKER
commands,
from
SLOT_MARKER(1)
to
SLOT_MARKER(15). After each command, the
CRX14 waits for a tag answer. If the answer is correctly decoded, the corresponding Chip_ID is
stored in the Input/Output Frame Register. If there
is no answer, or if the answer is wrong (with a CRC
error, for example), the CRX14 stores an error
code in the Input/Output Frame Register. At the
end of the sequence, the host has to read the Input/Output Frame Register to retrieve all the identified Chip_IDs.
27/40
CRX14
Figure 32. Anti-Collision ST short range memory Sequence (1)
S
Slot S
T Device Marker
T CRX14
A Select Register
SOF
R Code Address O
P
T
I²C
RF
PCALL 16 TAG
Command
CRC
CRC
CRX14
EOF
CRC
CRC
EOF
Slot Marker CRC
Command
CRC
CRX14
EOF
TAG
SOF
TAG
Chip_ID
TAG
CRC
TAG
CRC
TAG
EOF
SOF
Chip_ID
CRC
CRC
EOF
TAG
SOF
TAG
Chip_ID
TAG
CRC
TAG
CRC
TAG
EOF
03h
Slot 0
SOF
06h
CRX14
SOF
04h
t0 t1
<--> <-->
I²C
RF...
Slot 1
SOF
16h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 2
SOF
26h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 3
SOF
36h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 4
SOF
46h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 5
SOF
56h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 6
SOF
66h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 7
SOF
76h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 8
SOF
86h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 9
SOF
96h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
ai09263
28/40
CRX14
Figure 33. Anti-Collision ST short range memory Sequence Continued
I²C
RF ...
Slot 10
SOF
96h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 11
SOF
56h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 12
SOF
66h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 13
SOF
76h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 14
SOF
86h
CRC
CRC
EOF
t0 t1
<--> <-->
SOF
Chip_ID
CRC
CRC
EOF
Slot 15
SOF
96h
CRC
CRC
EOF
SOF
Chip_ID
CRC
CRC
EOF
I²C
RF ...
I²C
RF ...
I²C
RF ...
I²C
RF ...
I²C
RF ...
S
T Device
A Select
R Code
T
I²C ...
RF
t0
t1
<--> <-->
R
E
S
T Device Answer Status
Status
Slot 1
I/O
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 0
Register A Select Frame Slot Bits Slot Bits Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
Address R Code Length b0 to b7 b8 to b15 Answer Answer Answer Answer Answer Answer Answer Answer Answer
T
01h
12h
Status
Status Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
S
Slot 9
Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 T
Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID O
Answer Answer Answer Answer Answer Answer Answer P
I²C ... Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
RF
ai09264
29/40
CRX14
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
–65 to 150
°C
215(2)
°C
–0.3 to 6.5
V
–0.3 to Vcc+0.3
V
–0.3 to 6.5
V
Output Power on Antenna Output Driver (RFOUT)
100
mW
Electrostatic Discharge Voltage (Human Body model) (3)
4000
V
Electrostatic Discharge Voltage (Machine model) (4)
500
V
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering(1)
VIO
Input or Output range (SDA)
VIO
Input or Output range (others pads)
VCC
Supply Voltage
POUT
VESD
Note: 1. Compliant with the JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. No longer than 40 seconds.
3. MIL-STD-883C, 3015.7 (100pF, 1500Ω).
4. EIAJ IC-121 (Condition C) (200pF, 0Ω)
30/40
CRX14
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 9. I²C AC Measurement Conditions
Parameter
Min.
Max.
Unit
VCC Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (TA)
−20
85
°C
50
ns
Input Rise and Fall Times
Input Pulse Voltages
0.2VCC
0.8VCC
V
Input and Output Timing Reference Voltages
0.3VCC
0.7VCC
V
Figure 34. I²C AC Testing I/O Waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI09235
Table 10. I²C Input Parameters(1,2)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (SCL, E0, E1, E2))
6
pF
tNS
Low Pass Filter Input Time Constant (SCL & SDA Inputs)
400
ns
100
Note: 1. Sampled only, not 100% tested.
2. TA = 25 °C, f = 400kHz.
31/40
CRX14
Table 11. I²C DC Characteristics
Symbol
Parameter
Test Condition
ILI
Input Leakage Current (SCL,
SDA, E0, E1, E2)
ILO
Output Leakage Current (SCL,
SDA, E0, E1, E2)
ICC
ICC1
Max.
Unit
0V ≤VIN ≤VCC
±2
µA
0V ≤VOUT ≤VCC, SDA in Hi-Z
±2
µA
VCC = 5V, fc = 400kHz (rise/fall time < 30ns),
RF OFF
6
mA
VCC = 5V, fc = 400kHz (rise/fall time < 30ns),
RF ON
20
mA
VIN = VSS or VCC, VCC = 5V, RF OFF
5
mA
Supply Current
Supply Current (Stand-by)
Input Low Voltage (SCL, SDA)
−0.3
0.3VCC
V
Input Low Voltage (E0, E1, E2)
−0.3
0.3VCC
V
Input High Voltage (SCL, SDA)
0.7VCC
VCC + 1
V
Input High Voltage (E0, E1, E2)
0.7VCC
VCC + 1
V
0.4
V
VIL
VIH
VOL
Min.
IOL = 3mA, VCC = 5V
Output Low Voltage (SDA)
Figure 35. I²C AC Waveforms
tCHCL
CLCH
SCL
tDXCX
tDLCL
tCHDH
SDA IN
tCHDX
START
CONDITION
tCLDX
SDA
INPUT
tDHDL
STOP &
BUS FREE
SDA
CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tRFEX
SDA IN
tCHDH
STOP
CONDITION
tCHDX
CRX14 command execution
START
CONDITION
ai09236
32/40
CRX14
Table 12. I²C AC Characteristics
Symbol
Alt.
Parameter
Fast I²C
400 kHz
Min
Max
I²C
100 kHz
Min
Unit
Max
tCH1CH2 2
tR
Clock Rise Time
300
1000
ns
tCL1CL2 2
tF
Clock Fall Time
300
300
ns
tDH1DH2 2
tR
SDA Rise Time
20
300
20
1000
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
20
300
ns
tCHDX 1
tSU:STA
Clock High to Input Transition
600
4700
ns
tCHCL
tHIGH
Clock Pulse Width High
600
4000
ns
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
4000
ns
tCLDX
tHD:DAT
Clock Low to Input Transition
0
0
µs
tCLCH
tLOW
Clock Pulse Width Low
1.3
4.7
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
250
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
600
4000
ns
tDHDL
tBUF
Input High to Input Low (Bus Free)
1.3
4.7
µs
tCLQV
tAA
Clock Low to Data Out Valid
tCLQX
tDH
Data Out Hold Time After Clock Low
fC
fSCL
Clock Frequency
1000
200
3500
200
400
ns
ns
100
kHz
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested
33/40
CRX14
Figure 36. CRX14 Synchronous Timing
RFOUT ASK Modulated Signal
VRFOUT
tRFSBL
tRFF
A
tRFR
B
fCC
tPOR
FRAME transmission between the reader and the contactless device
tDR
1
tDR
0
DATA 1
EOF
FRAME transmitted by the CRX14 in ASK
847kHz
FRAME transmitted by the PICC in BPSK
t0
SOF
t1
1 1 0 DATA
tDA
1 0 DATA
1 0
tDA
Data jitter on FRAME transmitted by the CRX14 in ASK
tJIT
tJIT
tJIT
tJIT
tJIT
0
START
tRFSBL
tRFSBL
tRFSBL
tRFSBL
tRFSBL
ai09258
34/40
CRX14
Table 13. RFOUT AC Characteristics
Symbol
Parameter
Condition
Min.
Max.
Unit
fCC
External Oscillator Frequency
VCC = 5V
13.553
13.567
MHz
MICARRIER
Carrier Modulation Index
MI=(A-B)/(A+B)
10
14
%
tRFR, tRFF
10% Rise and Fall time
0.5
1.5
µs
tRFSBL
Pulse Width on RFOUT
1 ETU = 128/fCC
9.44
tJIT
ASK modulation bit jitter
CRX14 to PICC
-0.5
t0
Antenna Reversal delay
Min = 64/fS
75
µs
t1
Synchronization delay
Min = 80/fS
94
µs
tWDG
Answer delay watchdog (b5=0, b6=0)
tWDG
Answer delay watchdog (b5=0, b6=1)
tWDG
Answer delay watchdog (b5=1, b6=0)
tWDG
Answer delay watchdog (b5=1, b6=1)
tDR
Time Between Request characters
PA
RFOUT output power
90
mW
tPOR
CRX14 Power-On delay
20
ms
µs
0.5
Request EOF
rising edge
to
first Answer
start bit
CRX14 to PICC
µs
500
µs
5
ms
10
ms
309
ms
9.44
µs
Note: 1. Note:Data specified in the table above are estimated or target values. All values can be updated during product qualification.
Table 14. RFIN AC Characteristics
Symbol
tRFSBL
Parameter
PICC Pulse Width
fS
PICC Sub-carrier Frequency
tDA
Time Between Answer characters
VDYN
VOFFSET
VRET
RFIN Dynamic Voltage Level
RFIN Offset Voltage Level
RFIN Retro-modulation Level
Condition
Min.
Max.
Unit
1 ETU = 128/fCC
9.44
µs
fCC/16
847.5
KHz
PICC to CRX14
1, 2, 3
ETU
VDYN Max for VOFFSET = VCC/2
0.5
VCC/2
V
2
3
V
120
mV
Note: 1. Note:Data specified in the table above are estimated or target values. All values can be updated during product qualification.
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CRX14
PACKAGE MECHANICAL
Figure 37. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data
millimeters
inches
Symbol
Typ.
Min.
A
Typ.
Min.
1.75
A1
0.10
A2
Max.
0.069
0.25
0.004
1.60
0.010
0.063
α
0°
8°
0°
8°
B
0.35
0.46
0.014
0.018
C
0.19
0.25
0.007
0.010
CP
0.10
D
9.80
10.00
–
–
E
3.80
L
0.40
N
16
e
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Max.
1.27
0.004
0.386
0.394
–
–
4.00
0.150
0.157
1.27
0.016
0.050
0.050
16
CRX14
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
CRX14
–
MQ
/ XXX
Device Type
CRX14
Package
MQ = SO16 Narrow (150 mils width)
MQP = SO16 Narrow (150 mils width) Lead-Free and RoHS compliant
Customer Code
XXX = Given by the issuer
For a list of available options (speed, package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
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CRX14
APPENDIX A. ISO14443 TYPE B CRC CALCULATION
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#define BYTE
unsigned char
#define USHORT unsigned short
unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc)
{
ch = (ch^(BYTE)((*lpwCrc) & 0x00FF));
ch = (ch^(ch<<4));
*lpwCrc = (*lpwCrc >> 8)^((USHORT)ch << 8)^((USHORT)ch<<3)^((USHORT)ch>>4);
return(*lpwCrc);
}
void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE
*TransmitSecond)
{
BYTE chBlock; USHORTt wCrc;
wCrc = 0xFFFF; // ISO 3309
do
{
chBlock = *Data++;
UpdateCrc(chBlock, &wCrc);
} while (--Length);
wCrc = ~wCrc; // ISO 3309
*TransmitFirst = (BYTE) (wCrc & 0xFF);
*TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF);
return;
}
int main(void)
{
BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i;
printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1");
printf("CRC_B of [ ");
for(i=0; i<4; i++)
printf("%02X ",BuffCRC_B[i]);
ComputeCrc(BuffCRC_B, 4, &First, &Second);
printf("] Transmitted: %02X then %02X.", First, Second);
return(0);
}
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CRX14
REVISION HISTORY
Table 17. Document Revision History
Date
Version
Revision Details
4-Aug-2004
1.0
First issue
23-Feb-2005
2.0
Document put into new template.
21-Jul-2005
3.0
Added Package information in Table 16., Ordering Information Scheme.
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CRX14
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
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