STMICROELECTRONICS SRIX4K

SRIX4K
13.56 MHz short-range contactless memory chip
with 4096-bit EEPROM, anticollision and anti-clone functions
Features
■
ISO 14443-2 Type B air interface compliant
■
ISO 14443-3 Type B frame format compliant
■
13.56 MHz carrier frequency
■
847 kHz subcarrier frequency
■
106 Kbit/second data transfer
■
France Telecom proprietary anti-clone function
■
8 bit Chip_ID based anticollision system
■
2 count-down binary counters with automated
antitearing protection
■
64-bit Unique Identifier
■
4096-bit EEPROM with Write Protect feature
■
READ BLOCK and WRITE BLOCK (32 bits)
■
Internal tuning capacitor
■
1million ERASE/WRITE cycles
■
40-year data retention
■
Self-timed programming cycle
■
5 ms typical programming time
■
Packages
– ECOPACK® (RoHS compliant)
Antenna (A3)
Antenna (A4)
Antenna (A5)
Wafer
April 2007
Rev 7
1/50
www.st.com
1
Contents
SRIX4K
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.1
3
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
4
AC1, AC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input data transfer from the Reader to the SRIX4K (request frame) . . . . . 9
3.1.1
Character transmission format for request frame . . . . . . . . . . . . . . . . . . 9
3.1.2
Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3
Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output data transfer from the SRIX4K to the Reader (answer frame) . . . 11
3.2.1
Character transmission format for answer frame . . . . . . . . . . . . . . . . . . 11
3.2.2
Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3
Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
Resettable OTP area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
32-bit binary counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
EEPROM area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.1
OTP_Lock_Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2
Fixed Chip_ID (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
SRIX4K operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
SRIX4K states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/50
6.1
POWER-OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
READY state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3
INVENTORY state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4
SELECTED state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
DESELECTED state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SRIX4K
Contents
6.6
7
DEACTIVATED state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1
Description of an anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Anti-clone function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
SRIX4K commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
INITIATE() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.2
PCALL16() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3
SLOT_MARKER(SN) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4
SELECT(Chip_ID) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5
COMPLETION() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.6
RESET_TO_INVENTORY() command . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.7
READ_BLOCK(Addr) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.8
WRITE_BLOCK (Addr, Data) command . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.9
GET_UID() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.10
Power-On state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Appendix A ISO 14443 Type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . 46
Appendix B SRIX4K command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3/50
List of tables
SRIX4K
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
4/50
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRIX4K memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standard anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Command code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
A3 antenna specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
A4 antenna specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A5 antenna specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SRIX4K
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Die floor plan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
10% ASK modulation of the received wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRIX4K request frame character format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wave transmitted using BPSK subcarrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Answer end of frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Resettable OTP area (addresses 0 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WRITE_BLOCK update in Standard mode (binary format) . . . . . . . . . . . . . . . . . . . . . . . . 15
WRITE_BLOCK update in Reload mode (Binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Binary counter (addresses 5 to 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Count down example (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
EEPROM (addresses 7 to 127) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
State transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SRIX4K Chip_ID description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Example of an anticollision sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INITIATE request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
INITIATE response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
INITIATE Frame Exchange Between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . 29
PCALL16 request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCALL16 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCALL16 frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . 30
SLOT_MARKER request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SLOT_MARKER response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SLOT_MARKER frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . 31
SELECT request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SELECT Response Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SELECT frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . 32
COMPLETION request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
COMPLETION response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
COMPLETION frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . 33
RESET_TO_INVENTORY request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RESET_TO_INVENTORY response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RESET_TO_INVENTORY frame exchange between Reader and SRIX4K . . . . . . . . . . . . 34
READ_BLOCK request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
READ_BLOCK response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
READ_BLOCK frame exchange between Reader and SRIX4K. . . . . . . . . . . . . . . . . . . . . 35
WRITE_BLOCK request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WRITE_BLOCK response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WRITE_BLOCK frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . 37
GET_UID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
GET_UID response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5/50
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
6/50
SRIX4K
64-bit unique identifier of the SRIX4K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GET_UID frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . 38
SRIX4K synchronous timing, transmit and receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
A3 antenna specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
A4 antenna specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A5 antenna specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
INITIATE frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . 47
PCALL16 frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . 47
SLOT_MARKER frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . 47
SELECT frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . . 47
COMPLETION frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . 47
RESET_TO_INVENTORY frame exchange between Reader and SRIX4K . . . . . . . . . . . . 48
READ_BLOCK frame exchange between Reader and SRIX4K. . . . . . . . . . . . . . . . . . . . . 48
WRITE_BLOCK frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . 48
GET_UID frame exchange between Reader and SRIX4K . . . . . . . . . . . . . . . . . . . . . . . . . 48
SRIX4K
1
Description
Description
The SRIX4K is a contactless memory, powered by an externally transmitted radio wave. It
contains a 4096-bit user EEPROM fabricated with STMicroelectronics CMOS technology.
The memory is organized as 128 blocks of 32 bits. The SRIX4K is accessed via the
13.56 MHz carrier. Incoming data are demodulated and decoded from the received
Amplitude Shift Keying (ASK) modulation signal and outgoing data are generated by load
variation using Bit Phase Shift Keying (BPSK) coding of a 847 kHz subcarrier. The received
ASK wave is 10% modulated. The Data transfer rate between the SRIX4K and the reader is
106 Kbit/s in both reception and emission modes.
The SRIX4K follows the ISO 14443-2 Type B recommendation for the radio-frequency
power and signal interface.
Figure 1.
Logic diagram
SRIX4K
Power
Supply
Regulator
4 Kbit
User
EEPROM
AC1
ASK
Demodulator
BPSK
Load
Modulator
AC0
AI06829
The SRIX4K is specifically designed for short range applications that need secure and reusable products. The SRIX4K includes an anticollision mechanism that allows it to detect
and select tags present at the same time within range of the reader. The anticollision is
based on a probabilistic scanning method using slot markers. The SRIX4K provides an anticlone function which allows its authentication. Using the STMicroelectronics single chip
coupler, CRX14, it is easy to design a reader with the authentication capability and to build a
system with a high level of security.
Table 1.
Signal names
AC1
Antenna coil
AC0
Antenna coil
7/50
Signal description
SRIX4K
The SRIX4K contactless EEPROM can be randomly read and written in block mode (each
block containing 32 bits). The instruction set includes the following ten commands:
●
READ_BLOCK
●
WRITE_BLOCK
●
INITIATE
●
PCALL16
●
SLOT_MARKER
●
SELECT
●
COMPLETION
●
RESET_TO_INVENTORY
●
AUTHENTICATE
●
GET_UID
The SRIX4K memory is organized in three areas, as described in Figure 3. The first area is
a resettable OTP (one time programmable) area in which bits can only be switched from 1 to
0. Using a special command, it is possible to erase all bits of this area to 1. The second area
provides two 32-bit binary counters which can only be decremented from FFFF FFFFh to
0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the
EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle
during each WRITE_BLOCK command.
Figure 2.
Die floor plan
AC0
AC1
AI09055
2
Signal description
2.0.1
AC1, AC0
The pads for the Antenna Coil. AC1 and AC0 must be directly bonded to the antenna.
8/50
SRIX4K
Data transfer
3
Data transfer
3.1
Input data transfer from the Reader to the SRIX4K (request
frame)
The reader must generate a 13.56 MHz sinusoidal carrier frequency at its antenna, with
enough energy to “remote-power” the memory. The energy received at the SRIX4K’s
antenna is transformed into a supply voltage by a regulator, and into data bits by the ASK
demodulator. For the SRIX4K to decode correctly the information it receives, the reader
must 10% amplitude-modulate the 13.56 MHz wave before sending it to the SRIX4K. This is
represented in Figure 3. The data transfer rate is 106 Kbits/s.
Figure 3.
10% ASK modulation of the received wave
DATA BIT TO TRANSMIT
TO THE SRIX4K
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE READER
Transfer time for one data bit is 1/106 kHz
AI05729
3.1.1
Character transmission format for request frame
The SRIX4K transmits and receives data bytes as 10-bit characters, with the least
significant bit (b0) transmitted first, as shown in Figure 4. Each bit duration, an ETU
(Elementary Time Unit), is equal to 9.44 µs (1/106 kHz).
These characters, framed by a Start Of Frame (SOF) and an End Of Frame (EOF), are put
together to form a Command Frame as shown in Figure 10. A frame includes an SOF,
commands, addresses, data, a CRC and an EOF as defined in the ISO 14443-3 Type B
Standard. If an error is detected during data transfer, the SRIX4K does not execute the
command, but it does not generate an error frame.
Figure 4.
SRIX4K request frame character format
b0
1 ETU
Start
"0"
b1
LSb
b2
b3
b4
b5
Information Byte
b6
b7
b8
b9
MSb
Stop
"1"
ai07664
9/50
Data transfer
SRIX4K
Table 2.
3.1.2
Bit description
Bit
Description
Value
b0
Start bit used to synchronize the transmission
b0 = 0
b1 to b8
Information Byte (command, address or data)
The information byte is sent with the
least significant bit first
b9
Stop bit used to indicate the end of a character
b9 = 1
Request start of frame
The SOF described in Figure 5 is composed of:
–
one falling edge,
–
followed by 10 ETUs at logic-0,
–
followed by a single rising edge,
–
followed by at least 2 ETUs (and at most 3) at logic-1.
Figure 5.
ETU
Request start of frame
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
0
0
0
0
0
0
0
0
0
0
1
1
ai07665
3.1.3
Request end of frame
The EOF shown in Figure 6 is composed of:
–
one falling edge,
–
followed by 10 ETUs at logic-0,
–
followed by a single rising edge.
Figure 6.
ETU
Request end of frame
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
0
0
0
0
0
0
0
0
0
0
ai07666
10/50
SRIX4K
3.2
Data transfer
Output data transfer from the SRIX4K to the Reader (answer
frame)
The data bits issued by the SRIX4K use retro-modulation. Retro-modulation is obtained by
modifying the SRIX4K current consumption at the antenna (load modulation). The load
modulation causes a variation at the reader antenna by inductive coupling. With appropriate
detector circuitry, the reader is able to pick up information from the SRIX4K. To improve
load-modulation detection, data is transmitted using a BPSK encoded, 847 kHz subcarrier
frequency ƒs as shown in Figure 7, and as specified in the ISO 14443-2 Type B Standard.
Figure 7.
Wave transmitted using BPSK subcarrier modulation
Data Bit to be Transmitted
to the Reader
Or
847kHz BPSK Modulation
Generated by the SRIX4K
BPSK Modulation at 847kHz
During a One-bit Data Transfer Time (1/106kHz)
3.2.1
AI05730
Character transmission format for answer frame
The character format is the same as for input data transfer (Figure 4). The transmitted
frames are made up of an SOF, data, a CRC and an EOF (Figure 10). As with an input data
transfer, if an error occurs, the reader does not issue an error code to the SRIX4K, but it
should be able to detect it and manage the situation. The data transfer rate is
106 Kbits/second.
3.2.2
Answer start of frame
The SOF described in Figure 8 is composed of:
–
followed by 10 ETUs at logic-0
–
followed by 2 ETUs at logic-1
Figure 8.
ETU
Answer start of frame
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
0
0
0
0
0
0
0
0
0
0
1
1
ai07665
11/50
Data transfer
3.2.3
SRIX4K
Answer end of frame
The EOF shown in Figure 9 is composed of:
–
followed by 10 ETUs at logic-0,
–
followed by 2 ETUs at logic-1.
Figure 9.
Answer end of frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
0
0
0
0
0
0
0
0
0
0
1
1
ai07665
3.3
Transmission frame
Between the Request data transfer and the Answer data transfer, all ASK and BPSK
modulations are suspended for a minimum time of t0 = 128/ƒS. This delay allows the reader
to switch from Transmission to Reception mode. It is repeated after each frame. After t0, the
13.56 MHz carrier frequency is modulated by the SRIX4K at 847 kHz for a period of
t1 = 128/ƒS to allow the reader to synchronize. After t1, the first phase transition generated
by the SRIX4K forms the start bit (‘0’) of the Answer SOF. After the falling edge of the
Answer EOF, the reader waits a minimum time, t2, before sending a new Request Frame to
the SRIX4K.
Figure 10. Example of a complete transmission frame
Sent by the
Reader
SOF
12 bits
Cmd
Data
CRC
CRC
EOF
10 bits
10 bits
10 bits
10 bits
10 bits
at 106kb/s
SOF
fs=847.5kHz
t DR
Sent by the
SRIX4K
SOF
Sync
t0
t1
128/fs
128/fs
12 bits
Data CRC CRC EOF
10 bits
10 bits
10 bits
12 bits
t2
Input data transfer using ASK
Output data transfer using BPSK
AI05731
12/50
SRIX4K
3.4
Data transfer
CRC
The 16-bit CRC used by the SRIX4K is generated in compliance with the ISO 14443 Type B
recommendation. For further information, please see Appendix A. The initial register
contents are all 1s: FFFFh.
The two-byte CRC is present in every Request and in every Answer Frame, before the EOF.
The CRC is calculated on all the bytes between SOF (not included) and the CRC field.
Upon reception of a Request from a reader, the SRIX4K verifies that the CRC value is valid.
If it is invalid, the SRIX4K discards the frame and does not answer the reader.
Upon reception of an Answer from the SRIX4K, the reader should verify the validity of the
CRC. In case of error, the actions to be taken are the reader designer’s responsibility.
The CRC is transmitted with the Least Significant Byte first and each byte is transmitted with
the least significant bit first.
Figure 11. CRC transmission rules
LSByte
LSbit
MSByte
MSbit
CRC 16 (8 bits)
LSbit
MSbit
CRC 16 (8 bits)
ai07667
13/50
Memory mapping
4
SRIX4K
Memory mapping
The SRIX4K is organized as 128 blocks of 32 bits as shown in Figure 3. All blocks are
accessible by the READ_BLOCK command. Depending on the write access, they can be
updated by the WRITE_BLOCK command. A WRITE_BLOCK updates all the 32 bits of the
block.
Table 3.
SRIX4K memory mapping
Msb32 bits BlockLsb
Block
Addr
b31b24 b23b16 b15b8 b7b0
0
32 bits Boolean Area
1
32 bits Boolean Area
2
32 bits Boolean Area
3
32 bits Boolean Area
4
32 bits Boolean Area
5
32 bits binary counter
6
32 bits binary counter
7
User Area
8
User Area
9
User Area
10
User Area
11
User Area
12
User Area
13
User Area
14
User Area
15
User Area
16
User Area
...
User Area
127
User Area
255
OTP_Lock_Reg
ST Reserved
Description
Resettable OTP
bits
Count down
Counter
Lockable
EEPROM
EEPROM
Fixed Chip_ID
(Option)
System OTP bits
UID0
64 bits UID Area
UID1
14/50
ROM
SRIX4K
4.1
Memory mapping
Resettable OTP area
In this area contains five individual 32-bit Boolean Words (see Figure 12 for a map of the
area). A WRITE_BLOCK command will not erase the previous contents of the block as the
Write cycle is not preceded by an Auto Erase cycle. This feature can be used to reset
selected bits from 1 to 0. All bits previously at 0 remain unchanged. When the 32 bits of a
block are all at 0, the block is empty, and cannot be updated any more. See Figure 13 and
Figure 14 for examples of the result of the WRITE_BLOCK command in the resettable OTP
area.
Figure 12. Resettable OTP area (addresses 0 to 4)
Block
Address
MSb
b31
32-bit Block
b16 b15
b24 b23
0
32-bit Boolean Area
1
32-bit Boolean Area
2
32-bit Boolean Area
3
32-bit Boolean Area
4
32-bit Boolean Area
LSb
b0
b8 b7
Description
Resettable
OTP Bit
ai07657
Figure 13. WRITE_BLOCK update in Standard mode (binary format)
b31
b0
Previous data stored in block
1
...
1
1
0
1
0
1
1
1
1
1
0
1
1
Data to be written
1
...
1
0
0
1
0
1
1
0
0
1
1
1
1
New data stored in block
1
...
1
0
0
1
0
1
1
0
0
1
0
1
1
ai07658
The five 32-bit blocks making up the Resettable OTP area can be erased in one go by
adding an Auto Erase cycle to the WRITE_BLOCK command. An Auto Erase cycle is added
each time the SRIX4K detects a Reload command. The Reload command is implemented
through a specific update of the 32-bit binary counter located at block address 6 (see
Section 4.2: 32-bit binary counters for details).
15/50
Memory mapping
SRIX4K
Figure 14. WRITE_BLOCK update in Reload mode (Binary format)
b31
b0
Previous data stored in block
1
...
1
1
0
1
0
1
1
1
1
1
0
1
1
Data to be written
1
...
1
1
1
1
0
1
1
0
0
1
1
1
1
New data stored in block
1
...
1
1
1
1
0
1
1
0
0
1
1
1
1
ai07659
4.2
32-bit binary counters
The two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to
count down from 232 (4096 million) to 0. The SRIX4K uses dedicated logic that only allows
the update of a counter if the new value is lower than the previous one. This feature allows
the application to count down by steps of 1 or more. The initial value in Counter 5 is
FFFF FFFEh and is FFFF FFFFh in Counter 6. When the value displayed is 0000 0000h,
the counter is empty and cannot be reloaded. The counter is updated by issuing the
WRITE_BLOCK command to block address 5 or 6, depending on which counter is to be
updated. The WRITE_BLOCK command writes the new 32-bit value to the counter block
address. Figure 16 shows examples of how the counters operate.
The counter programming cycles are protected by automated antitearing logic. This function
allows the counter value to be protected in case of power down within the programming
cycle. In case of power down, the counter value is not updated and the previous value
continues to be stored.
Figure 15. Binary counter (addresses 5 to 6)
Block
Address
5
6
MSb
b31
b24 b23
32-bit Block
b16 b15
32-bit Binary Counter
32-bit Binary Counter
b8 b7
LSb
b0
Description
Count down
Counter
ai07660
16/50
SRIX4K
Memory mapping
Figure 16. Count down example (binary format)
b31
b0
Initial data
1
...
1
1
1
1
1
1
1
1
1
1
1
1
1
1-unit decrement
1
...
1
1
1
1
1
1
1
1
1
1
1
1
0
1-unit decrement
1
...
1
1
1
1
1
1
1
1
1
1
1
0
1
1-unit decrement
1
...
1
1
1
1
1
1
1
1
1
1
1
0
0
8-unit decrement
1
...
1
1
1
1
1
1
1
1
1
0
1
0
0
Increment not allowed
1
...
1
1
1
1
1
1
1
1
1
1
0
0
0
ai07661
The counter with block address 6 controls the Reload command used to reset the resettable
OTP area (addresses 0 to 4). Bits b31 to b21 act as an 11-bit Reload counter; whenever one
of these 11 bits is updated, the SRIX4K detects the change and adds an Erase cycle to the
WRITE_BLOCK command for locations 0 to 4 (see Section 4.1: Resettable OTP area). The
Erase cycle remains active until a POWER-OFF or a SELECT command is issued. The
SRIX4K’s resettable OTP area can be reloaded up to 2,047 times (211-1).
4.3
EEPROM area
The 121 blocks between addresses 7 and 127 are EEPROM blocks of 32 bits each (484
Bytes in total). (See Figure 17 for a map of the area.) These blocks can be accessed using
the READ_BLOCK and WRITE_BLOCK commands. The WRITE_BLOCK command for the
EEPROM area always includes an Auto-Erase cycle prior to the Write cycle.
Blocks 7 to 15 can be Write-protected. Write access is controlled by the 8 bits of the
OTP_Lock_Reg located at block address 255 (see Section 4.4.1: OTP_Lock_Reg for
details). Once protected, these blocks (7 to 15) cannot be unprotected.
17/50
Memory mapping
SRIX4K
Figure 17. EEPROM (addresses 7 to 127)
Block
Address
MSb
b31
b24 b23
32-bit Block
b16 b15
7
User Area
8
User Area
9
User Area
10
User Area
11
User Area
12
User Area
13
User Area
14
User Area
15
User Area
16
User Area
...
User Area
127
User Area
b8 b7
LSb
b0
Description
Lockable
EEPROM
EEPROM
Ai07661B
4.4
System area
This area is used to modify the settings of the SRIX4K. It contains 3 registers:
OTP_Lock_Reg, Fixed Chip_ID and ST Reserved. See Figure 18 for a map of this area.
A WRITE_BLOCK command in this area will not erase the previous contents. Selected bits
can thus be set from 1 to 0. All bits previously at 0 remain unchanged. Once all the 32 bits of
a block are at 0, the block is empty and cannot be updated any more.
Figure 18. System area
Block
Address
255
MSb
b31
32-bit Block
b24 b23
OTP_Lock_Reg
b16 b15
ST Reserved
LSb
b8 b7
b0
Fixed Chip_ID
(Option)
Description
OTP
ai07663
18/50
SRIX4K
4.4.1
Memory mapping
OTP_Lock_Reg
The 8 bits, b31 to b24, of the System Area (block address 255) are used as OTP_Lock_Reg
bits in the SRIX4K. They control the Write access to the 9 EEPROM blocks with addresses
7 to 15 as follows:
–
When b24 is at 0, blocks 7 and 8 are Write-protected
–
When b25 is at 0, block 9 is Write-protected
–
When b26 is at 0, block 10 is Write-protected
–
When b27 is at 0, block 11 is Write-protected
–
When b28 is at 0, block 12 is Write-protected
–
When b29 is at 0, block 13 is Write-protected
–
When b30 is at 0, block 14 is Write-protected
–
When b31 is at 0, block 15 is Write-protected.
The OTP_Lock_Reg bits cannot be erased. Once Write-protected, EEPROM blocks behave
like ROM blocks and cannot be unprotected.
4.4.2
Fixed Chip_ID (Option)
The SRIX4K is provided with an anticollision feature based on a random 8-bit Chip_ID. Prior
to selecting an SRIX4K, an anticollision sequence has to be run to search for the Chip_ID of
the SRIX4K. This is a very flexible feature, however the searching loop requires time to run.
For some applications, much time could be saved by knowing the value of the SRIX4K
Chip_ID beforehand, so that the SRIX4K can be identified and selected directly without
having to run an anticollision sequence. This is why the SRIX4K was designed with an
optional mask setting used to program a fixed 8-bit Chip_ID to bits b7 to b0 of the system
area. When the fixed Chip_ID option is used, the random Chip_ID function is disabled.
19/50
SRIX4K operation
5
SRIX4K
SRIX4K operation
All commands, data and CRC are transmitted to the SRIX4K as 10-bit characters using ASK
modulation. The start bit of the 10 bits, b0, is sent first. The command frame received by the
SRIX4K at the antenna is demodulated by the 10% ASK demodulator, and decoded by the
internal logic. Prior to any operation, the SRIX4K must have been selected by a SELECT
command. Each frame transmitted to the SRIX4K must start with a Start Of Frame, followed
by one or more data characters, two CRC Bytes and the final End Of Frame. When an
invalid frame is decoded by the SRIX4K (wrong command or CRC error), the memory does
not return any error code.
When a valid frame is received, the SRIX4K may have to return data to the reader. In this
case, data is returned using BPSK encoding, in the form of 10-bit characters framed by an
SOF and an EOF. The transfer is ended by the SRIX4K sending the 2 CRC Bytes and the
EOF.
20/50
SRIX4K
6
SRIX4K states
SRIX4K states
The SRIX4K can be switched into different states. Depending on the current state of the
SRIX4K, its logic will only answer to specific commands. These states are mainly used
during the anticollision sequence, to identify and to access the SRIX4K in a very short time.
The SRIX4K provides 6 different states, as described in the following paragraphs and in
Figure 19.
6.1
POWER-OFF state
The SRIX4K is in POWER-OFF state when the electromagnetic field around the tag is not
strong enough. In this state, the SRIX4K does not respond to any command.
6.2
READY state
When the electromagnetic field is strong enough, the SRIX4K enters the READY state. After
Power-up, the Chip_ID is initialized with a random value. The whole logic is reset and
remains in this state until an INITIATE() command is issued. Any other command will be
ignored by the SRIX4K.
6.3
INVENTORY state
The SRIX4K switches from the READY to the INVENTORY state after an INITIATE()
command has been issued. In INVENTORY state, the SRIX4K will respond to any
anticollision commands: INITIATE(), PCALL16() and SLOT_MARKER(), and then remain in
the INVENTORY state. It will switch to the SELECTED state after a SELECT(Chip_ID)
command is issued, if the Chip_ID in the command matches its own. If not, it will remain in
INVENTORY state.
6.4
SELECTED state
In SELECTED state, the SRIX4K is active and responds to all READ_BLOCK(),
WRITE_BLOCK(), AUTHENTICATE() and GET_UID() commands. When an SRIX4K has
entered the SELECTED state, it no longer responds to anticollision commands. So that the
reader can access another tag, the SRIX4K can be switched to the DESELECTED state by
sending a SELECT(Chip_ID2) with a Chip_ID that does not match its own, or it can be
placed in DEACTIVATED state by issuing a COMPLETION() command. Only one SRIX4K
can be in SELECTED state at a time.
6.5
DESELECTED state
Once the SRIX4K is in DESELECTED state, only a SELECT(Chip_ID) command with a
Chip_ID matching its own can switch it back to SELECTED state. All other commands are
ignored.
21/50
SRIX4K states
6.6
SRIX4K
DEACTIVATED state
When in this state, the SRIX4K can only be turned off. All commands are ignored.
Figure 19. State transition diagram
POWER-OFF
Out of
Field
On Field
READY
Chip_ID8bits = RND
INITIATE()
Out of
Field
INVENTORY
Out of
Field
INITIATE() or PCALL16()
or SLOT_MARKER(SN) or
SELECT(wrong Chip_ID)
SELECT(Chip_ID)
RESET_TO_INVENTORY()
Out of
Field
SELECT(Chip_ID)
SELECTED
DESELECTED
COMPLETION()
Out of
Field
DEACTIVATED
SELECT(≠ Chip_ID)
SELECT(Chip_ID)
READ_BLOCK()
WRITE_BLOCK()
AUTHENTICATE()
GET_UID()
AI05733
22/50
SRIX4K
7
Anticollision
Anticollision
The SRIX4K provides an anticollision mechanism that searches for the Chip_ID of each
device that is present in the reader field range. When known, the Chip_ID is used to select
an SRIX4K individually, and access its memory. The anticollision sequence is managed by
the reader through a set of commands described in Section 5: SRIX4K operation:
●
INITIATE()
●
PCALL16()
●
SLOT_MARKER().
The reader is the master of the communication with one or more SRIX4K device(s). It
initiates the tag communication activity by issuing an INITIATE(), PCALL16() or
SLOT_MARKER() command to prompt the SRIX4K to answer. During the anticollision
sequence, it might happen that two or more SRIX4K devices respond simultaneously, so
causing a collision. The command set allows the reader to handle the sequence, to separate
SRIX4K transmissions into different time slots. Once the anticollision sequence has
completed, SRIX4K communication is fully under the control of the reader, allowing only one
SRIX4K to transmit at a time.
The Anticollision scheme is based on the definition of time slots during which the SRIX4K
devices are invited to answer with minimum identification data: the Chip_ID. The number of
slots is fixed at 16 for the PCALL16() command. For the INITIATE() command, there is no
slot and the SRIX4K answers after the command is issued. SRIX4K devices are allowed to
answer only once during the anticollision sequence. Consequently, even if there are several
SRIX4K devices present in the reader field, there will probably be a slot in which only one
SRIX4K answers, allowing the reader to capture its Chip_ID. Using the Chip_ID, the reader
can then establish a communication channel with the identified SRIX4K. The purpose of the
anticollision sequence is to allow the reader to select one SRIX4K at a time.
The SRIX4K is given an 8-bit Chip_ID value used by the reader to select only one among up
to 256 tags present within its field range. The Chip_ID is initialized with a random value
during the READY state, or after an INITIATE() command in the INVENTORY state.
The four least significant bits (b0 to b3) of the Chip_ID are also known as the
CHIP_SLOT_NUMBER. This 4-bit value is used by the PCALL16() and SLOT_MARKER()
commands during the anticollision sequence in the INVENTORY state.
Figure 20. SRIX4K Chip_ID description
b7
b6
b5
b4
b3
b2
b1
b0
8-bit Chip_ID
b0 to b3: CHIP_SLOT_NUMBER
ai07668
Each time the SRIX4K receives a PCALL16() command, the CHIP_SLOT_NUMBER is
given a new 4-bit random value. If the new value is 0000b, the SRIX4K returns its whole 8-bit
Chip_ID in its answer to the PCALL16() command. The PCALL16() command is also used
to define the slot number 0 of the anticollision sequence. When the SRIX4K receives the
SLOT_MARKER(SN) command, it compares its CHIP_SLOT_NUMBER with the
SLOT_NUMBER parameter (SN). If they match, the SRIX4K returns its Chip_ID as a
response to the command. If they do not, the SRIX4K does not answer. The
SLOT_MARKER(SN) command is used to define all the anticollision slot numbers from 1 to
15.
23/50
24/50
S
O
F
Time
Comment
Timing
SRIX devices
Reader
PCALL 16
Request
E
O
F
No
collision
t2
E
O
F
t0 + t1
Answer
Chip_ID
X0h
<->
S
O
F
>
<->
<
Slot 0
S
O
F
Slot
Marker
(1)
E
O
F
t0 + t1
<->
<
Answer
Chip_ID
X1h
Collision
S Answer
O Chip_ID
F
X1h
S
O
F
Slot 1
E
O
F
E
O
F
t2
<->
>
S
O
F
Slot
Marker
(2)
E
O
F
t3
>
No
Answer
<
<
Slot 2
>
S
O
F
...
...
Slot N
E
O
F
t0 + t1
t2
E
O
F
<->
Slot
Marker
(15)
<->
S
O
F
<
S
O
F
No
collision
Answer
Chip_ID
XFh
Slot 15
1. The value X in the Answer Chip_ID means a random hexadecimal character from 0 to F.
>
t2
<->
Ai09035b
E
O
F
>
Anticollision
SRIX4K
Figure 21. Description of a possible anticollision sequence
SRIX4K
7.1
Anticollision
Description of an anticollision sequence
The anticollision sequence is initiated by the INITIATE() command which triggers all the
SRIX4K devices that are present in the reader field range, and that are in INVENTORY
state. Only SRIX4K devices in INVENTORY state will respond to the PCALL16() and
SLOT_MARKER(SN) anticollision commands.
A new SRIX4K introduced in the field range during the anticollision sequence will not be
taken into account as it will not respond to the PCALL16() or SLOT_MARKER(SN)
command (READY state). To be considered during the anticollision sequence, it must have
received the INITIATE() command and entered the INVENTORY state.
Table 4 shows the elements of a standard anticollision sequence. (See Figure 22 for an
example.)
Table 4.
Standard anticollision sequence
Step 1
Init:
Send INITIATE().
– If no answer is detected, go to step1.
– If only 1 answer is detected, select and access the SRIX4K. After accessing the
SRIX4K, deselect the tag and go to step1.
– If a collision (many answers) is detected, go to step2.
Step 2
Slot 0
Send PCALL16().
– If no answer or collision is detected, go to step3.
– If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step3.
Step 3
Slot 1
Send SLOT_MARKER(1).
– If no answer or collision is detected, go to step4.
– If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step4.
Step 4
Slot 2
Send SLOT_MARKER(2).
– If no answer or collision is detected, go to step5.
– If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step5.
Step N
Send SLOT_MARKER(3 up to 14) ...
Slop N – If no answer or collision is detected, go to stepN+1.
– If 1 answer is detected, store the Chip_ID, Send SELECT() and go to stepN+1.
Send SLOT_MARKER(15).
Step 17 Slot 15 – If no answer or collision is detected, go to step18.
– If 1 answer is detected, store the Chip_ID, Send SELECT() and go to step18.
Step 18
All the slots have been generated and the Chip_ID values should be stored into
the reader memory. Issue the SELECT(Chip_ID) command and access each
identified SRIX4K one by one. After accessing each SRIX4K, switch them into
DESELECTED or DEACTIVATED state, depending on the application needs.
– If collisions were detected between Step2 and Step17, go to Step2.
– If no collision was detected between Step2 and Step17, go to Step1.
After each SLOT_MARKER() command, there may be several, one or no answers from the
SRIX4K devices. The reader must handle all the cases and store all the Chip_IDs, correctly
decoded. At the end of the anticollision sequence, after SLOT_MARKER(15), the reader
can start working with one SRIX4K by issuing a SELECT() command containing the desired
Chip_ID. If a collision is detected during the anticollision sequence, the reader has to
generate a new sequence in order to identify all unidentified SRIX4K devices in the field.
The anticollision sequence can stop when all SRIX4K devices have been identified.
25/50
Anticollision
SRIX4K
Figure 22. Example of an anticollision sequence
Command
Tag 1
Tag 2
Tag 3
Tag 4
Tag 5
Tag 6
Tag 7
Tag 8
Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
Comments
READY State
28h
75h
40h
01h
02h
FEh
A9h
7Ch
Each tag gets a random Chip_ID
INITIATE ()
40h
13h
3Fh
4Ah
50h
48h
52h
7Ch
Each tag get a new random Chip_ID.
All tags answer: collisions
45h
12h
30h
43h
55h
43h
53h
73h
PCALL16()
SELECT(30h)
30h
All CHIP_SLOT_NUMBERs get
a new random value
Slot0: only one answer
30h
Tag3 is identified
SLOT_MARKER(1)
Slot1: no answer
SLOT_MARKER(2)
12h
Slot2: only one answer
SELECT(12h)
12h
Tag2 is identified
SLOT_MARKER(3)
43h
43h
53h
73h
SLOT_MARKER(4)
SLOT_MARKER(5)
Slot3: collisions
Slot4: no answer
45h
55h
Slot5: collisions
SLOT_MARKER(6)
Slot6: no answer
SLOT_MARKER(N)
SlotN: no answer
SLOT_MARKER(F)
SlotF: no answer
All CHIP_SLOT_NUMBERs get
a new random value
Slot0: collisions
PCALL16()
40h
41h
53h
42h
50h
74h
50h
40h
SLOT_MARKER(1)
41h
Slot1: only one answer
SELECT(41h)
41h
Tag4 is identified
SLOT_MARKER(2)
42h
Slot2: only one answer
SELECT(42h)
42h
Tag6 is identified
SLOT_MARKER(3)
53h
Slot3: only one answer
SELECT(53h)
53h
Tag5 is identified
SLOT_MARKER(4)
74h
Slot4: only one answer
SELECT(74h)
74h
Tag8 is identified
SLOT_MARKER(N)
PCALL16()
SlotN: no answer
41h
SELECT(50h)
50h
All CHIP_SLOT_NUMBERs get
a new random value
Slot0: only one answer
50h
Tag7 is identified
50h
41h
Slot1: only one answer but already
found for tag4
43h
SlotN: no answer
All CHIP_SLOT_NUMBERs get
a new random value
Slot0: only one answer
SLOT_MARKER(3)
43h
Slot3: only one answer
SELECT(43h)
43h
Tag1 is identified
SLOT_MARKER(1)
SLOT_MARKER(N)
PCALL16()
All tags are identified
26/50
ai07669
SRIX4K
8
Anti-clone function
Anti-clone function
The SRIX4K provides an anti-clone function that allows the application to authentication the
device. This function uses reserved data that is stored in the SRIX4K memory at its time of
manufacture.
The Authentication system is based on a proprietary challenge/response mechanism which
allows the application software to authenticate any member of the secure memory tag
SRXxxx family from STMicroelectronics (of which the SRIX4K is the prime example). A
reader system, based on the ST CRX14 chip coupler, can check each SRIX4K tag for
authenticity, and protect the application system against silicon copies or emulators.
A complete description of the Authentication system is available under Non Disclosure
Agreement (NDA) with STMicroelectronics. For more details about this SRIX4K function,
please contact your nearest STMicroelectronics sales office.
27/50
SRIX4K commands
9
SRIX4K
SRIX4K commands
See the paragraphs below for a detailed description of the Commands available on the
SRIX4K. The commands and their hexadecimal codes are summarized in Table 5. A brief is
given in Appendix B.
Table 5.
Command code
Hexadecimal Code
28/50
Command
06h-00h
INITIATE()
06h-04h
PCALL16()
x6h
SLOT_MARKER (SN)
08h
READ_BLOCK(Addr)
09h
WRITE_BLOCK(Addr, Data)
0Ah
AUTHENTICATE(RND)
0Bh
GET_UID()
0Ch
RESET_TO_INVENTORY
0Eh
SELECT(Chip_ID)
0Fh
COMPLETION()
SRIX4K
9.1
SRIX4K commands
INITIATE() command
Command Code = 06h - 00h
INITIATE() is used to initiate the anticollision sequence of the SRIX4K. On receiving the
INITIATE() command, all SRIX4K devices in READY state switch to INVENTORY state, set
a new 8-bit Chip_ID random value, and return their Chip_ID value. This command is useful
when only one SRIX4K in READY state is present in the reader field range. It speeds up the
Chip_ID search process. The CHIP_SLOT_NUMBER is not used during INITIATE()
command access.
Figure 23. INITIATE request format
SOF
INITIATE
06h
CRCL
00h
CRCH
8 bits
EOF
8 bits
AI07670
Request parameter:
–
No parameter
Figure 24. INITIATE response format
SOF
Chip_ID
CRCL
8 bits
8 bits
CRCH
EOF
8 bits
AI07671
Response parameter:
–
Chip_ID of the SRIX4K
Figure 25. INITIATE Frame Exchange Between Reader and SRIX4K
Reader
SRIX4K
SOF
06h
00h
CRCL
CRCH
EOF
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07672b
29/50
SRIX4K commands
9.2
SRIX4K
PCALL16() command
Command Code = 06h - 04h
The SRIX4K must be in INVENTORY state to interpret the PCALL16() command.
On receiving the PCALL16() command, the SRIX4K first generates a new random
CHIP_SLOT_NUMBER value (in the 4 least significant bits of the Chip_ID).
CHIP_SLOT_NUMBER can take on a value between 0 an 15 (1111b). The value is retained
until a new PCALL16() or INITIATE() command is issued, or until the SRIX4K is powered off.
The new CHIP_SLOT_NUMBER value is then compared with the value 0000b. If they
match, the SRIX4K returns its Chip_ID value. If not, the SRIX4K does not send any
response.
The PCALL16() command, used together with the SLOT_MARKER() command, allows the
reader to search for all the Chip_IDs when there are more than one SRIX4K device in
INVENTORY state present in the reader field range.
Figure 26. PCALL16 request format
SOF
PCALL16
06h
CRCH
CRCL
04h
8 bits
EOF
8 bits
AI07673
Request parameter:
–
No parameter
Figure 27. PCALL16 response format
SOF
Chip_ID
CRCL
8 bits
8 bits
CRCH
EOF
8 bits
AI07671
Response parameter:
–
Chip_ID of the SRIX4K
Figure 28. PCALL16 frame exchange between Reader and SRIX4K
Reader
SRIX4K
SOF
06h
04h
CRCL
CRCH
EOF
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07674b
30/50
SRIX4K
9.3
SRIX4K commands
SLOT_MARKER(SN) command
Command Code = x6h
The SRIX4K must be in INVENTORY state to interpret the SLOT_MARKER(SN) command.
The SLOT_MARKER Byte code is divided into two parts:
–
b3 to b0: 4-bit command code
with fixed value 6.
–
b7 to b4: 4 bits known as the SLOT_NUMBER (SN). They assume a value
between 1 and 15. The value 0 is reserved by the PCALL16() command.
On receiving the SLOT_MARKER() command, the SRIX4K compares its
CHIP_SLOT_NUMBER value with the SLOT_NUMBER value given in the command code.
If they match, the SRIX4K returns its Chip_ID value. If not, the SRIX4K does not send any
response.
The SLOT_MARKER() command, used together with the PCALL16() command, allows the
reader to search for all the Chip_IDs when there are more than one SRIX4K device in
INVENTORY state present in the reader field range.
Figure 29. SLOT_MARKER request format
SOF
SLOT_MARKER
CRCL
X6h
8 bits
CRCH
EOF
8 bits
AI07675
Request parameter:
–
x: Slot number
Figure 30. SLOT_MARKER response format
SOF
Chip_ID
CRCL
8 bits
8 bits
CRCH
EOF
8 bits
AI07671
Response parameters:
–
Chip_ID of the SRIX4K
Figure 31. SLOT_MARKER frame exchange between Reader and SRIX4K
Reader
SRIX4K
SOF
X6h
CRCL
CRCH
EOF
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07676b
31/50
SRIX4K commands
9.4
SRIX4K
SELECT(Chip_ID) command
Command Code = 0Eh
The SELECT() command allows the SRIX4K to enter the SELECTED state. Until this
command is issued, the SRIX4K will not accept any other command, except for INITIATE(),
PCALL16() and SLOT_MARKER(). The SELECT() command returns the 8 bits of the
Chip_ID value. An SRIX4K in SELECTED state, that receives a SELECT() command with a
Chip_ID that does not match its own is automatically switched to DESELECTED state.
Figure 32. SELECT request format
SOF
SELECT
0Eh
Chip_ID
CRCL
8 bits
CRCH
8 bits
EOF
8 bits
AI07677
Request parameter:
–
8-bit Chip_ID stored during the anticollision sequence
Figure 33. SELECT Response Format
SOF
Chip_ID
CRCL
8 bits
CRCH
8 bits
EOF
8 bits
AI07671
Response parameters:
–
Chip_ID of the selected tag. Must be equal to the transmitted Chip_ID
Figure 34. SELECT frame exchange between Reader and SRIX4K
Reader
SRIX4K
SOF
0Eh
Chip_ID
CRCL
CRCH
EOF
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07678b
32/50
SRIX4K
9.5
SRIX4K commands
COMPLETION() command
Command Code = 0Fh
On receiving the COMPLETION() command, a SRIX4K in SELECTED state switches to
DEACTIVATED state and stops decoding any new commands. The SRIX4K is then locked
in this state until a complete reset (tag out of the field range). A new SRIX4K can thus be
accessed through a SELECT() command without having to remove the previous one from
the field. The COMPLETION() command does not generate a response.
All SRIX4K devices not in SELECTED state ignore the COMPLETION() command.
Figure 35. COMPLETION request format
SOF
COMPLETION
0Fh
CRCL
CRCH
8 bits
8 bits
EOF
AI07679
Request parameters:
–
No parameter
Figure 36. COMPLETION response format
No Response
AI07680
Figure 37. COMPLETION frame exchange between Reader and SRIX4K
Reader
SRIX4K
SOF
0Fh
CRCL
CRCH
EOF
No Response
AI07681
33/50
SRIX4K commands
9.6
SRIX4K
RESET_TO_INVENTORY() command
Command Code = 0Ch
On receiving the RESET_TO_INVENTORY() command, all SRIX4K devices in SELECTED
state revert to INVENTORY state. The concerned SRIX4K devices are thus resubmitted to
the anticollision sequence. This command is useful when two SRIX4K devices with the
same 8-bit Chip_ID happen to be in SELECTED state at the same time. Forcing them to go
through the anticollision sequence again allows the reader to generates new PCALL16()
commands and so, to set new random Chip_IDs.
The RESET_TO_INVENTORY() command does not generate a response.
All SRIX4K devices that are not in SELECTED state ignore the RESET_TO_INVENTORY()
command.
Figure 38. RESET_TO_INVENTORY request format
SOF
RESET_TO_INVENTORY
CRCL
CRCH
0Ch
8 bits
8 bits
EOF
AI07682
Request parameter:
–
No parameter
Figure 39. RESET_TO_INVENTORY response format
No Response
AI07680
Figure 40. RESET_TO_INVENTORY frame exchange between Reader and SRIX4K
Reader
SRIX4K
SOF
0Ch
CRCL
CRCH
EOF
No Response
AI07681
34/50
SRIX4K
9.7
SRIX4K commands
READ_BLOCK(Addr) command
Command Code = 08h
On receiving the READ_BLOCK command, the SRIX4K reads the desired block and returns
the 4 data Bytes contained in the block. Data Bytes are transmitted with the Least
Significant Byte first and each byte is transmitted with the least significant bit first.
The address byte gives access to the 128 blocks of the SRIX4K (addresses 0 to 127).
READ_BLOCK commands issued with a block address above 127 will not be interpreted
and the SRIX4K will not return any response, except for the System area located at address
255.
The SRIX4K must have received a SELECT() command and be switched to SELECTED
state before any READ_BLOCK() command can be accepted. All READ_BLOCK()
commands sent to the SRIX4K before a SELECT() command is issued are ignored.
Figure 41. READ_BLOCK request format
SOF
READ_BLOCK
08h
ADDRESS
8 bIts
CRCL
8 bits
CRCH
EOF
8 bits
AI07684
Request parameter:
–
ADDRESS: block addresses from 0 to 127, or 255
Figure 42. READ_BLOCK response format
SOF
DATA 1
DATA 2
DATA 3
DATA 4
CRCL
CRCH
8 bIts
8 bIts
8 bIts
8 bIts
8 bits
8 bIts
EOF
AI07685
Response parameters:
–
DATA 1: Less significant data Byte
–
DATA 2: Data Byte
–
DATA 3: Data Byte
–
DATA 4: Most significant data Byte
Figure 43. READ_BLOCK frame exchange between Reader and SRIX4K
S
Reader O
F
SRIX4K
08h
ADDR
E
CRCL CRCH O
F
S
<-t0-><-t1-> O DATA DATA
2
1
F
DATA
3
E
DATA CRC CRC
O
L
H
4
F
AI07686b
35/50
SRIX4K commands
9.8
SRIX4K
WRITE_BLOCK (Addr, Data) command
Command Code = 09h
On receiving the WRITE_BLOCK command, the SRIX4K writes the 4 bytes contained in the
command to the addressed block, provided that the block is available and not Writeprotected. Data Bytes are transmitted with the Least Significant Byte first, and each byte is
transmitted with the least significant bit first.
The address Byte gives access to the 128 blocks of the SRIX4K (addresses 0 to 127).
WRITE_BLOCK commands issued with a block address above 127 will not be interpreted
and the SRIX4K will not return any response, except for the System area located at address
255.
The result of the WRITE_BLOCK command is submitted to the addressed block. See the
following Figures for a complete description of the WRITE_BLOCK command:
–
Figure 12: Resettable OTP area (addresses 0 to 4).
–
Figure 15: Binary counter (addresses 5 to 6).
–
Figure 17: EEPROM (addresses 7 to 127).
The WRITE_BLOCK command does not give rise to a response from the SRIX4K. The
reader must check after the programming time, tW, that the data was correctly programmed.
The SRIX4K must have received a SELECT() command and be switched to SELECTED
state before any WRITE_BLOCK command can be accepted. All WRITE_BLOCK
commands sent to the SRIX4K before a SELECT() command is issued, are ignored.
Figure 44. WRITE_BLOCK request format
SOF WRITE_BLOCK
09h
ADDRESS
DATA 1
DATA 2
DATA 3
8 bIts
8 bIts
8 bIts
8 bIts
DATA 4
CRCL
CRCH
8 bIts
8 bits
8 bIts
EOF
AI07687
Request parameters:
–
ADDRESS: block addresses from 0 to 127, or 255
–
DATA 1: Less significant data Byte
–
DATA 2: Data Byte
–
DATA 3: Data Byte
–
DATA 4: Most significant data Byte.
Figure 45. WRITE_BLOCK response format
No Response
AI07680
36/50
SRIX4K
SRIX4K commands
Figure 46. WRITE_BLOCK frame exchange between Reader and SRIX4K
Reader
SOF
09h
ADDR
DATA DATA
1
2
DATA
3
DATA CRC CRC EOF
L
H
4
No Response
SRIX4K
AI07688
9.9
GET_UID() command
Command Code = 0Bh
On receiving the GET_UID command, the SRIX4K returns its 8 UID Bytes. UID Bytes are
transmitted with the Least Significant Byte first, and each byte is transmitted with the least
significant bit first.
The SRIX4K must have received a SELECT() command and be switched to SELECTED
state before any GET_UID() command can be accepted. All GET_UID() commands sent to
the SRIX4K before a SELECT() command is issued, are ignored.
Figure 47. GET_UID request format
SOF
GET_UID
CRCL
CRCH
0Bh
8 bits
8 bits
EOF
AI07693
Request parameter:
–
No parameter
Figure 48. GET_UID response format
SOF UID 0
UID 1
UID 2
UID 3
8 bits
8 bIts
8 bIts
8 bIts
UID 4
8 bIts
UID 5
8 bIts
UID 6
8 bIts
UID 7
8 bIts
CRCL
CRCH
8 bits
8 bIts
EOF
AI07694
Response parameters:
–
UID 0: Less significant UID Byte
–
UID 1 to UID 6: UID Bytes
–
UID 7: Most significant UID Byte.
37/50
SRIX4K commands
SRIX4K
Unique Identifier (UID)
Members of the SRIX4K family are uniquely identified by a 64-bit Unique Identifier (UID).
This is used for addressing each SRIX4K device uniquely after the anticollision loop. The
UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. It is a read-only code, and
comprises (as summarized in Figure 49):
●
an 8-bit prefix, with the most significant bits set to D0h
●
an 8-bit IC Manufacturer code (ISO/IEC 7816-6/AM1) set to 02h (for
STMicroelectronics)
●
a 6-bit IC code set to 00 0011b = 3d for SRIX4K
●
a 42-bit Unique Serial Number
Figure 49. 64-bit unique identifier of the SRIX4K
Most significant bits
63
55
47
41
D0h
02h
3d
Least significant bits
0
Unique Serial Number
AI14082
Figure 50. GET_UID frame exchange between Reader and SRIX4K
Reader
S
E
O 0Bh CRCL CRCH O
F
F
S
E
<-t0-><-t1-> O UID UID UID UID UID UID UID UID CRCL CRCH O
0
1
2
3
4
5
6
7
F
F
SRIX4K
AI07692b
9.10
Power-On state
After Power-On, the SRIX4K is in the following state:
38/50
–
It is in the low-power state.
–
It is in READY state.
–
It shows highest impedance with respect to the reader antenna field.
–
It will not respond to any command except INITIATE().
SRIX4K
10
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
15
25
°C
23
months
Wafer
kept in its antistatic bag
TSTG, hSTG,
Storage conditions
tSTG
15
25
°C
40%
60%
RH
2
years
–20
20
mA
–7
7
V
–100
100
V
Human Body model(1)
–1000
1000
V
model(2)
–4000
4000
V
A3, A4, A5
ICC
VMAX
Supply current on AC0 / AC1
Input voltage on AC0 / AC1
Machine model
VESD
Electrostatic Discharge
Voltage
Human Body
(1)
1. Mil. Std. 883 - Method 3015
2. ESD test: ISO 10373-6 for proximity cards
39/50
DC and ac parameters
11
SRIX4K
DC and ac parameters
Table 7.
Operating conditions
Symbol
TA
Table 8.
Symbol
Parameter
Ambient operating temperature
Min.
Max.
Unit
–20
85
°C
DC characteristics
Parameter
Condition
Min
Typ
Max
Unit
3.5
V
VCC
Regulated voltage
ICC
Supply current (Active in Read)
VCC = 3.0 V
100
µA
ICC
Supply current (Active in Write)
VCC = 3.0 V
250
µA
VRET
Retromodulation induced voltage
ISO 10373-6
CTUN
Internal tuning capacitor
Table 9.
Symbol
fCC
2.5
20
13.56 MHz
64
pF
AC characteristics
Parameter
Condition
External RF signal frequency
MICARRIER Carrier modulation index
Minimum pulse width for start bit
tJIT
ASK modulation data jitter
tMIN CD
Minimum time from carrier
generation to first data
Min
Max
13.553 13.567
MI=(A-B)/(A+B)
tRFR, tRFF 10% Rise and Fall times
tRFSBL
mV
14
%
0.8
2.5
µs
9.44
–2
µs
+2
5
µs
ms
fS
Subcarrier frequency
fCC/16
847.5
kHz
t0
Antenna reversal delay
128/fS
151
µs
t1
Synchronization delay
128/fS
151
µs
t2
Answer to new request delay
14 ETU
132
0
tDR
Time between request characters
Coupler to SRIX4K
tDA
Time between answer characters
SRIX4K to Coupler
tW
Programming time for WRITE
µs
57
0
µs
µs
With no Auto-Erase
Cycle (OTP)
3
ms
With Auto-Erase Cycle
(EEPROM)
5
ms
Binary Counter
Decrement
7
ms
1. All timing measurements were performed on a reference antenna with the following characteristics:
External size: 75 mm x 48 mm
Number of turns: 3
Width of conductor: 1 mm
Space between 2 conductors: 0.4 mm
Value of the coil: 1.4 µH
Tuning Frequency: 14.4 MHz.
40/50
MHz
8
ETU = 128/fCC
Coupler to SRIX4K
Unit
SRIX4K
DC and ac parameters
Figure 51. SRIX4K synchronous timing, transmit and receive
ASK Modulated signal from the Reader to the Contactless device
A
tRFF
B
tRFR
ƒcc
tRFSBL
tMIN CD
FRAME Transmission between the reader and the contactless device
tDR
1
tDR
0
DATA
1
EOF
FRAME Transmitted by the reader in ASK
847KHz
FRAME Transmitted by the SRIX4K
in BPSK
t0
SOF
11 0
t1
tDA
DATA
10
DATA
10
tDA
Data jitter on FRAME Transmitted by the reader in ASK
tJIT
tJIT
tJIT
tJIT
tJIT
0
START
tRFSBL
tRFSBL
tRFSBL
tRFSBL
tRFSBL
AI09052
41/50
Package mechanical
12
SRIX4K
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 52. A3 antenna specification
A
A1
B
B1
AI09046B
Table 10.
A3 antenna specification
Symbol
Type
Min
Max
Unit
A
Coil width
38
37.5
38.5
mm
B
Coil length
38
37.5
38.5
mm
A1
Inlay width
43
42.5
43.5
mm
B1
Inlay length
43
42.5
43.5
mm
Overall thickness of copper antenna coil
110
90
130
µm
Silicon thickness
180
165
195
µm
Unloaded Q value
40
Q
FNOM
PA
42/50
Parameter
Unloaded free-air resonance
H-field energy for device operation
15.1
MHz
0.5
114
A/m
dbµA/m
SRIX4K
Package mechanical
Figure 53. A4 antenna specification
A A1
B
B1
AI07696B
Table 11.
A4 antenna specification
Symbol
Parameter
Type
Min
Max
Unit
A
Coil width
15
14.5
15.5
mm
B
Coil length
15
14.5
15.5
mm
A1
Inlay width
19
18.5
19.5
mm
B1
Inlay length
19
18.5
19.5
mm
Overall thickness of copper antenna coil
110
90
130
µm
Silicon thickness
180
165
195
µm
Unloaded Q value
30
Q
FNOM
PA
Unloaded free-air resonance
H-field energy for device operation
14.5
MHz
1.5
123.5
A/m
dbµA/m
43/50
Package mechanical
SRIX4K
Figure 54. A5 antenna specification
A
A1
B
B1
AI09071B
Table 12.
A5 antenna specification
Symbol
Type
Min
Max
Unit
A
Coil width
42
41.5
42.5
mm
B
Coil length
65
64.5
65.5
mm
A1
Inlay width
46
45.5
46.5
mm
B1
Inlay length
70
69.5
70.5
mm
Overall thickness of copper antenna coil
140
130
150
µm
Silicon thickness
180
165
195
µm
Unloaded Q value
30
Q
FNOM
PA
44/50
Parameter
Unloaded free-air resonance
H-field energy for device operation
14.8
MHz
0.25
108
A/m
dbµA/m
SRIX4K
13
Part numbering
Part numbering
Table 13.
Ordering information scheme
Example:
SRIX4K
–
W4
/XXX
Device type
SRIX4K
Package
W4 =180 µm ± 15 µm Unsawn Wafer
SBN18= 180 µm ± 15 µm Bumped and Sawn Wafer on 8-inch Frame
A3T = 38 mm x 38 mm Copper Antenna on Continuous Tape
A3S = 38 mm x 38 mm Copper Singulated Adhesive Antenna on Tape
A4T = 15 mm x 15 mm Copper Antenna on Continuous Tape
A4S = 15 mm x 15 mm Copper Singulated Adhesive Antenna on Tape
A5T = 42 mm x 65 mm Copper Antenna on Continuous Tape
A5S = 42 mm x 65 mm Copper Singulated Adhesive Antenna on Tape
Customer code
XXX = Given by STMicroelectronics
Note: Devices are shipped from the factory with the memory content bits erased to 1.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
45/50
ISO 14443 Type B CRC calculation
Appendix A
SRIX4K
ISO 14443 Type B CRC calculation
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#define BYTE unsigned char
#define USHORT unsigned short
unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc)
{
ch = (ch^(BYTE)((*lpwCrc) & 0x00FF));
ch = (ch^(ch<<4));
*lpwCrc = (*lpwCrc >> 8)^((USHORT)ch <<
8)^((USHORT)ch<<3)^((USHORT)ch>>4);
return(*lpwCrc);
}
void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE
*TransmitSecond)
{
BYTE chBlock; USHORTt wCrc;
wCrc = 0xFFFF; // ISO 3309
do
{
chBlock = *Data++;
UpdateCrc(chBlock, &wCrc);
} while (--Length);
wCrc = ~wCrc; // ISO 3309
*TransmitFirst = (BYTE) (wCrc & 0xFF);
*TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF);
return;
}
int main(void)
{
BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i;
printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1”);
printf("CRC_B of [ ");
for(i=0; i<4; i++)
printf("%02X ",BuffCRC_B[i]);
ComputeCrc(BuffCRC_B, 4, &First, &Second);
printf("] Transmitted: %02X then %02X.”, First, Second);
return(0);
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SRIX4K
SRIX4K command summary
Appendix B
SRIX4K command summary
Figure 55. INITIATE frame exchange between Reader and SRIX4K
Reader
SOF
06h
00h
CRCL
CRCH
EOF
SRIX4K
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07672b
Figure 56. PCALL16 frame exchange between Reader and SRIX4K
Reader
SOF
06h
04h
CRCL
CRCH
EOF
SRIX4K
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07674b
Figure 57. SLOT_MARKER frame exchange between Reader and SRIX4K
Reader
SOF
X6h
CRCL
CRCH
EOF
SRIX4K
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07676b
Figure 58. SELECT frame exchange between Reader and SRIX4K
Reader
SOF
0Eh
Chip_ID
CRCL
CRCH
SRIX4K
EOF
<-t0-><-t1-> SOF
Chip_ID
CRCL
CRCH
EOF
AI07678b
Figure 59. COMPLETION frame exchange between Reader and SRIX4K
Reader
SRIX4K
SOF
0Fh
CRCL
CRCH
EOF
No Response
AI07681
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SRIX4K command summary
SRIX4K
Figure 60. RESET_TO_INVENTORY frame exchange between Reader and SRIX4K
Reader
SOF
0Ch
CRCL
CRCH
EOF
SRIX4K
No Response
AI07681
Figure 61. READ_BLOCK frame exchange between Reader and SRIX4K
S
Reader O
F
08h
ADDR
E
CRCL CRCH O
F
S
<-t0-><-t1-> O DATA DATA
1
2
F
SRIX4K
DATA
3
E
DATA CRC CRC
L
H O
4
F
AI07686b
Figure 62. WRITE_BLOCK frame exchange between Reader and SRIX4K
Reader
SOF
09h
ADDR
DATA DATA
1
2
DATA
3
DATA CRC CRC EOF
L
H
4
No Response
SRIX4K
AI07688
Figure 63. GET_UID frame exchange between Reader and SRIX4K
Reader
SRIX4K
S
E
O 0Bh CRCL CRCH O
F
F
S
E
<-t0-><-t1-> O UID UID UID UID UID UID UID UID CRCL CRCH O
0
1
2
3
4
5
6
7
F
F
AI07692b
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SRIX4K
Revision history
Revision history
Table 14.
Date
Document revision history
Version
Changes
28-Nov-2002
1.0
Document written
17-Jul-2003
1.1
Data briefing extracted
12-Mar-2004
2.0
First public release of full datasheet
26-Apr-2004
3.0
Correction to memory map
29-Nov-2004
4.0
Package mechanical section revised.
13-Dec-2004
5.0
VRET and CTUN parameters added to Table 8: DC characteristics.
17-Aug-2005
6.0
Updated initial counter values in Section 4.2: 32-bit binary counters on
page 16.
10-Apr-2007
7
Document reformatted. Small text changes.
All antennas are ECOPACK® compliant.
Unique Identifier (UID) on page 38 added. CTUN min and max values
removed, typical value added in Table 8: DC characteristics.
Space removed between t0 and t1 in “frame exchange between Reader
and SRIX4K” Figures (see Appendix B: SRIX4K command summary on
page 47).
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SRIX4K
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