L6732 Adjustable step-down controller with synchronous rectification Features ■ Input voltage range from 1.8V to 14V ■ Supply voltage range from 4.5V to 14V ■ Adjustable output voltage down to 0.6V with ±0.8% accuracy over line voltage and temperature (0°C~125°C) ■ Fixed frequency voltage mode control ■ TON lower than 100ns ■ 0% to 100% duty cycle ■ External input voltage reference ■ Soft-start and inhibit ■ High current embedded drivers ■ Predictive anti-cross conduction control ■ Programmable high-side and low-side RDS(on) sense over-current-protection HTSSOP16 (Exposed Pad) Applications ■ LCD & PDP TV ■ Selectable switching frequency 250KHz/ 500KHz ■ High performance / high density DC-DC modules ■ Pre-bias start up capability ■ Low voltage distributed DC-DC ■ Power good output ■ niPOL converters ■ Master/slave synchronization with 180° phase shift ■ DDR memory supply ■ Graphic cards ■ Over voltage protection ■ Thermal shut-down ■ Package: HTSSOP16 Order codes Part number Package Packing L6732 HTSSOP16 Tube L6732TR HTSSOP16 Tape & Reel September 2006 Rev 5 1/36 www.st.com 36 L6732 Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 12 5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.9 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.12 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.13 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.13.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/36 L6732 6 7 Contents Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 L6732 demoboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 20A board description and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 5A board description and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3/36 Summary description 1 L6732 Summary description The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPOL converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of ±0.8% and it is also possible to use an external reference from 0V to 2.5V. The input voltage can range from 1.8V to 14V, while the supply voltage can range from 4.5V to 14V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The PWM duty cycle can range from 0% to 100% with a minimum on-time (TON, MIN) lower than 100ns making possible conversions with very low duty cycle at high switching frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250KHz or 500KHz). The error amplifier features a 10MHz gain-bandwidth-product and 5V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the RDS(ON) of both the high-side and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. During the soft-start, the sink mode capability is disabled in order to allow a proper start-up also in pre-biased output voltage conditions. After the soft-start the device can sink current. Other features are Power-Good, Master/Slave synchronization (with 180° phase shift), over-voltage-protection, feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters. 4/36 L6732 1.1 Figure 1. Summary description Functional description Block diagram Vcc=4.5V-14V Vin=1.8V-14V OCH OCL VCCDR BOOT LDO SS Monitor HGATE Protection and Ref OSC - PHASE VOUT EAREF L6732 PGOOD + - LGATE - 0.6V + PWM PGND E/A SYNCH + FB GND - COMP 5/36 L6732 Electrical data 2 Electrical data 2.1 Maximum rating Table 1. Absolute maximum ratings Symbol Parameter Value Unit -0.3 to 18 V 0 to 6 V 0 to VBOOT - VPHASE V BOOT -0.3 to 24 V PHASE -1 to 18 VCC to GND and PGND, OCH, PGOOD VCC VBOOT - VPHASE Boot Voltage VHGATE - VPHASE VBOOT VPHASE PHASE Spike, transient < 50ns (FSW = 500KHz) SS, FB, EAREF, SYNC, OCL, LGATE, COMP, VCCDR OCH Pin PGOOD Pin OTHER PINS 2.2 V +24 -0.3 to 6 V ±1500 ±1000 V ±2000 Thermal data Table 2. Symbol 6/36 Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002 "Human Body Model" Acceptance Criteria: "Normal Performance" -3 Thermal data Description Value Unit 50 °C/W RthJA Thermal Resistance Junction to Ambient TSTG Storage temperature range -40 to +150 °C TJ Junction operating temperature range -40 to +125 °C TA Ambient operating temperature range -40 to +85 °C L6732 3 Pin connections and functions Pin connections and functions Figure 2. Pins connection ( top view) PGOOD 1 16 VCC SYNCH 2 15 VCCDR SGND 3 14 LGATE FB 4 13 PGND COMP 5 12 BOOT SS/INH 6 11 HGATE EAREF 7 10 PHASE OCL 8 9 OCH HTSSOP16 Table 3. Pin functions Pin n. Name Function 1 PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up this pin to VCCDR with a 10K resistor to obtain a logical signal. 2 SYNCH It is a Master-Slave pin. Two or more devices can be synchronized by simply connecting the SYNCH pins together. The device operating with the highest FSW will be the Master. The Slave devices will operate with 180° phase shift from the Master. The best way to synchronize devices together is to set their FSW at the same value. If it is not used the SYNCH pin can be left floating. 3 SGND 4 FB 5 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. 6 SS/INH The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10 A through the capacitor. When the voltage at this pin is lower than 0.5V the device is disabled. All the internal references are referred to this pin. This pin is connected to the error amplifier inverting input. Connect it to VOUT through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. 7/36 L6732 Pin connections and functions Table 3. Pin n. Pin functions Name Function By setting the voltage at this pin is possible to select the internal/external reference and the switching frequency: VEAREF 0-80% of VCCDR -> External Reference/FSW=250KHz 7 EAREF VEAREF = 80%-95% of VCCDR -> VREF = 0.6V/FSW=500KHz VEAREF = 95%-100% of VCCDR -> VREF = 0.6V/FSW=250KHz An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100µA (IOCL) from this pin to ground through the external resistor (ROCL). The over-current threshold is given by the following equation: 8 OCL I OCL • I OCL I VALLEY = -------------------------------2 • R DSONLS Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the high-frequency noise related to the GND. Connect a capacitor only to a "clean" GND. 9 OCH A resistor connected from this pin and the high-side MOSFET(s) drain sets the peakcurrent-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100µA current generator (IOCH) sinks a current from the drain through the external resistor (ROCH). The over-current threshold is given by the following equation: I OCH • R OCH I PEAK = --------------------------------R DSONHS 8/36 10 PHASE This pin is connected to the source of the high-side MOSFET(s) and provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL. 11 HGATE This pin is connected to the high-side MOSFET(s) gate. 12 BOOT Through this pin is supplied the high-side driver. Connect a capacitor from this pin to the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT). 13 PGND This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device. 14 LGATE This pin is connected to the low-side MOSFET(s) gate. 15 VCCDR 5V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with at least 1µF ceramic cap. 16 VCC Supply voltage pin. The operative supply voltage range is from 4.5V to 14V. L6732 4 Electrical characteristics Electrical characteristics VCC = 12V, TA = 25°C, unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition VCC Stand by current OSC = open; SS to GND VCC quiescent current OSC= open; HG = open, LG = open, PH=open Turn-ON VCC threshold VOCH = 1.7V Turn-OFF VCC threshold VOCH = 1.7V Min. Typ. Max. Unit 7 9 8.5 10 4.0 4.2 4.4 V 3.6 3.8 4.0 V VCC supply current ICC mA Power-ON VCC VIN OK Turn-ON VOCH threshold 1.1 1.25 1.47 V VIN OK Turn-OFF VOCH threshold 0.9 1.05 1.27 V 4.5 5 5.5 V SS = 2V 7 10 13 SS = 0 to 0.5V 20 30 45 237 250 263 KHz 450 500 550 KHz VCCDR regulation VCCDR voltage VCC = 5.5V to 14V IDR = 1mA to 100mA Soft start and inhibit ISS Soft Start Current µA Oscillator fOSC ∆VOSC Accuracy Ramp Amplitude 2.1 V Output voltage VFB Output Voltage VDIS = 0 to Vth 0.597 0.6 0.603 V 9/36 L6732 Table 4. Electrical characteristics Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 70 100 150 kΩ 0.290 0.5 µA Error amplifier REAREF IFB EAREF Input resistance Vs. GND I.I. bias current VFΒ = 0V Ext Ref Clamp 2.3 VOFFSET V Error amplifier offset Vref = 0.6V GV Open Loop Voltage Gain Guaranteed by design 100 dB GBWP Gain-Bandwidth Product Guaranteed by design 10 MHz Slew-Rate COMP = 10pF Guaranteed by design 5 V/µs High Side Source Resistance VBOOT - VPHASE = 5V 1.7 Ω RHGATE_OFF High Side Sink Resistance VBOOT - VPHASE = 5V 1.12 Ω RLGATE_ON VCCDR = 5V 1.15 Ω VCCDR = 5V 0.6 Ω SR -5 +5 mV Gate drivers RHGATE_ON Low Side Source Resistance RLGATE_OFF Low Side Sink Resistance Protections IOCH OCH Current Source IOCL OCL Current Source VOCH = 1.7V 90 100 110 µΑ 90 100 110 µΑ VFB Rising Over Voltage Trip (VFB / VEAREF) OVP VEAREF = 0.6V VFB Falling VEAREF = 0.6V 120 % 117 % Power Good OCH Current Source VOCH = 1.7V OCL Current Source OVP Table 5. Over Voltage Trip (VFB / VEAREF) VFB Rising 90 100 110 µΑ 90 100 110 µΑ % 120 VEAREF = 0.6V Thermal characteristics (VCC = 12V) Symbol Parameter Test condition Min. Typ. Max. TJ = 0°C~ 125°C 0.596 0.6 0.605 TJ = -40°C~ 125°C 0.593 0.6 0.605 Unit Output voltage VFB Output Voltage V 10/36 L6732 Device description 5 Device description 5.1 Oscillator The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper voltage at the EAREF pin (see Table 3. Pins function and section 4.3 Internal and external reference). 5.2 Internal LDO An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5V) is the VCCDR pin (Figure 3.). Figure 3. LDO block diagram. 4.5÷14V LDO The LDO can be by-passed, providing directly a 5V voltage to VCCDR. In this case VCC and VCCDR pins must be shorted together as shown in Figure 4. VCCDR pin must be filtered with at least 1µF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. VCCDR also represents a voltage reference for PGOOD pin (see Table 3. Pins Function). 11/36 Device description 5.3 L6732 Bypassing the LDO to avoid the voltage drop with low Vcc If VCC≈ 5V the internal LDO works in dropout with an output resistance of about 1Ω. The maximum LDO output current is about 100mA and so the output voltage drop is 100mV, to avoid this the LDO can be bypassed. Figure 4. 5.4 Bypassing the LDO Internal and external references It is possible to set the internal/external reference and the switching frequency by setting the proper voltage at the EAREF pin. The maximum value of the external reference depends on the VCC: with VCC = 4V the clamp operates at about 2V (typ.), while with VCC greater than 5V the maximum external reference is 2.5V (typ.). ● VEAREF from 0% to 80% of VCCDR -> External reference/Fsw=250KHz ● VEAREF from 80% to 95% of VCCDR -> VREF = 0.6V/Fsw=500KHz ● VEAREF from 95% to 100% of VCCDR -> VREF = 0.6V/Fsw=250KHz Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered: ● The minimum OVP threshold is set at 300mV; ● The under-voltage-protection doesn't work; ● The PGOOD signal remains low; To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into the device (see Figure 5.). Finally it must be taken into account that the voltage at the EAREF pin is captured by the device at the start-up when VCC is about 4V. 12/36 L6732 5.5 Figure 5. 5.6 Device description Error amplifier Error amplifier reference Soft start When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is 35µA and charges the capacitor up to 0.5V. After that it becomes 10µA until the final charge value of approximately 4V (see Figure 6). The output of the error amplifier is clamped with this voltage (VSS) until it reaches the programmed value. No switching activity is observable if VSS is lower than 0.5V and both MOSFETs are OFF. When VSS is between 0.5V and 1.1V the low-side MOSFET is turned on because the comp signal is lower than the valley of the triangular wave and so the duty-cycle is 0%. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) even the high-side MOSFET begins to switch and the output voltage starts to increase. The L6732 can only source current during the soft-start phase in order to manage the prebias start-up applications. This means that when the start-up occurs with output voltage greater than 0V (pre-bias startup), even when Vss is between 0.5V and 1.1V the low-side MOSFET is kept OFF (see Figure 7 and Figure 8). 13/36 L6732 Device description Figure 6. Device start-up: voltage at the SS pin. Vcc Vin 4.2V VCC VIN 1.25V t Vss 4V 0.5V t Figure 7. Start-up without pre-bias LGate VOUT IL VSS 14/36 L6732 Figure 8. Device description Start-up with pre-bias LGate VOUT IL VSS The L6732 can sink or source current after the soft-start phase (see Figure 9.). If an over current is detected during the soft-start phase, the device provides a constant-currentprotection. In this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value and so, in case of high ripple current during the soft-start, the converter can start in any case, limiting the current (see section 4.6 Monitoring and protections) but not entering in HICCUP mode. Figure 9. Inductor current during and after soft-start. VOUT VSS VCC IL During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. 15/36 L6732 Device description 5.7 Driver section The high-side and low-side drivers allow using different types of power MOSFETs (also multiple MOSFETs to reduce the RDSON), maintaining fast switching transitions. The low-side driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead time control avoids MOSFETs cross-conduction maintaining very short dead time duration in the range of 20ns. The control monitors the phase node in order to sense the low-side body diode recirculation. If the phase node voltage is less than a certain threshold (-350mV typ.) during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control doesn't work when the high-side body diode is conducting because the phase node doesn't go negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. 5.8 Monitoring and protections The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference, the low-side driver is turned on as long as the over voltage is detected (see Figure 10.). Figure 10. OVP LGate FB It must be taken into account that there is an electrical network between the output terminal and the FB pin and therefore the voltage at the pin is not a perfect replica of the output voltage. However due to the fact that the converter can sink current, in the most of cases the low-side will turn-on before the output voltage exceeds the over-voltage threshold, because the error amplifier will throw off balance in advance. Even if the device doesn't report an over-voltage, the behavior is the same, because the low-side is turned-on immediately. The following figure shows the device behavior during an over-voltage event. The output voltage rises with a slope of 100mV/µs, emulating in this way the breaking of the high-side MOSFET as an over-voltage cause. 16/36 L6732 Device description Figure 11. OVP: the low-side MOSFET is turned-on in advance. VOUT 109% VFB LGate The device realizes the over-current-protection (OCP) sensing the current both on the high-side MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in Table 3. Pins function): ● Peak Current Limit ● Valley Current Limit The Peak Current Protection is active when the high-side MOSFET(s) is turned on, after a masking time of about 100ns. The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a masking time of about 400ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-protection) the device enters in HICCUP mode: the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10µA and when the voltage at the SS pin reaches 0.5V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the TON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned off (after the masking time and the internal delay) and returned on at the next pwm cycle. The limit of this protection is that the TON can't be less than masking time plus propagation delay because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-current-protection is very helpful in this case to limit the current. If during the off-time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned on until the current is over the valleycurrent-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula: I MAX = IVALLEY + Vin − Vout ⋅ TON , MIN L (4) In constant current protection a current control loop limits the value of the error amplifier output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. Figure 12. shows the behaviour of the device during an over current condition that persists also in the soft-start phase. 17/36 L6732 Device description 5.9 HICCUP mode during an OCP Figure 12. Constant current and Hiccup mode during an OCP. VSS VCOMP IL 5.10 Thermal shutdown When the junction temperature reaches 150°C ±10°C the device enters in thermal shutdown. Both MOSFETs are turned off and the soft-start capacitor is rapidly discharged with an internal switch. The device doesn't restart until the junction temperature goes down to 120°C and, in any case, until the voltage at the soft-start pin reaches 500mV. 5.11 Synchronization The presence of many converters on the same board can generate beating frequency noise. To avoid this it is important to make them operate at the same switching frequency. Moreover, a phase shift between different modules helps to minimize the RMS current on the common input capacitors. Figure 13 and Figure 14 shows the results of two modules in synchronization. Two or more devices can be synchronized simply connecting together the SYNCH pins. The device with the higher switching frequency will be the Master while the other one will be the Slave. The Slave controller will increase its switching frequency reducing the ramp amplitude proportionally and then the modulator gain will be increased. 18/36 L6732 Device description Figure 13. Synchronization: PWM Signal Figure 14. Synchronization: Inductor currents To avoid a huge variation of the modulator gain, the best way to synchronize two or more devices is to make them work at the same switching frequency and, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. If, during synchronization between two (or more) L6732, it's important to know in advance which the master is, it's timely to set its switching frequency at least 15% higher than the slave. Using an external clock signal (fEXT) to synchronize one or more devices that are working at a different switching frequency (fSW) it is recommended to follow the below formula: f SW ≤ f EXT ≤ 1,3 ⋅ f SW (5) The phase shift between master and slaves is approximately 180°. 19/36 L6732 Device description 5.12 Minimum on-time (TON, MIN) The device can manage minimum on-times lower than 100ns. This feature comes down from the control topology and from the particular over-current-protection system of the L6732. In fact, in a voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6732, neither for the over-current protection, given that during the off-time the valley-current-protection can operate in every case. The first advantage related to this feature is the possibility to realize extremely low conversion ratios. Figure 15 shows a conversion from 14V to 0.3V at 500KHz with a TON of about 50ns. Figure 15. 14V -> 0.3V@500KHz, 5A VOUT IL VPHASE 50ns The on-time is limited by the turn-on and turn-off times of the MOSFETs. 20/36 L6732 5.13 Device description Bootstrap anti-discharging system This built-in system avoids that the voltage across the bootstrap capacitor becomes less than 3.3V. An internal comparator senses the voltage across the external bootstrap capacitor keeping it charged, eventually turning-on the low-side MOSFET for approximately 200ns. If the bootstrap capacitor is not enough charged the high-side MOSFET cannot be effectively turnedon and it will present a higher RDSON. In some cases the OCP can be also triggered. The bootstrap capacitor can be discharged during the soft-start in case of very long soft-start time and light loads. It's also possible to mention one application condition during which the bootstrap capacitor can be discharged: 5.13.1 Fan's power supply In many applications the FAN is a DC MOTOR driven by a voltage-mode DC/DC converter. Often only the speed of the MOTOR is controlled by varying the voltage applied to the input terminal and there's no control on the torque because the current is not directly controlled. In order to vary the MOTOR speed the output voltage of the converter must be varied. The L6732 has a dedicated pin called EAREF (see the related section) that allows providing an external reference to the non-inverting input of the error-amplifier. In these applications the duty cycle depends on the MOTOR's speed and sometimes 100% has to be set in order to go at the maximum speed. Unfortunately in these conditions the bootstrap capacitor can not be recharged and the system cannot work properly. Some PWM controller limits the maximum duty-cycle to 80-90% in order to keep the bootstrap cap charged but this make worse the performance during the load transient. Thanks to the "bootstrap antidischarging system" the L6732 can work at 100% without any problem. The following picture shows the device behaviour when input voltage is 5V and 100% is set by the external reference. Figure 16. 100% duty cycle operation 21/36 L6732 Application details 6 Application details 6.1 Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current (∆IL) between 20% and 30% of the maximum output current. The inductance value can be calculated with the following relationship: L≅ Vin − Vout Vout ⋅ Fsw ⋅ ∆I L Vin (6) Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 17. shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V at a switching frequency of 500KHz. INDUCT O R CURRE NT RIP P L Figure 17. Inductor current ripple. 8 7 V in = 1 2 V , L = 1 u H 6 5 4 3 V in = 1 2 V , L = 2 u H 2 V in = 5 V , L = 5 0 0 n H 1 V in = 5 V , L = 1 .5 u H 0 0 1 2 3 4 O UT P UT V O L T AG E (V ) Increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size. 22/36 L6732 6.2 Application details Output capacitors The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): ∆Vout ESR = ∆Iout ⋅ ESR (7) Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas: ∆VoutCOUT = ∆Iout 2 ⋅ L 2 ⋅ Cout ⋅ (Vin, min⋅ D max − Vout ) ∆VoutCOUT = ∆Iout 2 ⋅ L 2 ⋅ Cout ⋅Vout (8) (9) Formula (8) is valid in case of positive load transient while the formula (9) is valid in case of negative load transient. DMAX is the maximum duty cycle value that in the L6732 is 100%. For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR and a minimum COUT value can be set. The ESR and COUT values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula: ∆Vout = ∆I L ⋅ ( ESR + 1 ) 8 ⋅ Cout ⋅ Fsw (10) Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible. 6.3 Input capacitors The input capacitors have to sustain the RMS current flowing through them, that is: Irms = Iout ⋅ D ⋅ (1 − D) (11) Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5. The losses in worst case are: P = ESR ⋅ (0.5 ⋅ Iout ) 2 (12) 23/36 L6732 Application details 6.4 Compensation network The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulsewidth modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of VOUT/ VCOMP. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC. Figure 18. Compensation Network The compensation network consists in the internal error amplifier, the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation networks, the following suggestions may be used: ● Modulator singularity frequencies: ω LC = ● 24/36 1 L ⋅ Cout (13) ω ESR = 1 ESR ⋅ Cout (14) Compensation network singularity frequencies: ω P1 = 1 (15) ⎛ C18 ⋅ C19 ⎞ ⎟⎟ R5 ⋅ ⎜⎜ ⎝ C18 + C19 ⎠ ωZ 1 = 1 R5 ⋅ C19 (17) ωP 2 = ωZ 2 = 1 R4 ⋅ C20 1 C20 ⋅ (R3 + R4 ) (16) (18) L6732 Application details ● Compensation network design: – Put the gain R5/R3 in order to obtain the desired converter bandwidth ϖC = R5 Vin ⋅ ⋅ϖ LC (19) R3 ∆Vosc – Place ωZ1 before the output filter resonance ωLC; – Place ωZ2 at the output filter resonance ωLC; – Place ωP1 at the output capacitor ESR zero ωESR; – Place ωP2 at one half of the switching frequency; – Check the loop gain considering the error amplifier open loop gain. Figure 19. Asymptotic Bode plot of Converter's open loop gain 25/36 L6732 L6732 demoboards 7 L6732 demoboards 7.1 20A board description and PCB layout L6732 20A demoboard realizes in a four layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5V to 14V and the output voltage is at 3.3V. The module can deliver an output current in excess of 20A. The switching frequency is set at 250KHz (controller free-running Fsw) but it can be set to 500KHz acting on the EAREF pin. Figure 20. Demoboard schematic VIN R9 D1 C9 C11 J1 C12-C13 C10 R5 VCCDR GIN 15 R6 EAREF J2 BOOT 12 OCH R11 9 11 7 HGATE L1 Q4-6 EXT REF 10 C5 PHASE VOUT R10 VCC VCC VCCDR C8 R8 C7 PGOOD R13 GND PGOOD 14 16 U1 L6732 3 R12 LGATE D3 C15 Q1-3 13 PGND GOUT SS 1 6 C4 SYNCH SYNCH 2 8 OCL 5 4 VFB COMP R3 R7 C2 R4 C3 R2 26/36 C16-C19 R1 C1 L6732 L6732 demoboards Table 6. Demoboard part list Reference Value Manufacturer Package Supplier R1 1kΩ Neohm SMD 0603 IFARCAD R2 1kΩ Neohm SMD 0603 IFARCAD R3 4K7 R4 2k7 Neohm SMD 0603 IFARCAD R5 0Ω Neohm SMD 0603 IFARCAD R6 N.C. Neohm SMD 0603 IFARCAD R7 2K Neohm SMD 0603 IFARCAD R8 10Ω Neohm SMD 0603 IFARCAD R9 1K5 Neohm SMD 0603 IFARCAD R10 2.2Ω Neohm SMD 0603 IFARCAD R11 2.2Ω Neohm SMD 0603 IFARCAD R12 N.C. Neohm SMD 0603 IFARCAD R13 10K Neohm SMD 0603 IFARCAD C1 4.7nF Kemet SMD 0603 IFARCAD C2 47nF Kemet SMD 0603 IFARCAD C3 1nF Kemet SMD 0603 IFARCAD C4 100nF Kemet SMD 0603 IFARCAD C5 100nF Kemet SMD 0603 IFARCAD C6 N.C. / / / C7 100nF Kemet SMD 0603 IFARCAD C8 4.7uF 20V AVX SMA6032 IFARCAD C9 1nF Kemet SMD 0603 IFARCAD C10 1uF Kemet SMD 0603 IFARCAD C11 220nF Kemet SMD 0603 IFARCAD C12-13 3X 15uF / / ST (TDK) C15 N.C. / / / C16-19 2X 330uF / / ST (poscap) L1 1.8uH Panasonic SMD ST D1 STPS1L30M ST DO216AA ST D3 STPS1L30M ST DO216AA ST Q1-Q2 STS12NH3LL ST SO8 ST Q4-Q5 STS25NH3LL ST SO8 ST U1 L6732 ST HTSSOP16 ST 27/36 L6732 L6732 demoboards Table 7. Other inductor manufacturer Manufacturer Series Inductor Value (µH) Saturation Current (A) WURTH ELEKTRONIC 744318180 1.8 20 SUMIDA CDEP134-2R7MC-H 2.7 15 EPCOS HPI_13 T640 1.4 22 TDK SPM12550T-1R0M220 1 22 TOKO FDA1254 2.2 14 HCF1305-1R0 1.15 22 HC5-1R0 1.3 27 Series Capacitor value(µF) Rated voltage (V) C4532X5R1E156M 15 25 C3225X5R0J107M 100 6.3 NIPPON CHEMI-CON 25PS100MJ12 100 25 PANASONIC ECJ4YB0J107M 100 6.3 COILTRONICS Table 8. Other capacitor manufacturer Manufacturer TDK Figure 21. Demoboard efficiency Fsw =400K H z fsw = 500kHz E F F IC IE N 9 5 .0 0 % 9 0 .0 0 % VIN = 5V 8 5 .0 0 % 8 0 .0 0 % VIN = 12V 7 5 .0 0 % 1 3 5 7 9 I o u t (A ) 28/36 11 13 15 L6732 L6732 demoboards Figure 22. Top layer Figure 23. Power ground layer Figure 24. Signal-ground layer Figure 25. Bottom layer 29/36 L6732 L6732 demoboards 7.2 5A board description and PCB layout L6732 5A demoboard realizes in a two layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5V to 14V and the output voltage is at 3.3V. The module can deliver an output current of up to 5A. The switching frequency is set at 250KHz (controller free-running FSW) but it can be set to 500KHz acting on the EAREF pin. Compared to the 20A version, the only difference of this board, compared to the first one, is the presence of a dual mosfet chip, for the High-side and Low-side Mosfets; besides R15 has been inserted between High side mosfet Gate and Phase pin; R14 has been inserted between Low side mosfet Gate and Pgnd pin. Table 9. 30/36 Demoboard part list Reference Value Manufacturer Package Supplier R1 1kΩ Neohm SMD 0603 IFARCAD R2 1kΩ Neohm SMD 0603 IFARCAD R3 4K7 R4 2k7 Neohm SMD 0603 IFARCAD R5 0Ω Neohm SMD 0603 IFARCAD R6 N.C. Neohm SMD 0603 IFARCAD R7 4K99 Neohm SMD 0603 IFARCAD R8 10Ω Neohm SMD 0603 IFARCAD R9 2K49 Neohm SMD 0603 IFARCAD R10 2.2Ω Neohm SMD 0603 IFARCAD R11 2.2Ω Neohm SMD 0603 IFARCAD R12 N.C. Neohm SMD 0603 IFARCAD R13 10K Neohm SMD 0603 IFARCAD R14 N.C. Neohm SMD 0603 IFARCAD R15 N.C. Neohm SMD 0603 IFARCAD C1 4.7nF Kemet SMD 0603 IFARCAD C2 47nF Kemet SMD 0603 IFARCAD C3 1nF Kemet SMD 0603 IFARCAD C4 100nF Kemet SMD 0603 IFARCAD C5 100nF Kemet SMD 0603 IFARCAD C6 N.C. / / / C7 100nF Kemet SMD 0603 IFARCAD C8 4.7uF 20V AVX SMA6032 IFARCAD C9 1nF Kemet SMD 0603 IFARCAD C10 1uF Kemet SMD 0603 IFARCAD L6732 L6732 demoboards Table 9. Demoboard part list Reference Value Manufacturer Package Supplier C11 220nF Kemet SMD 0603 IFARCAD C12-13 3X 10uF / / ST (TDK) C15 N.C. / / / C16-19 2X 330uF / / ST (poscap) L1 2,7uH DO3316P-272HC Coilcraft SMD ST D1 STPS1L30M ST DO216AA ST D3 STPS1L30M ST DO216AA ST Q1 STS8DNH3LL (Dual Mosfet) ST SO8 ST U1 L6732 ST HTSSOP16 ST Figure 26. Demoboard efficiency 31/36 L6732 demoboards Figure 27. Top layer Figure 28. Power ground layer 32/36 L6732 L6732 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 33/36 L6732 Package mechanical data Figure 29. HTSSOP16 mechanical data TSSOP16 EXPOSED PAD MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A 1.2 A1 0.15 A2 0.8 b TYP. MAX. 0.047 0.004 0.006 0.039 0.041 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5.1 0.193 D1 1 MIN. 5 3.0 0.197 0.201 0.118 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.5 0.169 0.173 0.177 E2 3.0 0.118 e 0.65 0.0256 K 0° L 0.45 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 7419276A 34/36 L6732 9 Revision history Revision history Table 10. Revision history Date Revision Changes 20-Dec-2005 1 Initial release 24-Jan-2006 2 Improved description of Soft-Start, in case of Pre-bias Start-Up 29-May-2006 3 New template, thermal data updated 26-Jun-2006 4 Note page 10 deleted 25-Sep-2006 5 New DemoBoards Section 7: L6732 demoboards on page 26 35/36 L6732 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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